KR101602332B1 - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention provides a plasma display panel comprising first and second substrates facing each other and spaced apart from each other; A gate wiring and a data wiring formed on the first substrate and defining a pixel region intersecting with each other; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor and formed in the pixel region; A first link wiring connected to the data wiring; A drive integrated circuit connected to the first link wiring; A second link wiring connected to the drive integrated circuit; A ground shield pattern formed on at least one of an upper portion and a lower portion of the second link wiring so as to cover the second link wiring; And a flexible printed circuit connected to the second link wiring.

Link wiring, ground shielding pattern, EMC

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

The present invention relates to a liquid crystal display device and more particularly to a liquid crystal display device in which a shielding ground pattern is formed on at least one of upper and lower portions of a link wiring for transmitting a signal to prevent electrostatic discharge through a link wiring and interference And an external signal from being interfered with, and a method of manufacturing the liquid crystal display device.

2. Description of the Related Art Generally, a liquid crystal display device has advantages of small size, thinness and low power consumption, and is used in a notebook computer, office automation equipment, audio / video equipment and the like. Particularly, an active matrix type liquid crystal display device in which a thin film transistor (Thin Film Transistor) is used as a switching element is suitable for displaying a dynamic image.

In recent years, a liquid crystal display device has been used as a display means of a mobile terminal, and a gate and a data driving integrated circuit (D-IC) have been mounted on one substrate of a liquid crystal panel A chip on glass (COG) type liquid crystal display device is often used.

1 is a view showing a conventional COG type liquid crystal display device.

As shown in Fig. 1, the liquid crystal display 10 includes a liquid crystal panel 20 and a flexible printed circuit (FPC) Although not shown, a backlight unit may be disposed under the liquid crystal panel 20.

The liquid crystal panel 20 includes first and second substrates 30 and 40 spaced apart from each other and a liquid crystal layer (not shown) formed between the first and second substrates 30 and 40.

A plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn are formed on the first substrate 30 so as to intersect with each other and define a pixel region P.

The pixel region P includes a thin film transistor T connected to a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn, a storage capacitor Cst connected to the thin film transistor T, A capacitor Clc is formed.

A COG type driving integrated circuit 50 and a flexible printed circuit 60 are attached to the edge of the first substrate 30 which is a non-display area.

The driving integrated circuit 50 is connected to the plurality of data lines DL1 to DLn through the plurality of first link lines 52 and connected to the flexible printed circuit 60 through the plurality of second link lines 54. [ do.

Further, although not shown, the driving integrated circuit 50 is also connected to a plurality of gate lines GL1 to GLm.

That is, the driving integrated circuit 50 is connected to a plurality of gate lines GL1 to GLm to supply a gate signal, and is connected to a plurality of data lines DL1 to DLn through a plurality of first link lines 52 And supplies the data signal.

The driving integrated circuit 50 is connected to the flexible printed circuit 60 through a plurality of second link wirings 54 and receives a power signal from the external system (not shown), a driving integrated circuit control signal D An IC control signal, a high-speed serial interface (HSSI) signal, and an RGB signal.

Here, the power supply signal includes Vci, VCC, VDD, IOVCC and the like, and the driving IC control signal includes RESET, RS, chip select (CS), read (RD) The signal includes a mobile display digital interface (MDDI) and a mobile industry processor interface (MIPI) pair signal.

That is, the driving integrated circuit 50 receives a power supply signal, a driving IC control signal, a high-speed serial interface signal, and the like from an external system to generate a gate signal and a data signal to generate a plurality of gate lines GL1 to GLm, To the wirings DL1 to DLn.

Here, the plurality of second link wirings 54 connecting the flexible printed circuit 60 and the drive integrated circuit 50 are formed in the same layer as at least one of the gate wirings and the data wirings formed on the first substrate 30 Which will be described with reference to the drawings.

Figs. 2A to 2C are cross-sectional views taken along the line II-II in Fig. 1, in which a plurality of second link wirings 54 are formed in the same layer as the gate wirings, the same layer as the gate wirings and the data wirings, .

2A, a plurality of second link wirings 54 made of a metal material are formed on the first substrate 30, and an organic or inorganic insulating material is formed on the plurality of second link wirings 54 The gate insulating film 34 and the protective layer 44 are continuously formed.

A first metal layer 54a made of a first metal material is formed on the first substrate 30 and a gate insulating film made of an organic or inorganic insulating material is formed on the first metal layer 54a 34 are formed.

A second metal layer 54b made of a second metal material and having a pattern shape corresponding to the first metal layer 54a is formed on the gate insulating film 34. The first and second metal layers 54a and 54b are formed of a plurality of And a second link wiring 54 of the second wiring layer 54 to transmit various signals.

A protective layer 44 is formed on the second metal layer 54b.

2C, a gate insulating film 34 made of organic or inorganic insulating material is formed on the first substrate 30 and a plurality of second link wirings (not shown) made of a metal material are formed on the gate insulating film 34 And a protective layer 44 is formed on the plurality of second link wirings 54.

As described above, the plurality of second link wirings 54 can be formed as a single layer in the same layer as the gate wiring, a double layer in the same layer as the gate wiring and the data wiring, or a single layer in the same layer as the data wiring.

However, the signal transmission path from the external system to the driving integrated circuit 50 includes a plurality of resistance components, for example, the contact resistance between the flexible printed circuit 60 and the external system, the contact resistance between the flexible printed circuit 60 The contact resistance between the flexible printed circuit 60 and the first substrate 30, the wiring resistance of the plurality of second link wirings 54, the contact resistance between the drive integrated circuit 50 and the first substrate 30, The internal resistance of the driving integrated circuit 50, and the like.

The plurality of second link wirings 54 have the largest resistance and thus the plurality of second link wirings 54 have electromagnetic compatibility EMC due to electrostatic discharge (ESD) The most vulnerable.

Here, the electrostatic discharge (ESD) means that static electricity accumulated in thousands to tens of thousands of volts is rapidly discharged due to contact or the like, and the electric elements and the like may be damaged by such electrostatic discharge.

Electromagnetic compatibility (ESD) can be classified into electromagnetic interference (EMI) and electromagnetic susceptibility (EMS). Electromagnetic interference (EMI) is a phenomenon in which electromagnetic waves generated from an electric device are emitted to the outside Conduction noise and radiation noise, and the electromagnetic immunity (EMS) means the degree to which the electric element can withstand the adverse effects of external electromagnetic waves.

The signals transmitted from the external system to the driving integrated circuit 50 through the plurality of second link wirings 54 are transferred from the driving integrated circuit 50 through the plurality of first wiring wirings 52 to the plurality of gate wirings 52. [ Unlike the gate signal and the data signal transmitted to the data lines GL1 to GLm and the plurality of data lines DL1 to DLn, a high-power power supply signal, a control signal for fine control of the driving integrated circuit 50, Interface signals, the plurality of second link wires 54 may be further susceptible to electrostatic discharge and electromagnetic compatibility.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems as described above, and it is an object of the present invention to provide a liquid crystal display device in which a ground shielding pattern is formed on at least one of upper and lower portions of a link wiring of a liquid crystal display device, A display device and a method of manufacturing the same are provided.

Further, according to the present invention, by forming a ground shielding pattern on at least one of the upper and lower portions of the link wiring of a liquid crystal display device, it is possible to prevent the damage of the link wiring and the drive integrated circuit due to the electrostatic discharge, Another object of the present invention is to provide a liquid crystal display device in which the noise is reduced and the signal transmitted to the link wiring is reduced, and a manufacturing method thereof.

According to an aspect of the present invention, there is provided a plasma display panel comprising: first and second substrates spaced apart from each other; A gate wiring and a data wiring formed on the first substrate and defining a pixel region intersecting with each other; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor and formed in the pixel region; A first link wiring connected to the data wiring; A drive integrated circuit connected to the first link wiring; A second link wiring connected to the drive integrated circuit; A ground shield pattern formed on at least one of an upper portion and a lower portion of the second link wiring so as to cover the second link wiring; And a flexible printed circuit connected to the second link wiring.

The second wiring line may be formed of the same material and the same material as the gate line, and the grounding shield pattern may be formed of the same material and the same material as at least one of the data line and the pixel electrode.

The second wiring line may be formed of the same material and the same material as the data line, and the grounding shield pattern may be formed of the same material and the same material as at least one of the gate line and the pixel electrode.

The second wiring line may be formed of a double layer of the same layer and the same material as the gate line and the data line, and the ground shielding pattern may be formed of the same material and the same material as the pixel electrode.

The signal transmitted to the second link wiring may be one of a power supply signal, a control signal of the drive integrated circuit, and a high-speed serial interface signal.

The thin film transistor includes a gate electrode formed on the first substrate and connected to the gate wiring, a gate insulating film formed on the gate electrode, and a semiconductor formed on the gate insulating film in correspondence to the gate electrode. And a source and drain electrode formed on the semiconductor layer and spaced apart from each other, wherein the gate insulating film and the ground shielding pattern are formed between the second link wiring and the ground shielding pattern, At least one of the protective layers may be interposed.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate wiring and a data wiring on a first substrate, Forming a thin film transistor connected to the gate wiring and the data wiring; Forming a pixel electrode connected to the thin film transistor in the pixel region; Forming first and second link wirings on edge portions of the first substrate; Forming a ground shielding pattern covering at least one of the upper and lower portions of the second link wiring line and grounding the second link wiring line; Attaching a drive integrated circuit to one end of the first and second link wirings; And attaching a flexible printed circuit to the other end of the second link wiring.

Here, the second link wiring may be formed simultaneously with the gate wiring, and the ground shielding pattern may be formed simultaneously with at least one of the data line and the pixel electrode.

The second wiring wiring may be formed simultaneously with the data wiring, and the ground shielding pattern may be formed simultaneously with at least one of the gate wiring and the pixel electrode.

Also, the second link wiring may be formed of a double layer formed simultaneously with the gate wiring and the data wiring, and the ground shielding pattern may be formed simultaneously with the pixel electrode.

According to the present invention having such characteristics, by forming a ground shielding pattern on at least one of the upper and lower portions of the link wiring connecting the flexible printed circuit and the drive integrated circuit of the liquid crystal display device, the electrostatic discharge and electromagnetic compatibility Improvement.

In addition, by forming the ground shielding pattern on at least one of the upper and lower portions of the link wiring connecting the flexible printed circuit and the drive integrated circuit of the liquid crystal display device, damage of the link wiring and the drive integrated circuit due to the electrostatic discharge is prevented, The noise to the signal transmitted to the wiring is reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

3 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 3, the liquid crystal display device 110 includes a liquid crystal panel 120 and a flexible printed circuit (FPC) 160. Although not shown, a backlight unit may be disposed under the liquid crystal panel 120.

The liquid crystal panel 120 includes first and second substrates 130 and 140 spaced apart from each other and a liquid crystal layer (not shown) formed between the first and second substrates 130 and 140.

A plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn are formed on the first substrate 130 so as to intersect with each other and define a pixel region P.

The pixel region P includes a thin film transistor T connected to a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn, a storage capacitor Cst connected to the thin film transistor T, A capacitor Clc is formed.

A plurality of first link wirings 152 and a plurality of second link wirings 154 are formed on the edge of the first substrate 130 which is a non-display area.

A COG type driving integrated circuit 150 and a flexible printed circuit 160 are attached to the edge of the first substrate 130.

The driving integrated circuit 150 is connected to the plurality of data lines DL1 to DLn through the plurality of first link lines 52 and connected to the flexible printed circuit 160 through the plurality of second link lines 154. [ do.

Although not shown, the driving integrated circuit 150 is also connected to a plurality of gate lines GL1 to GLm.

That is, the driving integrated circuit 150 is connected to a plurality of gate lines GL1 to GLm to supply a gate signal and is connected to a plurality of data lines DL1 to DLn through a plurality of first link lines 152 And supplies a data signal.

The driving integrated circuit 150 is connected to the flexible printed circuit 160 through a plurality of second link wirings 154 and receives a power signal from the external system (not shown), a driving integrated circuit control signal D An IC control signal, a high-speed serial interface (HSSI) signal, and an RGB signal.

Here, the power supply signal includes Vci, VCC, VDD, IOVCC and the like, and the driving IC control signal includes RESET, RS, chip select (CS), read (RD) The signal includes a mobile display digital interface (MDDI) and a mobile industry processor interface (MIPI) pair signal.

That is, the driving integrated circuit 150 receives a power signal, a driving IC control signal, a high-speed serial interface signal, etc. from an external system to generate a gate signal and a data signal, (GL1 to GLm) and a plurality of data lines (DL1 to DLn).

The plurality of second link wirings 154 connecting the flexible printed circuit 160 and the drive integrated circuit 150 are formed in the same layer as at least one of the gate wirings and the data wirings formed on the first substrate 130 .

At least one of the upper and lower portions of the plurality of second link wirings 154 is formed with a ground shielding pattern 156 having the same shape as the plurality of second link wirings 154, which will be described with reference to the drawings.

FIGS. 4A to 4C are cross-sectional views taken along a line IV-IV in FIG. 3, respectively, showing a ground shielding pattern according to another embodiment, and FIG. 5 is a cross-sectional view of the pixel region in FIG.

4A is a cross-sectional view illustrating a state in which a plurality of second link wirings 154 are formed of the same layer and the same material as the gate electrodes 132 of FIG. 5, and a plurality of ground shield patterns 156 are formed in the same manner as the pixel electrodes Layer, the same material.

4A, a plurality of second link wirings 154 made of a metal material are formed on the first substrate 130, and an organic or inorganic insulating material is formed on the plurality of second link wirings 154 The gate insulating film 134 and the protective layer 144 are continuously formed.

A plurality of ground shielding patterns 156 made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) are formed on the protection layer 144.

Here, the plurality of second link wirings 154 are formed of the same layer and the same material as the gate electrodes 132 and the plurality of gate wirings GL1 to GLm, and the plurality of ground shield patterns 156 are formed of the same material as the pixel electrodes 146 ), And the same material.

The plurality of ground shielding patterns 156 have the same shape as the plurality of second link wirings 154. The plurality of ground shielding patterns 156 are formed in the same shape as the plurality of second link wirings 154, ) May be formed to be equal to or greater than the second width w2. (w1? w2)

That is, the plurality of ground shield patterns 156 may be formed to cover the plurality of second link wirings 154 on the plurality of second link wirings 154.

The plurality of ground shield patterns 156 are grounded and may be connected to the ground terminal at the top of the first substrate 130 or may be connected to the ground terminal at an external system (not shown) through the flexible printed circuit 160 have.

Accordingly, the plurality of ground shield patterns 156 are surrounded and grounded by the plurality of second link wirings 154, so that a large number of second link wirings 154 (e.g., In particular, it is possible to prevent a charge from flowing into a wiring for transferring a drive IC control signal such as RESET and a power supply signal among a plurality of second link wirings 154, thereby preventing damage to the drive IC 150 .

In addition, radiation noise due to signals transmitted to the plurality of second link wires 154 is prevented, electromagnetic interference (EMI) characteristics are improved, and a plurality of second link wires 154 (EMS) characteristics are improved.

In particular, it prevents interference and distortion between signals transmitted to a plurality of second link wires 154, such as high-speed serial interface signals.

As a result, the electrostatic environment compatibility (EMC) characteristics of the plurality of second link wirings 154 are improved.

4B is a cross-sectional view showing a state in which a plurality of second link wirings 154 are formed in the same layer as the gate electrode (132 in FIG. 5), the first metal layer 154a made of the same material, and the source and drain electrodes And a plurality of ground shielding patterns 156 are formed of the same layer and the same material as that of the pixel electrode (146 in FIG. 5).

A first metal layer 154a made of a first metal material is formed on the first substrate 130 and a gate insulating film made of an organic or inorganic insulating material is formed on the first metal layer 154a 134 are formed.

A second metal layer 154b made of a second metal material and having a pattern shape corresponding to the first metal layer 154a is formed on the gate insulating layer 134. The first and second metal layers 154a and 154b are formed of a plurality of And transmits various signals.

A protection layer 144 is formed on the second metal layer 154b and a plurality of ground shield patterns 156 are formed on the protection layer 1440. [

The first metal layer 154a of the plurality of second link wirings 154 is formed of the same layer and the same material as the gate electrode 132 and the plurality of gate wirings GL1 to GLm, The second metal layer 154b of the first metal layer 154 is formed of the same layer and the same material as the source and drain electrodes 138 and 142 and the plurality of data lines DL1 to DLn, The same layer as the electrode 146, and the same material.

The plurality of ground shield patterns 156 have the same shape as the plurality of second link wirings 154. The first width w1 of the first metal layer 154a of the plurality of second link wirings 154 and the plurality The third width w3 of the plurality of ground shielding patterns 156 may be greater than or equal to the second width w2 of the second metal layer 154b of the second link wiring 154 of the first wiring layer 154. [ (w1? w3, w2? w3)

That is, the plurality of ground shield patterns 156 may be formed to cover the plurality of second link wirings 154 on the plurality of second link wirings 154.

Of course, the plurality of ground shielding patterns 156 may be connected to the ground terminal at the top of the first substrate 130 or may be connected to the ground terminal at an external system (not shown) through the flexible printed circuit 160 to be grounded .

Accordingly, the plurality of ground shield patterns 156 are surrounded and grounded by the plurality of second link wirings 154, so that a large number of second link wirings 154 (e.g., In particular, it is possible to prevent a charge from flowing into a wiring for transferring a drive IC control signal such as RESET and a power supply signal among a plurality of second link wirings 154, thereby preventing damage to the drive IC 150 .

In addition, radiation noise due to signals transmitted to the plurality of second link wires 154 is prevented, electromagnetic interference (EMI) characteristics are improved, and a plurality of second link wires 154 (EMS) characteristics are improved.

In particular, it prevents interference and distortion between signals transmitted to a plurality of second link wires 154, such as high-speed serial interface signals.

As a result, the electrostatic environment compatibility (EMC) characteristics of the plurality of second link wirings 154 are improved.

4C shows a case where a plurality of second link wirings 154 are formed of the same layer and the same material as the source and drain electrodes 138 and 142 of FIG. 5, and a plurality of ground shield patterns 156 are formed on the gate electrode The first pattern 156a of the same material and the second pattern 156b of the same layer and the same material as that of the pixel electrode (146 of FIG. 5).

4C, a first pattern 156a made of a first metal material is formed on the first substrate 130, and a gate insulating film (not shown) made of an organic or inorganic insulating material is formed on the first pattern 156a 134 are formed.

A plurality of second link wirings 154 made of a second metal material are formed on the gate insulating layer 134 and a protective layer 144 is formed on the plurality of second link wirings 154.

A second pattern 156b made of a transparent conductive material is formed on the protection layer 144. The first and second patterns 156a and 156b constitute a plurality of ground shield patterns 156, respectively.

The first pattern 156a of the plurality of ground shield patterns 156 is formed of the same layer and the same material as the gate electrode 132 and the plurality of gate lines GL1 to GLm, 154 are formed of the same layer and the same material as the source and drain electrodes 138 and 142 and the plurality of data lines DL1 to DLn and the second pattern 156b of the plurality of ground shielding patterns 156 is formed of the same layer, The same layer as the first layer 146 and the same material.

The plurality of ground shield patterns 156 have the same shape as the plurality of second link wirings 154. The second width w2 of the first pattern 156a of the plurality of ground shield patterns 156 and the ground width The third width w3 of the second pattern 156b of the pattern 156 may be formed to be equal to or greater than the first width w1 of the plurality of second link wirings 154. [ (w1? w2, w1? w3)

That is, the plurality of ground shield patterns 156 may be formed to cover the plurality of second link wirings 154 at upper and lower portions of the plurality of second link wirings 154.

Of course, the plurality of ground shielding patterns 156 may be connected to the ground terminal at the top of the first substrate 130 or may be connected to the ground terminal at an external system (not shown) through the flexible printed circuit 160 to be grounded .

Accordingly, the plurality of ground shield patterns 156 are surrounded and grounded by the plurality of second link wirings 154, so that a large number of second link wirings 154 (e.g., In particular, it is possible to prevent a charge from flowing into a wiring for transferring a drive IC control signal such as RESET and a power supply signal among a plurality of second link wirings 154, thereby preventing damage to the drive IC 150 .

In addition, radiation noise due to signals transmitted to the plurality of second link wires 154 is prevented, electromagnetic interference (EMI) characteristics are improved, and a plurality of second link wires 154 (EMS) characteristics are improved.

In particular, it prevents interference and distortion between signals transmitted to a plurality of second link wires 154, such as high-speed serial interface signals.

As a result, the electrostatic environment compatibility (EMC) characteristics of the plurality of second link wirings 154 are improved.

5, regarding the cross section of the pixel region P of the liquid crystal display device 110, a gate electrode 132 of a first metal material is formed on the first substrate 130, A gate insulating film 134 made of an inorganic or organic insulating material is formed on the electrode 132.

A semiconductor layer 136 of a semiconductor material is formed on the gate insulating layer 134 corresponding to the gate electrode 132 and source and drain electrodes 138 and 138 of a second metal material are formed on the semiconductor layer 136, 142 are formed.

A protective layer 144 of inorganic or organic insulating material is formed on the source and drain electrodes 138 and 142 and a pixel electrode 146 of a transparent conductive material is formed on the protective layer 144.

The gate electrode 132, the semiconductor layer 136, the source electrode 138 and the drain electrode 142 constitute a thin film transistor T and the pixel electrode 146 is connected to the drain electrode 142 through the contact hole of the protective layer 144. [ (Not shown).

Although not shown, the gate electrode 132 is connected to each of a plurality of gate wirings (GL1 to GLm in Fig. 3), and the source electrode 138 is connected to each of a plurality of data wirings (DL1 to DLn in Fig. 3).

In the structure shown in FIG. 4A, a ground shielding pattern composed of the same layer and the same material as the source and drain electrodes may be added. In the structure shown in FIG. 4C, one of the first and second patterns may be omitted .

Although not shown, a plurality of second link wirings may be formed of the same layer and the same material as the pixel electrodes, and the ground shielding pattern may be formed as a single layer of the same layer and the same material as the gate electrode, It may be formed of the same material and a double layer of the same layer and the same material as the source and drain electrodes.

6 is an equivalent circuit diagram of a second link wiring and a ground shielding pattern of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 6, a plurality of second link wirings 154 connected to a signal source SS of an external system (not shown) is composed of an equivalent resistance Req and an equivalent capacitor Ceq.

A plurality of grounding shield patterns 156 composed of first and second patterns 156a and 156b and grounded are connected to both ends of the signal source SS and the plurality of second link wiring lines 154. [

Here, the plurality of ground shield patterns 156 are formed of the first and second patterns 156a and 156b, but they may be formed of one of the first and second patterns 156a and 156b in other embodiments .

The signal source SS and the plurality of second link wirings 154 are electrically connected to the signal source SS and the plurality of second link wirings 154 by electrostatic discharge (EMI) characteristics and electromagnetic immunity (EMS) characteristics of a large number of second link wirings 154 can be protected against shocks such as sudden charge inflow by electrostatic discharge (ESD).

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

1 is a view showing a conventional COG type liquid crystal display device.

Figures 2a-2c are cross-sectional views along line II-II in Figure 1;

3 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

Figures 4A-4C are cross-sectional views along line IV-IV in Figure 3;

5 is a cross-sectional view of the pixel region of FIG. 3;

6 is an equivalent circuit diagram of a second link wiring and a ground shielding pattern of a liquid crystal display device according to an embodiment of the present invention.

Claims (11)

First and second substrates spaced apart from each other; A gate wiring and a data wiring arranged on the first substrate and defining a pixel region crossing each other; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor and disposed in the pixel region; A first link wiring connected to the data wiring; A drive integrated circuit connected to the first link wiring; A second link wiring connected to the drive integrated circuit; A ground shielding pattern disposed on at least one of the upper and lower portions of the second link wiring and having the same shape as the second link wiring and overlapped with the second link wiring and being grounded; And a flexible printed circuit connected to the second link wiring And the liquid crystal display device. The method according to claim 1, Wherein the second wiring line is formed of the same material and the same material as the gate line, and the ground shielding pattern is formed of the same material as at least one of the data line and the pixel electrode. The method according to claim 1, Wherein the second wiring line is formed of the same material and the same material as the data line, and the ground shielding pattern is formed of the same material and the same material as at least one of the gate line and the pixel electrode. The method according to claim 1, Wherein the second wiring line is formed of a double layer of the same layer and the same material as the gate line and the data line, and the ground shielding pattern is formed of the same layer and the same material as the pixel electrode. The method according to claim 1, Wherein the signal transmitted to the second link wiring is one of a power supply signal, a control signal of the drive integrated circuit, and a high-speed serial interface signal. The method according to claim 1, The thin film transistor includes a gate electrode disposed on the first substrate and connected to the gate wiring, a gate insulating film disposed on the gate electrode, a semiconductor layer disposed on the gate insulating film in correspondence to the gate electrode, A protective layer disposed on the semiconductor layer; and source and drain electrodes disposed on the semiconductor layer and spaced apart from each other, And at least one of the gate insulating film and the protective layer is interposed between the second link wiring and the ground shielding pattern. Forming gate wirings and data wirings crossing each other on the first substrate to define pixel regions; Forming a thin film transistor connected to the gate wiring and the data wiring; Forming a pixel electrode connected to the thin film transistor in the pixel region; Forming first and second link wirings on edge portions of the first substrate; Forming a ground shielding pattern on at least one of the upper and lower sides of the second link wiring, the ground shield pattern having the same shape as the second link wiring and overlapped with the second link wiring and being grounded; Attaching a drive integrated circuit to one end of the first and second link wirings; Attaching a flexible printed circuit to the other end of the second link wiring And the second electrode is electrically connected to the second electrode. 8. The method of claim 7, The second wiring line is formed at the same time as the gate line, and the ground shielding pattern is formed simultaneously with at least one of the data line and the pixel electrode. 8. The method of claim 7, Wherein the second wiring line is formed simultaneously with the data line, and the grounding shield pattern is formed simultaneously with at least one of the gate line and the pixel electrode. 8. The method of claim 7, Wherein the second wiring line is composed of a double layer formed simultaneously with the gate wiring and the data line, and the ground shielding pattern is formed simultaneously with the pixel electrode. The method according to claim 1, Wherein a width of the ground shielding pattern is greater than or equal to a width of the second link wiring.

Images