KR101604492B1 - Liquid Crystal Display device - Google Patents

Abstract

A liquid crystal display device is disclosed.

The LOG signal line formed in the link portion of the non-display region of the liquid crystal display panel is formed as a double metal layer made of a first metal and a second metal formed on a layer different from the first metal, The cross-sectional area of the line can be increased to minimize the distortion of the drive signals and the control signals provided to the LOG signal line by the line resistance, thereby improving the display quality.

A double metal layer, a contact hole, a line on glass (LOG) signal line,

Description

[0001] The present invention relates to a liquid crystal display device,

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing a load of a LOG line disposed in a link portion of a non-display region of a liquid crystal display panel, thereby improving a transmission efficiency of a scan signal and a power source.

In recent years, liquid crystal display devices have been manufactured in small to medium size, and are used for devices such as a GPS system capable of navigating to passenger cars as well as airplanes, ships, and devices that allow users to carry multimedia media such as images, music and videos.

Such a liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal display panel in which liquid crystal cells are arranged in a matrix by controlling light transmittance of liquid crystal cells according to a video signal. To this end, a liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and a driving circuit for driving the liquid crystal display panel.

The driving circuit includes a gate driver for supplying a scan signal to a gate line of the liquid crystal display panel, and a data driver for supplying a data signal to the data line of the liquid crystal display panel. At this time, the data driver and the gate driver are integrated into a plurality of drive IC chips (integrated circuit chips).

Each of the integrated data drive IC chip and the gate drive IC chip is mounted on a TCP (Tape Carrier Package) according to a method of mounting the integrated data drive IC chip and the gate drive IC chip on a liquid crystal display device, and is connected to a liquid crystal display panel by TAB (Tape Automated Bonding) There is a COG (Chip On Glass) method in which a drive IC chip is mounted directly on the substrate.

In recent years, signal lines connected to drive IC chips are formed on a glass substrate by a LOG (Line On Glass) method in order to further thin the liquid crystal display device by minimizing the size of the PCB. The signal lines connected to the drive IC chips are mounted on the thin film transistor array substrate by the LOG method to remove the printed circuit board and further thin the liquid crystal display panel.

In particular, signal lines connected to gate drive ICs requiring relatively few signal lines are formed on a thin film transistor array substrate by a LOG method, and thus a method of removing a gate printed circuit board is widely used.

In the case of the LOG method in which the gate printed circuit board is removed, the gate drive ICs control signals from a timing controller and a power supply unit mounted on a data printed circuit board through LOG signal lines formed on the thin film transistor array substrate, Voltages.

The LOG signal lines are formed on a non-display area of the liquid crystal display panel, and the LOG signal lines are formed using a mask process in the same manner as a plurality of gate lines and data lines formed on the liquid crystal display panel. Since the LOG signal lines supplied with the control signals and the driving voltages from the data PCB and supplied to the gate drive IC formed on the thin film transistor array substrate are formed to fit the limited area of the non-display area, Is difficult to secure sufficiently. This causes distortion of a plurality of control signals and driving voltages supplied to the gate drive IC through the LOG signal line, thereby degrading the display quality of the liquid crystal display panel.

The LOG signal lines formed in the link portion of the non-display region of the liquid crystal display panel are formed as a double metal layer to increase the cross-sectional area of the LOG signal line so that control signals provided to the LOG signal line by the line resistance, And it is an object of the present invention to provide a liquid crystal display device capable of minimizing voltage distortion.

It is another object of the present invention to provide a liquid crystal display device capable of improving display quality.

The liquid crystal display according to the present invention includes a liquid crystal display panel divided into a display region in which liquid crystal cells are arranged in a matrix form and a non-display region except for the display region, A plurality of data driver integrated circuits located on the other side of the non-display area and driving the plurality of data lines; and a driver circuit for supplying driving signals and driving voltages to the gate and data driver integrated circuits A flexible printed circuit board that is disposed between the flexible printed circuit board and the non-display area of the liquid crystal panel, the flexible printed circuit board and the flexible printed circuit board, And a driving voltage to the first gate driver integrated circuit among the plurality of gate driver integrated circuits And a second LOG signal line formed between the plurality of gate driver integrated circuits formed in the non-display area to provide a drive signal and a drive voltage provided from the first gate driver integrated circuit to a next gate driver integrated circuit Signal lines, and the second LOG signal lines are formed of a dual structure including first and second metal layers.

The LOG signal line formed in the link portion of the non-display region of the liquid crystal display panel is formed as a double metal layer made of a first metal and a second metal formed on a layer different from the first metal, The cross-sectional area of the line can be increased to minimize the distortion of the drive signals and the control signals provided to the LOG signal line by the line resistance, thereby improving the display quality.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, A gate driver 110 for supplying a scan signal to the gate lines GL1 to GLn and a data line DL1 to DLm for supplying a scan signal to the gate lines GL1 to GLn, A timing controller 130 for controlling the gate driver 110 and the data driver 120 and a gate voltage generating unit 130 for supplying a gate voltage to the gate driver 110. [ And a common voltage generator 150 for supplying a common voltage to the common electrode of the liquid crystal display panel 100.

In the liquid crystal display panel 100, liquid crystal is formed between two glass substrates, and a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other on the lower glass substrate. The thin film transistors TFT formed at the intersections of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm are connected to the data lines DL1 to DLn in response to scan signals from the gate lines GL1 to GLn, DLm to the liquid crystal cell Clc.

To this end, the gate electrode of the thin film transistor TFT is connected to the gate lines GL1 to GLn, and the source electrode thereof is connected to the data lines DL1 to DLm. The drain electrode of the thin film transistor TFT is connected to the pixel electrode of the liquid crystal cell Clc.

A storage capacitor Cst for holding the voltage of the liquid crystal cell Clc is formed on the lower glass substrate of the liquid crystal display panel 100. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the previous gate line or may be formed between the liquid crystal cell Clc and another common line.

On the upper glass substrate of the liquid crystal display panel 100, color filters of R, G, and B colors corresponding to the respective pixel regions where the thin film transistors (TFT) are formed, and the gate lines GL1 to GLn, A black matrix for covering the data lines DL1 to DLm and the thin film transistors (TFT), and a common electrode covering both of them.

The gate driver 110 correspondingly supplies a plurality of scan signals to the plurality of gate lines GL1 to GLn in response to a gate control signal GCS from the timing controller 130. [ The plurality of scan signals cause the plurality of gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronous signal period. The gate driver 110 may include a plurality of gate driver integrated circuits.

In response to the data control signals DCS from the timing controller 130, the data driver 120 generates a plurality of pixel data voltages each time one of the plurality of gate lines GL1 to GLn is enabled And supplies them to the plurality of data lines DL1 to DLm on the liquid crystal display panel 100, respectively. The data driver 120 may include a plurality of data driver ICs.

The timing controller 130 receives synchronization signals (Vsync, Hsync) supplied from an external system (for example, a graphics module of a computer system or a video demodulation module of a television receiving system, not shown) A gate control signal GCS for controlling the gate driver 110 and a data control signal DCS for controlling the data driver 120 are generated using a clock signal DE and a clock signal CLK.

In addition, the timing controller 130 arranges image data (Data) input from an external system and supplies the aligned data to the data driver 120. [

The gate voltage generator 140 generates a gate voltage using the power supply voltage Vdd supplied from a power supply unit (not shown) and supplies the gate voltage to the gate driver 110.

The common voltage generator 150 generates a common voltage Vcom using the power supply voltage Vdd supplied from the power supply unit and supplies the common voltage Vcom to the common electrode of the liquid crystal display panel 100 Supply.

The timing controller 130 and the gate voltage generator 140 and the common voltage generator 150 may be connected to the power supply unit 130 and the common voltage generator 150 on a data printed circuit board (not shown) on which the data driver 120 is mounted. Can be disposed.

Fig. 2 is a schematic view showing a part of the liquid crystal display device of Fig. 1. Fig.

1 and 2, a liquid crystal display device includes a liquid crystal display panel 100 in which a plurality of gate lines GL and a plurality of data lines DL are arranged, 1), a gate voltage generator (140 in FIG. 1) and a common voltage generator (150 in FIG. 1) arranged in the timing controller (130 in FIG. 1) And a data printed circuit board 124 attached to one surface of the liquid crystal display panel 100.

The liquid crystal display panel 100 includes a thin film transistor array substrate 101 and a color filter substrate 103.

Gate lines GL arranged to be spaced apart from each other in a horizontal direction and data lines DL arranged to be uniformly spaced apart in a vertical direction cross each other on the thin film transistor array substrate 101, GL) and the data line DL are defined. The pixels are arranged on the thin film transistor array substrate 101 in a matrix form.

In the non-display region of the TFT array substrate 101, first and second gate driver integrated circuits 110a and 110b for supplying a scan signal to the plurality of gate lines GL are formed.

A color filter substrate (103) is provided with red, green and blue color filters at positions corresponding to the pixels, and a black matrix for preventing color interference of light passing through the color filter And a common electrode for applying an electric field to the liquid crystal layer together with the pixel electrode of the thin film transistor array substrate is formed.

A pixel electrode and a common electrode are provided on an inner surface of the thin film transistor array substrate 101 opposite to the color filter substrate 103. The liquid crystal molecules of the liquid crystal layer are driven by a voltage difference between the pixel electrode and the common electrode, The luminance of the image displayed on the liquid crystal display panel 100 is changed according to the size of the image information applied to the pixels.

At this time, the liquid crystal display panel 100 and the data printed circuit board 124 are electrically and physically connected to each other through a flexible printed circuit (FPC)

A first data driver integrated circuit 120a constituting the data driver 120 shown in FIG. 1 is mounted on the data printed circuit board 124 and a plurality of data driver ICs 120a electrically connected to the plurality of data lines DL A data link line 125 is formed.

The plurality of data link lines 125 are disposed between an output terminal of the first data driver IC 120a and a data line DL of the liquid crystal display panel 100 and are connected to the first data driver IC 120a And the plurality of data lines DL are electrically connected to each other.

A first LOG signal line 160 is formed on the data printed circuit board 124 and the flexible printed circuit board 128. The first LOG signal line 160 extends from the data printed circuit board 124 and the flexible printed circuit board 128 to one edge of the non-display area of the thin film transistor array substrate 101. The first LOG signal line 160 formed at one edge of the non-display region of the thin film transistor array substrate 101 is electrically connected to the first gate driver integrated circuit 110a.

A second LOG signal line 170 located between the first and second gate driver integrated circuits 110a and 110b is formed in the non-display region of the thin film transistor array substrate 101. [

The first LOG signal line 160 receives control signals and a clock signal from a timing controller (130 in FIG. 1) mounted on the data printed circuit board 124. The first LOG signal line 160 is connected to a gate voltage from the gate voltage generator 140 (FIG. 1) mounted on the data printed circuit board 124, a power supply voltage from a power supply (not shown) Ground voltage, and the like.

The first LOG signal line 160 provides various signals (control signals and clock signal) and driving voltages (gate voltage, power supply voltage and ground voltage) to the first gate driver integrated circuit 110a, And drives the gate line GL electrically connected to the gate driver integrated circuit 110a. At the same time, the first LOG signal line 160 supplies the various signals and the driving voltage to the second LOG signal line 170 electrically connected to the first gate driver integrated circuit 110a.

The second LOG signal line 170 is formed between the first gate driver integrated circuit 110a and the second gate driver integrated circuit 110b. Specifically, the second LGO signal line 170 is connected to the gate line GL for electrically connecting the first and second gate driver ICs 110a and 110b and the gate line GL of the liquid crystal display panel 100, (115) is located. At this time, due to the limited area of the gate link portion, the second LOG signal line 170 may be composed of a double metal layer.

FIG. 3 is a cross-sectional view of the second LOG signal line of FIG. 2. FIG.

2 and 3, the second LOG signal line 170 includes a first metal layer 170a formed on the thin film transistor array substrate 101, a gate insulating layer 170b formed on the first metal layer 170a, A second metal layer 170b formed on the gate insulating layer 105 and electrically connected to the first metal layer 170a and a protective layer 107 formed on the second metal layer 170b. ).

The first metal layer 170a of the second LOG signal line 170 is formed through the same process as the gate line GL of the liquid crystal display panel 100 of FIG. Are formed through the same process using the same material as the data lines DL of the liquid crystal display panel 100. [

The first metal layer 170a is etched to expose a portion of the gate insulating layer 105 formed on the first metal layer 170a to expose a portion of the second metal layer 170b As shown in Fig.

The second LOG signal line 170 of the double metal layer is formed in the same process as the pixel region of the liquid crystal display panel 100. After the protective layer 107 is formed, A part of the gate insulating layer 105 may be etched to expose a portion of the gate insulating layer 105 to electrically connect the first and second metal layers 170a and 170b.

If the second LOG signal line 170 formed in the gate link unit having a limited area is formed of a double metal layer, the thickness of the second LOG signal line 170 becomes thicker than that of the conventional LOG signal line, . When the cross-sectional area of the second LOG signal line 170 increases, various signals (a control signal and a clock signal) provided through the first LOG signal line 160 and the first gate driver integrated circuit 110a according to the line resistance, And the distortion of the driving voltage (gate voltage, power supply voltage, and ground voltage) are reduced.

Thus, the liquid crystal display device according to the present invention can improve the display quality of the liquid crystal display panel 100. In addition, the liquid crystal display according to the present invention is capable of controlling various signals (control signal and clock signal) and driving voltages (gate voltage, power supply voltage, and ground voltage) provided to the first and second LOG signal lines 160 and 170 The transmission efficiency can be improved.

4 is a cross-sectional view of the second LOG signal line of FIG. 2 formed in accordance with another embodiment.

2 and 4, the second LOG signal line 270 according to another embodiment includes a first metal layer 270a formed on the thin film transistor array substrate 101 and a second metal layer 270b formed on the first metal layer 270a A gate insulating layer 205 formed on the entire surface of the substrate 101 on which the gate insulating layer 205 is formed, a protective layer 207 formed on the gate insulating layer 205, And a second metal layer 270b electrically connected to the second metal layer 270a.

The first metal layer 270a of the second LOG signal line 270 is formed of the same material as the gate line GL of the liquid crystal display panel 100 of FIG. 2 through the same process, and the second metal layer 270b Are formed through the same process using the same material as the pixel electrodes included in the pixel region of the liquid crystal display panel 100. [

A portion of the first metal layer 270a of the second LOG signal line 270 is exposed through the etching process to the gate insulating layer 205 and the protective layer 207 sequentially formed on the first metal layer 270a And is electrically connected to the second metal layer 270b formed on the passivation layer 207 through the exposed portion.

If the second LOG signal line 270 formed in the gate link unit having a limited area is formed of a double metal layer including the first and second metal layers 270a and 270b electrically connected to each other, And the cross-sectional area is increased. As the cross-sectional area of the second LOG signal line 270 increases, various signals (control signals) provided through the first LOG signal line (160 in FIG. 2) and the first gate driver integrated circuit (110a in FIG. 1) Signal and clock signal) and the driving voltage (gate voltage, power supply voltage, and ground voltage).

Thus, the liquid crystal display device according to the present invention can improve the display quality of the liquid crystal display panel 100. In addition, the liquid crystal display device according to the present invention is capable of controlling various signals (control signal and clock signal) and driving voltages (gate voltage, power supply voltage, and ground voltage) provided to the first and second LOG signal lines 160 and 270 The transmission efficiency can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention. FIG.

Fig. 2 is a schematic view showing a part of the liquid crystal display device of Fig. 1; Fig.

3 is a cross-sectional view of the second LOG signal line of FIG. 2;

4 is a cross-sectional view of the second LOG signal line of FIG. 2 formed in accordance with another embodiment;

Claims (7)

A liquid crystal display panel divided into a display region in which liquid crystal cells are arranged in a matrix form and a non-display region except for the display region; A plurality of gate driver integrated circuits located at one side of the non-display area and driving a plurality of gate lines; A plurality of data driver integrated circuits located on the other side of the non-display area and driving a plurality of data lines; A printed circuit board providing a driving signal and a driving voltage to the gate and data driver integrated circuit; A flexible printed circuit board relaying between the liquid crystal display panel and the printed circuit board; A first LOG which is disposed over the printed circuit board, the flexible printed circuit board and the non-display area of the liquid crystal display panel and provides the drive signal and the drive voltage to the first gate driver integrated circuit among the plurality of gate driver integrated circuits; Signal lines; And And a second LOG signal line disposed between the plurality of gate driver integrated circuits disposed in the non-display area to provide a drive signal and a drive voltage provided from the first gate driver integrated circuit to a next gate driver integrated circuit and, The second LOG signal lines are a dual structure including first and second metal layers, Wherein the first metal layer of the second LOG signal line is made of the same material as the plurality of gate lines and the second metal layer is made of the same material as the plurality of data lines, Further comprising an insulating layer between the first and second metal layers of the second LOG signal line, Wherein the first and second metal layers of the second LOG signal line are electrically connected to each other by exposing a portion of the insulating layer. delete delete delete The method according to claim 1, And the second LOG signal line is disposed in a link portion where gate line lines connecting the plurality of gate lines and the plurality of gate driver integrated circuits among the non-display regions are arranged. A liquid crystal display panel divided into a display region in which liquid crystal cells are arranged in a matrix form and a non-display region except for the display region; A plurality of gate driver integrated circuits located at one side of the non-display area and driving a plurality of gate lines; A plurality of data driver integrated circuits located on the other side of the non-display area and driving a plurality of data lines; A printed circuit board providing a driving signal and a driving voltage to the gate and data driver integrated circuit; A flexible printed circuit board relaying between the liquid crystal display panel and the printed circuit board; A first LOG which is disposed over the printed circuit board, the flexible printed circuit board and the non-display area of the liquid crystal display panel and provides the drive signal and the drive voltage to the first gate driver integrated circuit among the plurality of gate driver integrated circuits; Signal lines; And And a second LOG signal line disposed between the plurality of gate driver integrated circuits disposed in the non-display area to provide a drive signal and a drive voltage provided from the first gate driver integrated circuit to a next gate driver integrated circuit and, The second LOG signal lines are a dual structure including first and second metal layers, Wherein the first metal layer of the second LOG signal line is made of the same material as the plurality of gate lines and the second metal layer is made of the same material as the pixel electrode of the pixel region of the liquid crystal display panel, A gate insulation layer and a protection layer are sequentially disposed on a first metal layer of the second LOG signal line, And the first and second metal layers are electrically connected by exposing a part of the gate insulating layer and the protective layer of the second LOG signal line. The method according to claim 6, And the second LOG signal line is disposed in a link portion where gate line lines connecting the plurality of gate lines and the plurality of gate driver integrated circuits among the non-display regions are arranged.

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