KR101592936B1 - Low noise amplifier - Google Patents

Abstract

An embodiment of the present invention relates to a low noise amplifier.
A low noise amplifier according to an embodiment of the present invention includes: an input terminal; A gain cell electrically connected to the input terminal; A source follower electrically coupled to the gain cell; An output terminal electrically connected to the source follower; And a variable resistor electrically coupled between a node between the input terminal and the gain cell and a node between the source follower and the output terminal, the gain cell comprising: a common terminal for receiving an input signal from the input terminal; A gain section including a source section and a common drain section, and an inhibiting section electrically connected to the common drain section and for canceling an even-order harmonic distortion of the gain section, A bias voltage terminal for generating a bias voltage, a first resistor electrically connected to the bias voltage terminal at one end thereof, a second resistor electrically connected at one end to the bias voltage terminal, a first PMOS transistor having a gate electrically connected to the other end of the first resistor, A transistor (P-channel Metal Oxide Semiconductor Transistor) and a gate connected to the other end of the second resistor To include a first PMOS transistor 2 are connected.

Description

[0001] LOW NOISE AMPLIFIER [0002]

The present invention relates to a low noise amplifier.

A low noise amplifier (LNA) is a type of amplification circuit that serves to amplify a weak signal that is picked up by an antenna in a communication system.

As wireless communication technology evolves to broadband and high efficiency data transmission service, the frequency band of wireless transceiver is widening, and therefore, there is a need for a high performance low noise amplifier that satisfies all the performance of low noise, high linearity, and wide band operation have.

In particular, in the case of the digital television tuner cable standard, 137 channels are received in a wide band ranging from 48 to 860 MHz while 2 channels of other channels coexisting in the band due to the non-linearity of the receiver front- The combination of the difference and the third order components is converted into the reception channel frequency, which lowers the system noise ratio (signal noise ratio), which ultimately deteriorates the reception sensitivity.

Therefore, improving the linearity of the low noise amplifier constituting the front end of the receiver has become an important technical problem in a wideband receiver.

The present invention provides a low noise amplifier in which the loop gain is improved and the linearity is improved.

A low noise amplifier according to an embodiment of the present invention includes: an input terminal; A gain cell electrically connected to the input terminal; A source follower electrically coupled to the gain cell; An output terminal electrically connected to the source follower; And a variable resistor electrically coupled between a node between the input terminal and the gain cell and a node between the source follower and the output terminal, the gain cell comprising: a common terminal for receiving an input signal from the input terminal; A gain section including a source section and a common drain section and a suppression section electrically connected to the common drain section and for canceling even-order harmonic distortion of the gain section, A bias voltage terminal for generating a bias voltage, a first resistor electrically connected to the bias voltage terminal at one end thereof, a second resistor electrically connected at one end to the bias voltage terminal, a first PMOS transistor having a gate electrically connected to the other end of the first resistor, A transistor (P-channel Metal Oxide Semiconductor Transistor) and a gate connected to the other end of the second resistor To include a first PMOS transistor 2 are connected.

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Wherein the common source section includes: an inverting input terminal electrically connected to a node between the gate of the first PMOS transistor and the first resistor; A non-inverting input terminal electrically coupled to a node between the gate of the second PMOS transistor and the second resistor; A first NMOS transistor (N-channel Metal Oxide Semiconductor Transistor) having a gate electrically connected to the inverting input terminal; And a second NMOS transistor having a gate electrically connected to the non-inverting input terminal; . ≪ / RTI >

Here, the common drain section may include: a third NMOS transistor having a gate electrically connected to the inverting input terminal; A fourth NMOS transistor having a gate electrically connected to the non-inverting input terminal; A non-inverting output terminal electrically coupled to a drain of the first PMOS transistor, a source of the fourth NMOS transistor, and a drain of the first NMOS transistor; And an inverting output terminal electrically coupled to a drain of the second PMOS transistor, a source of the third NMOS transistor, and a drain of the second NMOS transistor; . ≪ / RTI >

Here, the gain cell may include a control unit electrically connected to the gain unit. Wherein the control section comprises: a third resistor electrically connected to the source of the first NMOS transistor; a fourth resistor electrically coupled to the source of the second NMOS transistor; and a third resistor electrically connected between the third resistor and the fourth resistor. Connected switches.

Here, the common source portion may be a common-source amplifier (CS), and the common drain portion may be a common-drain amplifier (CD).

The low noise amplifier according to the embodiment of the present invention has an advantage that the loop gain can be improved and the linearity can be improved.

1 is a circuit diagram of a low noise amplifier according to the first embodiment.
2 is a circuit diagram of the first gain cell and the second gain cell shown in FIG.
3 is a circuit diagram of a low-noise amplifier according to the second embodiment.
4 is a circuit diagram of the third gain cell shown in Fig.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

In the description of the embodiments according to the present invention, in the case where an element is described as being formed "on or under" another element, the upper (upper) or lower (lower) (On or under) all include that the two elements are in direct contact with each other or that one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

Hereinafter, a low-noise amplifier according to an embodiment of the present invention will be described with reference to the accompanying drawings.

Hereinafter, the low-noise amplifier 10 according to the first embodiment will be described with reference to Figs. 1 and 2. Fig.

≪ First Embodiment >

1 is a circuit diagram of a low noise amplifier according to the first embodiment.

Referring to FIG. 1, the low-noise amplifier 10 according to the first embodiment may be a two-stage hunt feedback LNA. Specifically, the low-noise amplifier 10 according to the first embodiment includes an input terminal V _IN , a first gain cell A ₁ , a second gain cell A ₂ , an output terminal V _OUT , And includes a first variable resistor R _F1 and a second variable resistor R _F2 .

The input terminal V _IN can receive the input signal. The input terminal V _IN includes a non-inverting input terminal V _IN + and an inverting input terminal V _IN- .

The first gain cell A ₁ includes a first non-inverting input terminal (+), a first inverting input terminal (-), a first inverting output terminal (-) and a first non-inverting output terminal (+). First gain cell (A ₁₎ a first non-inverting input terminal (+) is the first inverting input terminal of being electrically connected to the non-inverting input terminal (V _IN +), the first gain cell (A ₁₎ of the (-) is It is electrically connected to the inverting input terminal (V _IN -).

The second gain cell A ₂ includes a second inverting input terminal (-), a second non-inverting input terminal (+), a second non-inverting output terminal (+), and a second inverting output terminal (-). A second inverting input terminal of the gain cell (A ₂₎ (-) is first inverted output terminal of the first gain cell (A ₁₎ - second and is electrically connected to the second gain cell (A ₂₎ () The non-inverting input (+) is electrically connected to the first non-inverting output (+) of the first gain cell (A ₁ ).

The output terminal (V _OUT ) can output an output signal corresponding to the received input signal. The output terminal (V _OUT ) includes a non-inverted output terminal (V _OUT +) and an inverted output terminal (V _OUT -). The non-inverting output terminal V _OUT + is electrically connected to the second non-inverting output terminal (+) of the second gain cell A ₂ and the inverting output terminal V _OUT- is electrically connected to the second gain cell A ₂ . And the second inverting output terminal (-).

The first variable resistor R _F1 is connected between the first node N ₁ between the non-inverting input terminal V _IN + and the first non-inverting input terminal (+) of the first gain cell A ₁ , Inverting output terminal (+) of the second non-inverting output terminal (A ₂ ) and the second node (N ₂ ) between the non-inverting output terminal (V _OUT +).

The second variable resistor R _F2 is connected between the third node N ₃ between the inverting input terminal V _IN- and the first inverting input terminal (-) of the first gain cell A ₁ and the second node N ₃ between the second gain cell A ₂₎ a second inverting output (- is electrically coupled between the fourth node (N ₄₎ between a)) and the inverted output terminal (V _OUT.

The low noise amplifier 10 according to the first embodiment amplifies the first and second gain cells A ₁ and A 2 in proportion to the loop gain size using the first and second variable resistors R _F1 and R _F2 . A ₂ ) can be suppressed.

2 is a circuit diagram of the first gain cell and the second gain cell shown in FIG.

Referring to FIG. 2, the first gain cell A ₁ and the second gain cell A ₂ shown in FIG. 1 may include a common source portion 110 and a common drain portion 120.

The common source portion 110 may operate as a common-source amplifier (CS). Here, the source common amplifier is an amplifier in which an input signal is applied between a gate and a source, and an output signal is obtained between a drain and a source.

The common source unit 110 includes an inverting input V _in- , a non-inverting input V _in +, a first capacitor C ₁ , a second capacitor C ₂ , a first transistor M ₁ , A transistor M ₂ and a ground GRD.

The inverting input terminal V _in- is connected to the first inverting input terminal (-) of the first gain cell A ₁ shown in FIG. 1 or the second inverting input terminal (-) of the second gain cell A ₂ shown in FIG. ). Therefore, the inverting input (V _in -) is electrically connected to the inverting input terminal (V _IN -) shown in FIG. 1, or the first inverting output (-) of the first gain cell (A ₁ ) As shown in FIG.

A second non-inverting non-inverting input terminal (V _in +) is the first gain cell (A ₁₎ a first non-inverting input terminal (+) or the second gain cell (A ₂₎ shown in Figure 1 shown in Figure 1 May be an input (+). Thus, the inverting input terminal (V _in -) includes a first non-inverting output terminal of the non-inverting input terminal (V _IN +) with or electrically connected to, or the first gain cell (A ₁₎ shown in Figure 1 shown in Figure 1 (+).

The first end of the capacitor (C ₁₎ is the inverting input terminal (V _in -) being connected to and electrically, the second end of the capacitor (C ₂₎ are electrically connected to the non-inverting input terminal (V _in +).

The gate of the first transistor M ₁ is electrically connected to the other terminal of the first capacitor C ₁ and the gate of the second transistor M ₂ is electrically connected to the other terminal of the second capacitor C ₂ .

Ground (GRD) is connected to the electrical source and the source of the first transistor (M ₁₎ and a second transistor (M _2).

The common drain portion 120 can operate as a common-drain amplifier (CD). Here, the drain common amplifier is an amplifier in which an input signal is applied between a gate and a drain, and an output signal is obtained between a source and a drain.

The common drain part 120 includes a third capacitor C ₃ , a fourth capacitor C ₄ , a third transistor M ₃ , a fourth transistor M ₄ , an inverting output terminal V _out - (V _out +).

One end of the third capacitor C ₃ is electrically connected to the first node N ₁ between the inverting input terminal V _in- and the first capacitor C ₁ and one end of the fourth capacitor C ₄ is electrically connected to the first node N ₁ , And is electrically connected to the second node N ₂ between the non-inverting input (V _in +) and the second capacitor (C ₂ ).

The gate of the third transistor M ₃ is electrically connected to the other terminal of the third capacitor C ₃ and the gate of the fourth transistor M ₄ is electrically connected to the other terminal of the fourth capacitor C ₄ .

A third transistor (M ₃₎ electrically connected to the source and drain of the second transistor (M ₂₎ and, a non-inverting output terminal (V _out +) of the fourth transistor (M ₄₎ - inverted output terminal (V _out) And the drain of the first transistor M ₁ .

Here, the first to fourth transistors M ₁ , M ₂ , M ₃ , and M ₄ may be NMOS transistors (N-channel Metal Oxide Semiconductor Transistors).

In this manner, the first gain cell (A ₁₎ and the second gain cell (A ₂₎ is a first transistor the fourth transistor is non-linear component generated in the transconductance (trans conductance, gm1) of (M ₁₎ (M ₄₎ Is suppressed to a nonlinear component occurring in the transconductance (gm2) of the input signal and reduces the odd-order harmonic distortion component. Therefore, there is an advantage that the linearity of the gain cell can be improved because the odd harmonic distortion component is reduced.

However, the suppression of the nonlinear component mainly occurs only in the third component, which is somewhat vulnerable to the second order interaction in which the second nonlinear component generates the third component through feedback.

The gain of the gain cell is a value (gm1 / gm2) obtained by dividing the transconductance gm1 of the common source unit 110 by the transconductance gm2 of the common drain unit 120. [ Therefore, in order to obtain a high gain, asymmetry of the transistors of the common source unit 110 and the transistors of the common drain unit 120 is inevitable.

However, if the transconductance of the transistor of the common source part 110 is changed (by increasing gm1) or the transconductance of the transistor of the common drain part 120 is changed (by lowering gm2) for the asymmetry, A voltage drop occurs in the transistor and it is difficult to improve the gain of the gain cell.

Therefore, the low-noise amplifier 10 according to the first embodiment can not improve the loop gain, so it is difficult to improve the linearity from the feedback.

Hereinafter, the low-noise amplifier 20 according to the second embodiment, which improves the problem of the low-noise amplifier 10 according to the first embodiment, will be described with reference to Figs. 3 and 4. Fig.

≪ Second Embodiment >

3 is a circuit diagram of a low-noise amplifier according to the second embodiment. Here, among the components of the low-noise amplifier 20 shown in FIG. 3, the same reference numerals are used for the same components as those of the low-noise amplifier 10 shown in FIG. Therefore, the description of the same reference numerals will be omitted.

3, the low-noise amplifier 20 according to the second embodiment includes an input terminal V _IN , a third gain cell A ₃ , a fourth gain cell A ₄ , an output terminal V _OUT , And includes a first variable resistor R _F1 and a second variable resistor R _F2 .

The third gain cell A ₃ includes a third non-inverting input (+), a third inverting input (-), a third inverting output (-) and a third non-inverting output (+). A third inverting input terminal of the third gain cell (A _3), the third non-inverting input terminal (+) is the non-inverting input terminal (V _IN +) and being electrically connected to the third gain cell (A ₃₎ of the (-) is It is electrically connected to the inverting input terminal (V _IN -).

The fourth gain cell A ₄ may be a source follower. Also, although not shown in FIG. 3, the fourth gain cell A ₄ may be a gain cell such as the third gain cell A ₃ . Here, the source follower is a circuit in which the signal inputted to the gate is outputted to the source side.

The fourth gain cell A ₄ includes a fourth inverting input terminal (-), a fourth non-inverting input terminal (+), a fourth non-inverting output terminal (+), and a fourth inverting output terminal (-). 4 with and electrically connected to the fourth gain cell (A ₄₎ a fourth gain cell (A ₄₎ a fourth inverting input terminal of the (-) is a third inverting output of the third gain cell (A ₃₎ () non-inverting input terminal (+) is connected to a third non-inverting output (+) and the electrical gain of the third cell (a _3).

4 is a circuit diagram of the third gain cell shown in Fig.

3, the third gain cell A ₃ shown in FIG. 3 includes a gain unit 210 for receiving an input signal and outputting the input signal, and an even-harmonic distortion component (even and an inhibiting unit 220 for canceling an out-of-order harmonic distortion.

The gain section 210 may include a common source section 211 and a common drain section 212.

The common source portion 211 can operate as a source common type amplifier. Here, the source common amplifier is an amplifier in which an input signal is applied between a gate and a source, and an output signal is obtained between a drain and a source.

The common source portion 211 includes an inverting input V _in -, a non-inverting input V _in +, a first NMOS transistor M _1N , and a second NMOS transistor M _2N .

The inverting input (V _in -) receives the non-inverting signal included in the input signal.

The non-inverting input (V _in +) receives the inverting signal included in the input signal.

The first gate of the NMOS transistor (M _1N) is the inverting input terminal (V _in -) being electrically connected to the second gate of the NMOS transistor (M _2N) is electrically connected to the non-inverting input terminal (V _in +).

The common drain portion 212 can operate as a drain common type amplifier. Here, the drain common amplifier is an amplifier in which an input signal is applied between a gate and a drain, and an output signal is obtained between a source and a drain.

The common drain portion 212 includes a third NMOS transistor M _3N , a fourth NMOS transistor M _4N , an inverted output terminal V _out - and a non-inverted output terminal V _out +.

The third gate of the NMOS transistor (M _3N) is the inverting input terminal (V _in -) being connected to the electrical and the fourth gate of the NMOS transistor (M _4N) is electrically connected to the non-inverting input terminal (V _in +).

The inverting output terminal V _out - is electrically connected to the source of the third NMOS transistor M _3N and is electrically connected to the drain of the second NMOS transistor M _2N .

The non-inverting output terminal V _out + is electrically connected to the source of the fourth NMOS transistor M _4N and is electrically connected to the drain of the first NMOS transistor M _1N .

The common drain portion 212 may further include a first capacitor C ₁ , a second capacitor C ₂ , a first resistor R ₁ and a second resistor R ₂ .

The first capacitor C ₁ is electrically connected between the inverting input terminal V _in- and the gate of the third NMOS transistor M _3N and the second capacitor C ₂ is electrically connected between the non-inverting input terminal V _in + And may be electrically connected between the gates of the fourth NMOS transistor M _4N .

One end of the first resistor R ₁ is electrically connected to a node between the gates of the first capacitor C ₁ and the third NMOS transistor M _3N and a power is supplied to the other end of the first resistor R ₁ do. One end of the second resistor R ₂ is electrically connected to a node between the gates of the second capacitor C ₂ and the fourth NMOS transistor M _4N and the other end of the second resistor R ₂ is electrically connected to the power source .

Reduction unit 220 includes a bias voltage terminal (V _b), a third resistor (R _3), the fourth resistance (R _4), of claim 1 PMOS transistor (P channel Metal Oxide Semiconductor Transistor, M _1P) and a 2 PMOS transistor (M _2P ).

Bias voltage terminal (V _b) generates a bias voltage.

One end of the third resistor R ₃ is electrically connected to the bias voltage terminal V _b .

One end of the fourth resistor R ₄ is electrically connected to the bias voltage terminal V _b .

The gate of the first PMOS transistor M _1P is electrically connected to the other end of the third resistor R ₃ and the drain of the first PMOS transistor M _1P is electrically connected to the non-inverting output terminal V _out + .

The gate of the second PMOS transistor M _2P is electrically connected to the other end of the fourth resistor R ₄ and the drain of the second PMOS transistor M _2P is electrically connected to the inverted output terminal V _out- do.

An inverting input (V _in -) is electrically connected to a node between the gate of the first PMOS transistor (M 1 _P ) and the third resistor (R ₃ ). Here, a third capacitor C ₃ may be electrically connected between the gate of the first PMOS transistor M _1P and the inverting input terminal V _in -.

A non-inverting input terminal (V _in +) is electrically connected to a node between the gate of the second PMOS transistor (M _2P ) and the fourth resistor (R ₄ ). Here, a fourth capacitor C ₄ may be electrically connected between the gate of the second PMOS transistor M _2P and the non-inverting input terminal V _in +.

The third gain cell A ₃ may further include a control unit 230 electrically connected to the gain unit 210.

The control unit 230 includes a first current source I _B1 , a second current source I _B2 , a first resistor R _SD1 , and a second resistor R _SD2 .

The first current source I _B1 is electrically connected between the source of the first NMOS transistor M _1N and the ground GRD and the second current source I _B2 is electrically connected between the source of the second NMOS transistor M _2N and the ground RTI ID = 0.0 > (GRD). ≪ / RTI >

The first resistor R _SD1 is electrically connected to a node between the first current source I _B1 and the source of the first NMOS transistor M _1N and the second resistor R _SD2 is electrically connected to the second current source I _B2 , And the source of the second NMOS transistor _M2N . In addition, the first resistor (R _SD1) and a second resistor (R _SD2) between, the on / off a connection between the at least one switch is connected to the first resistor (R _SD1) and a second resistor (R _SD2) (ON / OFF).

Thus, the third gain cell A ₃ is turned on when the current I _1P of the first PMOS transistor M _1P is equal to the amount of the DC current flowing in the first NMOS transistor M _1N while the fourth NMOS transistor M _4N The current (I _4N ) of the current I 1 _N is naturally reduced. Therefore, even if the transconductance gm2 of the transistor of the common drain part 212 is lowered, no voltage drop occurs. Therefore, the third gain cell A ₃ can improve the gain of the third gain cell A ₃ by lowering the transconductance gm 2 of the transistor of the common drain portion 212 without a voltage drop.

Also, since the third gain cell A ₃ does not affect the output impedance because the drain of the first PMOS transistor M _1P is electrically connected to the non-inverting output terminal V _out +, the third gain cell A 3 ₃ ) can be improved.

Therefore, the low-noise amplifier 20 according to the second embodiment has an advantage that the linearity is improved from the feedback because the loop gain can be improved as compared with the second and third gain cells shown in Fig.

Also, in the low-noise amplifier 20 according to the second embodiment, the first PMOS transistor M _1P and the first NMOS transistor M _1N can operate as an inverter-type amplifier. Here, the inverter-type amplifier is an amplifier having an effect of suppressing an even harmonic distortion component like a differential amplifier.

The low-noise amplifier 20 according to the second embodiment including the inverter-type amplifier has a structure in which the even harmonic distortion component falls to the same frequency as the odd harmonic distortion component due to the second-order interaction so that the odd harmonic distortion component It is possible to prevent the amount from increasing.

Therefore, since the low-noise amplifier 20 according to the second embodiment prevents the amount of odd harmonic distortion components from being increased, there is an advantage that the gain of the amplifier can be higher than that of the low-noise amplifier 10 according to the first embodiment.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood that various changes and modifications may be made without departing from the spirit and scope of the invention. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

210: Gain section 211: Common source section
212: Common drain part 220:
230:

Claims (6)

An input terminal;
A gain cell electrically connected to the input terminal;
A source follower electrically coupled to the gain cell;
An output terminal electrically connected to the source follower; And
And a variable resistor electrically connected between a node between the input terminal and the gain cell and a node between the source follower and the output terminal,
Wherein the gain cell comprises:
A gain section including a common source section and a common drain section for receiving an input signal from the input terminal;
And an inhibiting unit electrically connected to the common drain unit and capable of canceling even-order harmonic distortion of the gain unit.
Wherein,
Bias voltage for generating bias voltage However,
A first resistor electrically connected to the bias voltage terminal at one end,
A second resistor electrically connected at one end to the bias voltage terminal,
A first PMOS transistor (P-channel Metal Oxide Semiconductor Transistor) having a gate electrically connected to the other end of the first resistor,
And a second PMOS transistor whose gate is electrically connected to the other end of the second resistor. delete The method according to claim 1,
The common source unit includes:
An inverting input terminal electrically coupled to a node between the gate of the first PMOS transistor and the first resistor;
A non-inverting input terminal electrically coupled to a node between the gate of the second PMOS transistor and the second resistor;
A first NMOS transistor (N-channel Metal Oxide Semiconductor Transistor) having a gate electrically connected to the inverting input terminal; And
And a second NMOS transistor whose gate is electrically connected to the non-inverting input. The method of claim 3,
The common-
A third NMOS transistor having a gate electrically connected to the inverting input terminal;
A fourth NMOS transistor having a gate electrically connected to the non-inverting input terminal;
A non-inverting output terminal electrically coupled to a drain of the first PMOS transistor, a source of the fourth NMOS transistor, and a drain of the first NMOS transistor; And
An inverting output terminal electrically connected to a drain of the second PMOS transistor, a source of the third NMOS transistor, and a drain of the second NMOS transistor; / RTI > 5. The method of claim 4,
Wherein the gain cell is electrically connected to the gain unit; Further comprising:
Wherein,
A third resistor electrically coupled to the source of the first NMOS transistor,
A fourth resistor electrically coupled to the source of the second NMOS transistor and
And a switch coupled between the third resistor and the fourth resistor. 6. The method according to any one of claims 1 to 5,
The common source portion is a common-source amplifier (CS)
Wherein the common drain portion is a common-drain amplifier (CD).

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