KR101580472B1 - Method for manufacturing a circuit board - Google Patents

Abstract

The present invention forms a two-layer embedded trace substrated (ETS) circuit by forming a built-in circuit on a carrier copper foil, laminating an insulating layer and a copper foil, separating the core, processing a cavity to incorporate passive elements, And an image process is carried out to form a three-layered substrate.

Description

[0001] METHOD FOR MANUFACTURING A CIRCUIT BOARD [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a printed circuit board (PCB) manufacturing technique, and more particularly, to a passive element embedded type coreless substrate manufacturing method. More particularly, the present invention relates to a three-layered package substrate having passive elements therein.

In recent years, the thickness of printed circuit boards has become thinner as electronic products have become shorter and thinner. As a result, the products which have conventionally been developed in four layers are being changed to three layers, and the copper foil circuit pattern to be manufactured on the board is becoming finer.

Further, instead of mounting the active element or the passive elements on the surface of the substrate, if the components are embedded in the printed circuit board, the degree of integration of the circuit can be increased and the parasitic component such as signal noise can be reduced. Has attracted the attention of the printed circuit board manufacturing industry.

1. Korean Patent Publication No. 10-2006-0005348. 2. Korean Patent Publication No. 10-2011-0011614. 3. Korean Patent Publication No. 10-2013-0003917. 4. Korean Patent Publication No. 10-2012-0134265.

It is an object of the present invention to provide a method of manufacturing a three-layer package substrate having a fine pitch circuit pattern and incorporating a passive element therein.

In order to achieve the above object, the present invention provides a two-layer ETS (embedded trace substrated) circuit by forming a built-in circuit on a carrier copper foil, laminating an insulating layer and a copper foil, separating the core, An insulating layer and a copper foil are laminated, and an image process is carried out to form a three-layered substrate.

The present invention has the advantage of increasing the circuit density and speeding up device operation speed by implementing a microcircuit pattern by the ETS method and embedding the parts in the substrate.

Figures 1a-1g illustrate a preferred embodiment of fabricating a two-layer ETS circuit in accordance with the present invention.
2A to 2H are views showing a method of manufacturing a circuit board according to the present invention.

(A) a first copper foil embedded and patterned on one surface of a first insulating layer; and a second copper foil formed on the opposite surface of the first copper foil, Forming a two-layer ETS circuit board composed of two copper foils; (b) forming a cavity through the first insulating layer of the ETS circuit board, attaching an adhesive film to one surface of the substrate, and pushing the component into the cavity and attaching the component to the adhesive film; (c) laminating a second insulating layer and a third copper foil on a surface opposite to the surface to which the adhesive film is adhered, followed by heat-press lamination, thereby embedding and mounting the component in the cavity; (d) removing the adhesive film, and drilling the second insulating layer to manufacture a second via hole connecting the terminal of the component or the second copper foil; And (e) copper plating to fill the second via hole, and selectively etching and pattern transferring the printed circuit board to form a circuit of a third layer.

Hereinafter, a method of manufacturing a passive element embedded type coreless package substrate according to the present invention will be described in detail with reference to FIGS. 1 and 2.

The present invention is characterized in that a micro circuit pattern is implemented by applying an embedded trace substation (ETS) method instead of using a conventional semi-additive process (SAP) or a modified semi-additive process (MSAP).

First, a built-in circuit is formed in the carrier copper foil, an insulating layer and a copper foil are laminated, and a core is separated to form a two-layer embedded trace substrated (ETS) circuit. Then, a cavity is formed in the ETS circuit of two layers to incorporate a passive element, an insulating layer and a copper foil are laminated, and an image process is performed to form a three-layer structure substrate.

1A to 1G are views showing a preferred embodiment of manufacturing a two-layer ETS circuit according to the present invention. 1A, a starting material is used as a material (hereinafter referred to as a detached core) in which carrier copper foil and base copper foil are coated on both sides of a core insulating layer.

1A, carrier copper foils 10b and 10d and base copper foils 10a and 10e are sequentially coated on both surfaces with a core insulating layer 10c interposed therebetween. As the core insulating layer 10c, an epoxy resin-based insulating material impregnated with a prepreg or fiber can be used.

An organic layer (not shown) or an adhesive layer is applied between the carrier copper foils 10b and 10d and the base copper foils 10a and 10e to bond the carrier copper foils 10b and 10d and the base copper foils 10a and 10e to each other The carrier copper foils 10b and 10d and the base copper foils 10a and 10e are detached when a slight physical force is applied.

Referring to FIG. 1B, a plating mask 20 is formed on both sides. The plating mask 20 is formed by coating a dry film (D / F) or the like according to a conventional technique and then carrying out a series of image processes such as photographing, developing and etching to transfer the pattern.

Referring to FIG. 1C, copper plating is performed in a state that the plating mask 20 is coated, thereby forming a first copper foil 30 on the base copper foils 10a and 10e. Then, after the first copper foil 30 is formed, the plating mask 20 is peeled and removed.

Referring to FIG. 1D, a first insulating layer 40 and a second copper foil 50 are laminated on both surfaces, and lamination is performed at a high temperature and a high pressure. 1E, the one surface and the side surface of the first copper foil 30 are embedded in the first insulating layer 40. As a result, As a result, unlike the prior art in which a circuit pattern protruding on the epoxy resin layer is formed, the present invention forms a circuit in the epoxy resin, so that the circuit pattern can be miniaturized (this is referred to as an ETS structure).

Referring to FIG. 1E, the first via hole 60 is processed by a laser drill or the like to expose the surface of the first copper foil 30 therein. Referring to FIG. 1F, copper plating is performed to fill the first via hole 60, and an image process is performed to transfer a circuit pattern to form a plating layer 70 electrically conductive with the first copper foil 30. Hereinafter, the copper plating layer additionally coated on the second copper foil 50 will be referred to as a second copper foil and denoted by reference numeral 70. [

Then, the carrier copper foils 10b and 10d are peeled off from the base copper foils 10a and 10e so as to be peeled from each other, thereby separating the structure of FIG. 2F into the core and the upper and lower structures. Referring to FIG. 1G, a circuit is formed by the first copper foil 30 on the base copper foil 10a and a circuit is formed by the second copper foil 70 thereon via the via hole 60, ETS circuit of two layers is completed.

The second copper foil 70 and the first copper foil 30 of FIG. 1G are made of the same material (copper (Cu)) and are connected to each other to form a substantially integrated structure. However, Hereinafter, different reference numerals are used in the drawings.

Hereinafter, a method of manufacturing a circuit board according to the present invention will be described in detail with reference to FIGS. 2A to 2H.

FIG. 2A shows the ETS circuit of the two layers obtained in FIG. 1G once again. Referring to FIG. 2B, a cavity 101 is formed by applying a laser drill or a mechanical drill method. The cavity 101 penetrates the first insulating layer 40.

Referring to FIG. 2C, the adhesive film 102 is attached to one surface of the substrate. As a preferred embodiment of the adhesive film according to the present invention, a polyimide (PI) film can be used. Referring to FIG. 2D, the component 103 is pushed into the cavity 101 and mounted to be adhered to the adhesive film 102. Here, the component 103 covers all of a semiconductor chip, an active element, a passive element such as an MLCC, and the like.

Referring to FIG. 2E, the second insulating layer 110 and the third copper foil 111 are sequentially stacked on the opposite side to which the adhesive film 102 is adhered, followed by lamination by heating and pressing. At this time, the resin flows out from the first insulating layer 40 and the second insulating layer 110 to fill the empty space in the cavity 101 and firmly fix the embedded part 103 during the curing process. Since the first insulating layer 40 and the second insulating layer 110 are integrated with each other, reference numerals 110 'will be used in the following description.

Referring to FIG. 2F, once the component 103 is firmly fixed in the cavity by the resin, the adhesive film 102 that has been used is removed. It should be noted that the drawings after FIG. 1F are shown reversed from the diagram of FIG. 1E.

Referring to FIG. 2G, the base copper foil 10a is etched by flash etching using a chemical solution, and the insulating layer 110 'is laser-drilled The second via holes connecting the electrodes of the inner layer circuit or the parts are formed and copper plating is carried out, and then the pattern is transferred according to the circuit pattern to manufacture the third layer copper circuit. Here, the copper foil plated on the third copper foil 111 is collectively referred to as the third copper foil 111. [ Finally, referring to FIG. 2H, a substrate according to the present invention is completed by printing a solder resist 120 on both sides of the substrate.

The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

A method of manufacturing a circuit board according to the present invention provides a three-layer package substrate having a fine pitch circuit pattern and a built-in passive element, thereby enabling high-speed device operation and mass production of high-density and high-quality products.

40: first insulating layer
110: second insulating layer
101: cavity
103: Parts
102: Adhesive film
120: Solder resist

Claims (4)

A method of manufacturing a three-layer circuit board having components embedded therein,
(a) a plating mask is coated on the surface of a detachable core in which carrier copper foil and base copper foil are sequentially coated on both surfaces with a core insulating layer interposed therebetween, copper plating is performed, and then the plating mask is removed to form a patterned first copper plating layer ;
(b) forming a first via hole exposing a surface of the first copper plating layer by laminating a first insulating layer and a second copper layer, followed by heat-press lamination, etching the second copper foil and the first insulating layer, The second copper plating layer is formed by selectively etching the copper foil so as to fill the first via hole and the copper copper foil is peeled off from the base copper foil to separate the copper foil from the base copper foil, Step of fabricating a layer ETS circuit board
(c) forming a cavity through the first insulating layer and the base copper foil on any one of the pair of two-layer ETS circuit boards, attaching an adhesive film to the surface of the base copper foil, pushing the component into the cavity, Adhering to the adhesive film;
(d) The second insulating layer and the third copper foil are laminated on the opposite side of the surface to which the adhesive film is adhered and heated and pressed to laminate the component in the cavity with the resin flowing out from the second insulating layer to fix step;
(e) peeling off the adhesive film, and drilling the third copper foil and the second insulating layer to manufacture a second via hole connecting the terminal of the component or the second copper foil; And
(f) a step of fabricating a circuit of the third layer by performing copper plating to fill the second via hole, selectively etching and transferring the pattern
≪ / RTI > delete delete The method of claim 1, further comprising printing solder resist on both sides of the substrate following step (f).

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