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KR101563642B1 - Stack Type Semiconductor Package - Google Patents

Stack Type Semiconductor Package Download PDF

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Publication number
KR101563642B1
KR101563642B1 KR1020080104543A KR20080104543A KR101563642B1 KR 101563642 B1 KR101563642 B1 KR 101563642B1 KR 1020080104543 A KR1020080104543 A KR 1020080104543A KR 20080104543 A KR20080104543 A KR 20080104543A KR 101563642 B1 KR101563642 B1 KR 101563642B1
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inner lead
chip
semiconductor package
die pad
lead element
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KR1020080104543A
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KR20100045566A (en
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황태성
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주식회사 아이티엠반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 적층형 반도체 패키지에 관한 것으로, 보다 상세하게는 적층된 칩과 이너 리드 사이의 와이어 본딩을 간편하게 할 수 있고 리드의 이탈을 방지할 수 있을 뿐만 아니라, 방열기능 또한 우수한 반도체 패키지에 관한 것이다. 본 발명의 적층형 반도체 패키지는 다이 패드에 부착되는 제 1 칩과, 상기 제 1칩 상면에 부착되는 제 2 칩과, 이너 리드의 선단이 상기 다이 패드보다 높은 위치에 형성되도록 절곡된 이너 리드가 수지밀봉부 내에 설치되며; 제 1 칩이 부착된 다이 패드의 면의 반대쪽 면이 수지밀봉부 외부로 노출되어 있는 것을 특징으로 한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked semiconductor package, and more particularly, to a semiconductor package which can easily perform wire bonding between a stacked chip and an inner lead, prevent lead detachment, and also has a heat dissipating function. The laminated semiconductor package of the present invention comprises a first chip attached to a die pad, a second chip attached to the upper surface of the first chip, and an inner lead bent so that the tip of the inner lead is formed at a position higher than the die pad, Is installed in the sealing portion; And the opposite face of the face of the die pad to which the first chip is attached is exposed to the outside of the resin sealing portion.

반도체 패키지, 이너 리드, 절곡 Semiconductor package, inner lead, bending

Description

적층형 반도체 패키지{Stack Type Semiconductor Package}[0001] The present invention relates to a stacked semiconductor package,

본 발명은 적층형 반도체 패키지에 관한 것으로, 보다 상세하게는 적층된 칩과 이너 리드(Inner Lead)사이의 와이어 본딩(Wire Bonding)을 간편하게 할 수 있고 리드(Lead)의 이탈을 방지할 수 있을 뿐만 아니라, 방열기능 또한 우수한 반도체 패키지에 관한 것이다.The present invention relates to a stacked semiconductor package, and more particularly, to a stacked semiconductor package which can simplify wire bonding between a stacked chip and an inner lead, And a semiconductor package excellent in heat radiation function.

최근 각종 휴대용 전자기기의 경박단소화 및 반도체 가공기술의 미세화에 따라 종래 단일 회로기능을 반도체 칩에 부여하였던 단기능 집적회로 단계에서 복수의 기능 시스템의 집적으로 확대되어 복수의 반도체 칩으로 단일 패키지를 형성하는 단계에 이르게 되었다. 2. Description of the Related Art [0002] In recent years, various types of portable electronic appliances have been developed to be miniaturized and miniaturized. As a result, .

복수의 반도체 칩을 단일 반도체 패키지 형태로 구성하게 되면 패키지 내부의 칩을 외부 환경으로부터 보호할 수 있을 뿐만 아니라, 프린터 기판에 실장할 때 공정수가 감소하며 정밀한 실장이 가능해지는 장점이 있다. When the plurality of semiconductor chips are formed in the form of a single semiconductor package, not only the chip inside the package can be protected from the external environment, but also the number of processes can be reduced when mounted on the printer substrate, thereby enabling the precise mounting.

하지만, 하나의 반도체 패키지 내부에 설치되는 전자부품 중에는 금속 산화막 반도체 전계 효과 트랜지스터(metal-oxide semiconductor field effect transistor, 이하 'MOSFET'라 함.)와 같이 발열량이 많은 전자부품이 포함될 수 있어 패키지 내의 다른 전자부품에도 고열에 의한 악영향을 미치게 된다. However, an electronic component installed in one semiconductor package may include an electronic component having a large heating value, such as a metal-oxide semiconductor field effect transistor (MOSFET) Electronic components are also adversely affected by high temperature.

또한, 반도체 칩이 적층된 구조를 가지게 됨에 따라 패키지의 강성이 실장되는 인쇄회로기판의 강성보다 강해져, 인쇄회로기판의 휨에 의해 아우터 리드의 인쇄회로기판과의 납땜결합이 손상되기도 하며, 이너 리드가 패키지의 수지밀봉부에서 이탈되는 경우도 많다.In addition, since the semiconductor chip has a laminated structure, the rigidity of the package becomes stronger than the rigidity of the printed circuit board on which the package is mounted, so that the solder bonding of the outer lead to the printed circuit board is damaged due to warping of the printed circuit board, Sealed portion of the package.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 반도체 패키지내의 고발열 소자의 열을 외부로 방출시켜 다른 소자에 미치는 열영향을 최소화하며 , 또한 반도체 패키지로부터 리드가 빠지지 않으면서 외부의 인쇄회로기판과도 확실한 접촉이 유지될 수 있는 적층형 반도체 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor package which can dissipate heat of a high- It is an object of the present invention to provide a stacked semiconductor package in which reliable contact with a substrate can be maintained.

본 발명의 적층형 반도체 패키지는The stacked semiconductor package of the present invention

다이 패드(Die Pad)에 부착되는 제 1 칩과,A first chip attached to a die pad,

상기 제 1칩 상면에 부착되는 제 2 칩과,A second chip attached to the upper surface of the first chip,

그 선단이 상기 다이 패드보다 높은 위치에 형성되도록 절곡된 이너 리드가 수지밀봉부 내에 설치되며;An inner lead bent in such a manner that its tip is formed at a position higher than the die pad is provided in the resin sealing portion;

제 1 칩이 부착된 다이 패드 면의 반대쪽 면이 수지밀봉부 외부로 노출되어 있는 것을 특징으로 한다. And the opposite surface of the die pad surface to which the first chip is attached is exposed to the outside of the resin sealing portion.

다이 패드에 제 1 칩을 부착할 때는 은(Ag) 함유량이 80%이상인 에폭시 재질의 접착제를 사용하며, 제 1 칩의 상면에 제 2 칩을 부착할 때는 테프론 재질의 접착제를 사용하는 것이 바람직하다. When attaching the first chip to the die pad, an epoxy adhesive having a silver (Ag) content of 80% or more is used. When attaching the second chip to the upper surface of the first chip, it is preferable to use an adhesive of Teflon .

상기 이너 리드의 선단에는 오목부와 볼록부 중 하나 이상이 형성되어 있는 것을 또 다른 특징으로 한다. And at least one of a concave portion and a convex portion is formed at the tip of the inner lead.

상기 아우터 리드의 단부에는 노치부를 구비하는 것이 바람직하다.It is preferable that a notch portion is provided at an end of the outer lead.

본 발명의 상기 구성에 따라, 반도체 패키지내의 고발열 소자의 열을 외부로 방출시켜 패키지 내의 다른 전자부품에 미치는 열영향을 최소화하며 , 또한 패키지로부터 리드가 빠지지 않고 외부의 인쇄회로기판과도 확실한 접촉이 유지될 수 있는 효과를 얻을 수 있다. According to the above-described structure of the present invention, the heat of the high heat-generating element in the semiconductor package is discharged to the outside to minimize the thermal influence on other electronic parts in the package, and the lead is not removed from the package, It is possible to obtain an effect that can be maintained.

이하, 본 발명을 그 실시예에 따라 도면을 참조하여 보다 상세하게 설명한다. Hereinafter, the present invention will be described in more detail with reference to the drawings in accordance with embodiments thereof.

도 1은 본 실시예에 인용되는 배터리 보호회로용 반도체 패키지 내부의 회로(점선 부분)를 나타낸 회로도이며, 도 2는 본 실시예의 적층 구조를 나타낸 것이다.Fig. 1 is a circuit diagram showing a circuit (dotted line portion) inside a semiconductor package for a battery protection circuit cited in this embodiment, and Fig. 2 shows a laminated structure of this embodiment.

도 1의 배터리 보호회로는 배터리의 과충전/과방전을 방지하기 위한 보호 IC(10)와 2개의 MOSFET(20)가 사용된다. In the battery protection circuit of Fig. 1, a protection IC 10 and two MOSFETs 20 are used to prevent over / over discharge of the battery.

2개의 MOSFET(20)는 제 1 칩으로 리드프레임의 다이 패드(30)의 상면에 부착된다. 제 1 칩을 다이 패드에 부착할 경우에는 은(Ag)의 함유량이 80%이상인 에폭시 재질의 접착제를 사용하는 것이 좋은데, 은(Ag)의 함유량이 80%이상이면 에폭시 수지재가 이루는 접착층의 열전달율이 우수하고, 그 이하인 경우에는 열전달율이 높지 않은 것으로 관찰되었다.Two MOSFETs 20 are attached to the top surface of the die pad 30 of the lead frame as a first chip. When the first chip is attached to the die pad, it is preferable to use an epoxy adhesive having a silver (Ag) content of 80% or more. If the silver (Ag) content is 80% or more, the heat transfer rate of the adhesive layer And the heat transfer rate was not high when the amount was less than the above value.

도 3은 본 실시예의 적층형 반도체 패키지를 뒤집어 바라본 사시도이며, 다이 패드(30)의 하면은 수지밀봉부(40) 외부로 노출되게 형성되어 있다. 이에 따라 MOSFET의 발열은 반도체 패키지 외부로 방출되게 되는 것이다.3 is a perspective view of the stacked semiconductor package according to the present embodiment. The lower surface of the die pad 30 is exposed to the outside of the resin sealing portion 40. As a result, the heat generated by the MOSFET is released to the outside of the semiconductor package.

제 1 칩인 2개의 MOSFET(20) 상면에는 제 2 칩인 보호IC(10)가 부착되게 된다. 제 2 칩과 제 1 칩을 접착시키기 위해 에폭시 재질의 접착제를 사용하게 되면, 접착시 발생하는 열팽창에 의해 제 1 칩의 표면이 손상되게 되는 문제점이 있다. 그러므로, 제 1 칩과 제 2 칩의 접착에는 테프론 재질의 접착제를 사용하는 것이 좋고, 테프론 재질의 접착재는 경화하여도 어느정도 탄성을 가지고 있어 제 1 칩이 다이 패드로 부터 통해 전달받을 수 있는 충격등을 완화시킬 수 있는 쿠션 역활을 하게 된다. The protection IC 10, which is the second chip, is attached to the upper surface of the two MOSFETs 20 as the first chip. If an epoxy adhesive is used to bond the second chip and the first chip, there is a problem that the surface of the first chip is damaged due to the thermal expansion occurring at the time of bonding. Therefore, it is preferable to use an adhesive of Teflon for bonding the first chip and the second chip, and the adhesive material of Teflon is somewhat resilient even when cured, so that the impact of the first chip can be transmitted through the die pad As a cushion that can alleviate the problem.

한편, 반도체 패키지의 리드 중 수지밀봉재 내부의 부분을 뜻하는 이너 리드(50)의 선단은 상기 다이 패드보다 높은 위치에 형성되도록 절곡되어 있다. 이 에 따라 제 1 칩/제 2 칩과 리드프레임으로 금선(gold wire)을 와이어 본딩할 때 본딩머신의 선단 이동거리를 단축시킬 수 있게 되며, 또한 리드가 수지밀봉부로부터 빠져나가려는 힘을 받게 되었을 때 절곡부는 이를 방지하는 역활도 하게 되는 것이다. On the other hand, the tip of the inner lead 50, which means a portion inside the resin sealing material in the lead of the semiconductor package, is bent to be formed at a position higher than the die pad. Accordingly, when the gold wire is wire-bonded to the first chip / second chip and the lead frame, the moving distance of the bonding machine can be shortened, and the lead is subjected to a force to escape from the resin sealing portion The bending portion also serves to prevent this.

또한 도 4와 같이 이너 리드(50)의 선단에 오목부(52)나 볼록부를 형성하고, 이러한 오목부나 볼록부가 수지밀봉부를 이루는 경화된 수지와 서로 협동하여 리드가 수지밀봉부로 부터 빠져나가는 것을 방지하는 것도 바람직하다. 4, a concave portion 52 and a convex portion are formed at the tip of the inner lead 50, and these concave portions or convex portions cooperate with the cured resin constituting the resin sealing portion to prevent the lead from escaping from the resin sealing portion .

상기 설명한 바와 같이 이너 리드(50)를 수지밀봉부 내에서 절곡하거나, 이너 리드 선단에 오목부(52)나 볼록부를 형성한 것에 의해, 반도체 패키지로부터 리드가 빠져나오는 일은 없어지게 되지만, 이 경우 인쇄회로기판에 납땜에 의해 반도체 패키지가 부착된 후 반도체 패키지가 뜻하지 않게 힘을 받아 납땜부위가 떨어지게 될 수도 있다. As described above, the inner lead 50 is bent in the resin sealing portion or the recess 52 or the convex portion is formed at the inner lead end, so that the lead does not come out from the semiconductor package. In this case, After the semiconductor package is attached by soldering to the circuit board, the semiconductor package may be subjected to an unintentional force and the soldering portion may be dropped.

이를 방지하기 위해서는 도 5에 도시한 바와 같이 수지밀봉부 외부로 돌출된 아우터 리드(60)에 노치부(62)를 가공함로써 납땜시 이러한 노치부를 따라 납이 확산되게 되므로 납땜의 젖음성 및 접착강도를 향상시킬 수 있게 되는 것이다. In order to prevent this, as shown in FIG. 5, when the notched portion 62 is formed on the outer lead 60 projecting out of the resin sealing portion, the lead is diffused along the notch portion during soldering, Can be improved.

도 1은 본 발명 실시예 반도체 패키지의 회로를 설명하기 위한 회로도.1 is a circuit diagram for explaining a circuit of a semiconductor package of an embodiment of the present invention.

도 2는 본 발명 실시예 반도체 패키지의 단면도2 is a cross-sectional view of an embodiment semiconductor package of the present invention

도 3은 본 발명 실시예 반도체 패키지의 하면을 나타낸 사시도.3 is a perspective view showing a bottom surface of a semiconductor package of an embodiment of the present invention.

도 4는 본 발명 실시예 이너 리드의 형태를 나타낸 부분 단면도.4 is a partial cross-sectional view showing an embodiment of the inner lead according to the present invention.

도 5는 본 발명 실시예 반도체 패키지의 사시도.5 is a perspective view of an example semiconductor package of the present invention.

** 도면의 주요부분에 대한 부호 설명 **[0001] Description of the Prior Art [0002]

10 : 제 2 칩, 보호 IC 20 : 제 1 칩, MOSFET10: second chip, protection IC 20: first chip, MOSFET

30 : 다이 패드 40 : 수지밀봉부 50 : 이너 리드 60 : 아우터 리드30: die pad 40: resin sealing portion 50: inner lead 60: outer lead

Claims (4)

다이 패드(Die Pad)에 부착되는 제 1 칩과,A first chip attached to a die pad, 상기 제 1칩 상면에 부착되는 제 2 칩과,A second chip attached to the upper surface of the first chip, 상기 다이 패드의 높이와 같거나 그 보다 낮은 위치에 설치되는 제1 이너 리드 요소, 상기 제1 이너 리드 요소로부터 연장하는 제2 이너 리드 요소, 및 상기 제2 이너 리드 요소로부터 연장하되 상기 다이 패드보다 높은 위치에 형성되는 제3 이너 리드 요소를 포함하는 이너 리드를 포함하고,A second inner lead element extending from the first inner lead element and a second inner lead element extending from the second inner lead element and extending from the die pad And an inner lead including a third inner lead element formed at a high position, 상기 이너 리드는 수지밀봉부 내에 설치되며;The inner lead is installed in the resin sealing portion; 상기 제 1 칩이 부착된 상기 다이 패드 면의 반대쪽 면이 상기 수지밀봉부 외부로 노출되어 있고,The opposite surface of the die pad surface to which the first chip is attached is exposed to the outside of the resin sealing portion, 상기 제1 이너 리드 요소와 상기 제2 이너 리드 요소는 제1 절곡부를 통해 이어지고,The first inner lead element and the second inner lead element extend through the first bent portion, 상기 제2 이너 리드 요소와 상기 제3 이너 리드 요소는 제2 절곡부를 통해 이어지는 것을 특징으로 하는 적층형 반도체 패키지.And the second inner lead element and the third inner lead element extend through the second bent portion. 제 1 항에 있어서, 상기 다이 패드에 제 1 칩을 부착할 때는 은(Ag) 함유량이 80%이상인 에폭시 재질의 접착제를 사용하며, 제 1 칩의 상면에 제 2 칩을 부착할 때는 테프론 재질의 접착제를 사용하는 것을 특징으로 하는 적층형 반도체 패키지.The method according to claim 1, wherein an epoxy adhesive having a silver (Ag) content of 80% or more is used for attaching the first chip to the die pad, and a Teflon Wherein the adhesive layer is made of an adhesive. 제 1 항에 있어서, 상기 이너 리드의 상기 제3 이너 리드 요소의 선단에는 오목부와 볼록부 중 하나 이상이 형성되어 있는 것을 특징으로 하는 적층형 반도체 패키지.The multi-layered semiconductor package according to claim 1, wherein at least one of a concave portion and a convex portion is formed at the tip of the third inner lead element of the inner lead. 제 1 항에 있어서, 상기 이너 리드의 상기 제1 이너 리드 요소에서 연장하되 상기 수지밀봉부의 외부로 돌출된 아우터 리드를 더 포함하고, 상기 아우터 리드의 단부에는 노치부를 구비하는 것을 특징으로 하는 적층형 반도체 패키지.2. The semiconductor device according to claim 1, further comprising an outer lead extending from the first inner lead element of the inner lead and protruding to the outside of the resin sealing portion, and the notch portion is provided at an end of the outer lead. package.
KR1020080104543A 2008-10-24 2008-10-24 Stack Type Semiconductor Package KR101563642B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005129750A (en) * 2003-10-24 2005-05-19 Denso Corp Semiconductor device
US20050121756A1 (en) * 2003-07-15 2005-06-09 Chow Wai W. Dual gauge leadframe
JP2006261509A (en) * 2005-03-18 2006-09-28 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050121756A1 (en) * 2003-07-15 2005-06-09 Chow Wai W. Dual gauge leadframe
JP2005129750A (en) * 2003-10-24 2005-05-19 Denso Corp Semiconductor device
JP2006261509A (en) * 2005-03-18 2006-09-28 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

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