KR101547225B1 - Current sampling method and circuit - Google Patents

Abstract

The current sampling circuit comprises a current sampling transistor; A capacitor arrangement between the gate and the source of the current sampling transistor; And an amplifier provided in a feedback loop between the gate and source of the current sampling transistor. The switch controls the circuit to sample the corresponding gate-to-low voltage at the current sampled in the capacitor array. The capacitor array includes a first capacitor circuit for sampling the gate source voltage at a first sampling phase; And a second capacitor circuit, wherein the first and second capacitor circuits are arranged to sample the gate source voltage together in a second sampling phase. The operating point of the amplifier is shifted between the first and second phases based on the gate source voltage sampled at the first sampling phase.

Description

[0001] CURRENT SAMPLING METHOD AND CIRCUIT [0002]

The present invention relates to current sampling methods and circuits and, in particular, but not exclusively, for capturing output signals from sensors having a current output.

 This application claims priority to U.S. Patent Application No. 61 / 016,602, filed December 26, 2007, the entire contents of which are incorporated herein by reference. This application also claims priority from European Patent Application No. 081654293, filed December 17, 2008, the entire contents of which are incorporated herein by reference.

In many sensing applications, sensing devices (e.g., diodes or transistors) generate an output current that depends on the parameter being sensed. The range of applications in which current sensors are used is enormous, and the present invention can be applied to any such application. For example, the sensed parameter may be a light level in the case of a photosensor and a temperature level in the case of a temperature sensor. Sensors will measure physical properties such as light, temperature, strain, or other forces.

The output current of the sensor will often be very small, so it is important to convert the signal to a more robust form close to the sensor to preserve the signal quality, especially the signal-to-noise ratio. Sampling of the current is required when the signal varies with time or when the outputs of multiple sensors are multiplexed with each other as in the case of an array of sensors.

Conventional current sampling circuits can be slow to acquire new signals, especially when the currents are very small.

Figure 1 shows a known simple sampling circuit. The sampled current may include, for example, a photocurrent and is represented by a current source 10. The current is drawn through a p-type drive transistor T1p and the p-type drive transistor T1p has a capacitor C1 connected between its source and gate. Thus, this capacitor stores the gate-source voltage corresponding to the sampled current.

The circuit has a first switch S1 (with a clk1 timing) between the gate and drain of the transistor T1p to turn the transistor to supply the sampled current. The second switch S2 (with clk2 timing) connects transistor T1p to the sensor, and the third switch S3 (which has clk3 timing) connects transistor T1p to the output of the sampling circuit.

As shown in FIG. 2, during the sampling phase S, the switches S1 and S2 are closed and the switch S3 is opened. The current to be sampled is pulled through transistor T1p, in this example photocurrent. The voltages present at the gate and drain of T1p settle at values that make the drain current at T1p the same as the photocurrent. This voltage is stored across the capacitor C1. During the holding phase H, switches S1 and S2 are opened and switch S3 is closed. The gate-source voltage of T1p is held by C1 and therefore the sampled photocurrent is available at the output of the circuit.

The time required to sample the current is proportional to (C1 + Cd) / gm1. Here, Cd is a capacitance of a sensor (i.e., a photodiode), and gm1 is a transconductance of the transistor T1p. When the current is measured small, transistor T1p will operate in a sub-threshold region. In this region, the value of gm1 is proportional to the drain current Id1. Therefore, when the current to be sampled is low, the settling time becomes long.

The settling time can be reduced by using the circuit shown in Fig.

The p-type transistor T1p is replaced by an n-type transistor T1n, and an inverting amplifier 20 is connected between the source and the gate of the transistor T1n. The storage capacitor C1 is again between the source and the gate, and the n-type transistor has a drain connected to the high voltage line VDD. In this arrangement, the settling time is newly proportional to (C1 + Cd) / (A · gm1). Here, A is the gain of the inverting amplifier 20. This reduces the settling time of the circuit by increasing the effective value of the transconductance of T1n.

Switch S4 (with clk4 timing) can open or close the amplifier feedback loop and switch S5 (with clk5 timing) can reset the amplifier.

As shown in Fig. 4, during sampling phase S, switches S2 and S4 are closed, then S3 and S5 are open, so the gate of T1n sees an amplified version of the voltage at the source. The gate source voltage Vgs of T1n required to produce the same drain current as the photocurrent is stored across C1. During the holding phase H, switches S4 and S2 are opened while S3 and S5 are closed. T1n provides the sampled current as the output of the circuit. The amplifier sits around the thresholds of the inputs and outputs connected together, thus ensuring that the voltage node associated with the sensor (in this example, the cathode of the photodiode) is kept completely constant.

The capacitor C1 of FIG. 3 is connected between the input and the output of the inverting amplifier 20 during the sampling phase S. Because of the Miller effect, the effective value of C1 is increased because the inverting amplifier 20 sees the equivalent capacitance A.C1 between the input and ground. This equivalent capacitor tends to be parallel to the Cd and to make the circuit slower, because the equivalent capacitor is between the capacitor Cd and the capacitor Cd (due to the Miller effect, the effective value of C1 is increased since the inverting amplifier 20 sees an equivalent capacitance A.C1 between its input and ground.

The circuit of Figure 3 is also limited by the current that needs to be sampled. The current fixes the gate source voltage to T1n that needs to be made in storage capacitor C1. When sampled, for example, 350 pA, the gate source voltage is approximately 700 mV, which corresponds to a particular operating point of the inverting amplifier.

Figure 5 shows a plot of the gain of an inverting amplifier as a function of Vout-Vin, which is the gate source voltage of T1n in the sampling phase. It can be seen that the operating point of the inverting amplifier, which is seated by the gate source voltage of T1n, will be different from the voltage at which the gain is at its maximum (in absolute value). In other words, the amplifier 20 is not biased to the optimum operating point. This shows the basic limitations of the approach shown in FIG.

According to the invention, there is provided a current sampling circuit comprising a current sampling transistor, a capacitor arrangement, an amplifier and a switch arrangement. The capacitor arrangement is between the gate and the source of the current sampling transistor to store the gate-source voltage corresponding to the current to be sampled. The amplifier is provided in a feedback loop between the gate and source of the current sampling transistor. The switch arrangement controls the circuit sampling the gate-source voltage corresponding to the current sampled in the capacitor array. The capacitor array includes a first capacitor circuit for sampling the gate source voltage at a first sampling phase; And a second capacitor circuit, wherein the first and second capacitor circuits are arranged to sample the gate source voltage together in a second sampling phase. The switch arrangement is operable to move the operating point of the amplifier between the first and second phases, based on the gate source voltage sampled in the first sampling phase

This arrangement provides a coarse sampling phase and is used to vary the operating conditions of the amplifier used in the circuit, in particular by varying the desired voltage at the output. This means that the amplifier can operate more efficiently in continuous and good tuning for the sampling phase.

The switch arrangement is such that if the first capacitor circuit is connected between the source and gate of the current sampling transistor for the first phase or if the first and second capacitor circuits are between the source and gate of the current sampling transistor for the second phase And a switch for selecting whether or not the switch is turned on. Thus, each phase uses a different circuit configuration for the capacitors in the capacitor array.

The switch arrangement comprises: a first amplifier output switch for connecting the output of the amplifier to the gate of the current sampling transistor for a first phase; And a second amplifier output switch for coupling the output of the amplifier to a junction between the first and second capacitor circuits in a second phase. In this way, the desired voltage at the amplifier output can be varied to change the amplifier operating conditions.

The reset phase is more preferably provided between the first and second phases, to which the amplifier inputs and outputs are coupled together.

One of the first and second capacitor circuits may include the first and second capacitors in series. By connecting the junction between the first and second capacitors to the reference potential during the sampling phase, the Miller effect described above can be avoided.

The present invention also provides a current sampling circuit including a current sampling transistor, a capacitor, an amplifier, and a switch arrangement. The capacitor arrangement is between the gate and the source of the current sampling transistor to store the gate-source voltage corresponding to the current being sampled. The amplifier is provided in a feedback loop between the gate and source of the current sampling transistor. The switch arrangement controls the circuit to sample the gate-source voltage corresponding to the current sampled in the capacitor array. The capacitor array includes first and second capacitors in series, and the switching array includes a switch for connecting the junction between the first and second capacitors to a reference potential. This current sampling circuit overcomes the Miller effect. The current sampling circuit of the present invention can be used as part of the sensor circuit, and the sensor in the sensor circuit has a current output that is the current to be sampled.

The present invention also provides a current sampling method. An embodiment of the current sampling method is described below. In the first sampling phase, the amplifier is used to amplify the source voltage of the current sampling transistor and is provided to the amplified voltage gate, the gate source voltage corresponding to the current sampled in the first capacitor circuit is sampled and sampled The gate source voltage is used to move the operating point of the amplifier. In the second sampling phase, the amplifier is used to amplify the source voltage of the current sampling transistor, the amplified voltage is provided to the gate, and the gate source voltage corresponding to the current sampled in the capacitor array is sampled. The capacitor array includes a first capacitor circuit and a second capacitor circuit.

The present invention also provides a current sampling method. An embodiment of the current sampling method is described below. In the sampling phase, the amplifier is used to amplify the source voltage of the current sampling transistor, the amplified voltage is supplied to the gate, and the gate source voltage corresponding to the current sampled in the capacitor circuit is sampled. The capacitor circuit comprises first and second capacitors in series, wherein during the sampling, the junction between the first and second capacitors is connected to a reference voltage.

In the hold phase, the sampled current is supplied to the output, and the junction between the first and second capacitors is isolated from the reference potential.

These methods correspond to the use of the circuits of the present invention. The sampling methods may be used as part of a signal sensing method and in a signal sensing method the sensor may be used to perform a sensing function thereby generating a current output sampled by the sampling methods of the present invention .

Thus, the present invention provides circuits and methods that provide two approaches. The first approach is to eliminate the Miller effect that exists during the sampling phase. This method is based on splitting the capacitance, which is increased by the Miller effect, into two series capacitors, and connecting a common terminal to a reference potential such as ground.

The second approach is a two-step sampling approach. In the first sampling phase, the coarse gate source voltage value is stored across the capacitor, and the second is used to move the operating point of the inverting amplifier in the sampling phase. In this way, during the second sampling phase, the inverter amplifiers will operate around a high gain region, thus giving shorter sampling times and good immunity to changes in transistor characteristics . The two approaches can be combined in a circuit / method.

The detailed description is set forth in the following example with reference to the accompanying drawings.

The invention may be better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings.

The following description is a deliberate mode of practicing the invention. This description is made for the purpose of illustrating the general principles of the present invention and should not be taken in a limiting sense. The scope of the invention is determined with reference to the appended claims.

The same reference numerals are used in other figures in which the constructions perform the same function. Therefore, the description of the function of each configuration is not repeated.

The present invention provides a solution to the two problems described above, namely, a Miller effect capacitance issue and an amplifier operating point issue. The sensor circuits are described below, describing these issues one by one, and the circuit is described with a description of the two issues.

The circuit of Figure 6 and the associated timing diagrams illustrate the Miller effect. In particular, the settling time of the circuit in FIG. 3 can be reduced in the circuit of FIG. 6, and in the circuit of FIG. 6, the capacitance C1 increased by the Miller effect is divided into two capacitors C1a and C1b. The circuit includes a switch S4 'for connecting the junction between the first and second capacitors C1a and C1b to the reference potential VSS1. Switch S4 'is clocked to the same signal as switch S4. Thus, during the sampling phase S, with the amplifier connected to the feedback loop, the junction is held at a fixed potential.

In this way, the Miller effect is eliminated and the settling time of the circuit is improved. During the sampling phase, C1a is seen as a capacitor driven by the output of the inverting amplifier, while C1b and C1b are connected to a fixed potential (e.g., ground) so that C1b is seen as the input capacitance of the inverting amplifier It has one terminal.

During the holding phase H, C1a and C1b are connected in series, so the sum of the voltage stored across C1a and the voltage stored across C1b forms the necessary gate source voltage for T1n to supply the sampled current .

In the circuit of FIG. 6, the change in the sampled current must be managed with special care in terms of rate. If the current changes very quickly, the sampled current can be well below the target current, take time to recover, and make the circuit inherently slow.

The circuit of Figure 7 and the associated timing diagram illustrate the amplifier operating point issue and perform a double sampling method.

The timeline is divided into a first sampling phase Sa, a reset phase R1, a second sampling phase Sb and a holding phase H.

The circuit has a series capacitor arrangement C1, C2 between the gate and the source of the current sampling transistor T1n to store the gate-source voltage corresponding to the sampled current. The circuit is controlled to sample the gate-source voltage corresponding to the current sampled at the first capacitor C1 at the first sampling phase Sa and the gate at the first and second capacitors in the second sampling phase Sb - controlled to sample the source voltage.

The first sampling phase can be considered as a coarse sampling phase, and second, is used to set the operating point of the amplifier 20 for a good sampling phase.

The switch S6 (with clk6 timing) determines whether the first capacitor C1 is connected between the source and gate of the current sampling transistor (for the first phase), or if the first and second capacitors C1, C2 Current sampling transistor to be connected in series between the source and the gate.

The output of amplifier 20 is connected to the gate by a first amplifier output switch S4 (having clk4 timing) for the first phase and by a second amplifier output switch S7 (having clk7 timing) for the second phase, And to one of the junctions between the second capacitors C1, C2. In this way, the voltage at the capacitor C1 is used to define the operating point of the amplifier.

During the first sampling phase Sa, the switches S2, S4 and S6 are closed while the switches S3, S5, S7 are open. Capacitor C2 is then shorted, while the coarse value of Vgs needed by T1n to supply the current to be sampled is made across C1.

During reset phase R1, switch S5 (with clk5 timing) is closed. This switch S5 connects the amplifier inputs and outputs together, and the switch S4 opens, so the amplifier is reset and does not provide a feedback function.

During this reset phase, inverter amplifier 20 is biased around a threshold, and the source of T1n is then taken at the amplifier threshold. Because one terminal of the source-gate capacitor C1 has a high impedance, the gate of T1n will follow this change in source voltage. C2 is held in a sieve with a threshold voltage of the inverting amplifier at both terminals.

During the second sampling phase Sb, switches S6 and S5 are opened while switch S7 is closed. The amplifier output is connected to the junction between the capacitors, and the two capacitors are between the gate and source of the transistor.

During this phase, the capacitor C1 maintains the coarse gate source voltage value Vgs stored from the first sampling phase Sa, and the correction needed to achieve the correct gate source voltage of T1n is made across C2.

Thus, by using a coarse voltage across C1, the operating point of the inverting amplifier is shifted toward a high gain region.

The reset phase R1 is necessary to avoid spikes of the drain current of T1n at the beginning of the second sampling phase Sb. This can happen as soon as switch S7 closes, because one terminal of C1 will see an amplified version of the source voltage of T1n, and is fed through C1 to the gate of T1n, thus causing an initial excess current.

The phase R1 then ensures, through resetting of the inverting amplifier, that the correct voltages are set up at the terminals of C1 and C2.

During the holding phase H, switches S3 and S5 are closed, and switches S2 and S7 are open. The capacitors C1 and C2 are then connected in series so that the sum of the voltages across each of them, i.e., the coarse value and the sum of the good corrections, is the final gate source of T1n needed to supply the correct sampled current to the output of the circuit To form a voltage.

The double sampling circuit in FIG. 7 is very independent of the rate at which the current to be sampled varies.

FIG. 8 shows an enhanced version of the circuit shown in FIG. In this circuit, the sampling time is further reduced by separating the capacitance associated with the Miller effect (C2 in FIG. 7), as described above with respect to FIG. 7 for a single sampling case.

The circuit of Figure 8 includes two pre-charge transistors P1, P2. In addition to these, this circuit is only equivalent to the circuit of Fig. 7 in that capacitor C2 is replaced by two series capacitors C2a, C2b having a junction where they are connected to a fixed potential via switch S8 (with clk8 timing) different.

Switch S8 closes during two sampling phases Sa, Sb and reset phase R1, and then opens during the holding phase.

In the circuit of Fig. 8, the pre-charge phase is used by the transistors P1, P2.

A first pre-charge transistor P1 is coupled between the transistor gate and the high power line VDD and a second pre-charge transistor P2 is coupled between the transistor drain and the high power line . They operate as switches and are controlled by lines clk9 and clk10.

In the pre-charge phase, P1 is on, P2 is off and switches S2, S6, S8 are closed. P1 increases the gate of T1n to the high voltage rail VDD and the source of T1n is taken at the threshold of the inverting amplifier bias so that C1, C2a and C2b have approximately VDD / 2 across them.

P2 isolates T1n from VDD so that no additional current flows across T1n. This phase is such that the initial current through T1n during the next first sampling phase Sa is given by the voltage stored across Cl during the pre-charge time and is highly compared to the photocurrent to be sampled do. Under these conditions, the circuit reacts very quickly to changes in the photocurrent, thus giving a fast sampling time. During all the other phases Sa, Rl, Sb and H, P1 is off and P2 is on, in order to make the connection to the power line VDD functionally the same as in all other circuits described.

This circuit is particularly important in sensor applications, for example, when sensing small currents related to light intensity, temperature, or degree of DNA hybridization can change in time Especially when it is.

The present invention can be used in display devices for processing optical sensor signals. Optical sensing can be used to automatically control the display depending on the ambient light level, and such control methods are known.

The circuits shown are only a few examples. The switches shown in the circuits can of course be implemented with transistors, and if the current sampling circuit is integrated on a substrate of another device such as a display, the same technology devices can be used for other circuit elements in the circuit board Will be used as switches. The implementation of the illustrated circuits will therefore be routine to those skilled in the art.

Although the present invention has been described by way of example and in terms of preferred embodiments, the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Figure 1 shows the first known current sampling circuit,

Figure 2 is a timing diagram for the circuit of Figure 1,

Figure 3 is a diagram of a second known current sampling circuit,

Figure 4 is a timing diagram for the circuit of Figure 3,

5 is a graph for explaining how the operating point of the amplifier affects performance,

6A is a first example of a current sampling circuit according to the present invention,

Figure 6b is a timing diagram for the circuit of Figure 6a,

Figure 7a is a second example of a current sampling circuit according to the present invention,

Figure 7b is a timing diagram for the circuit of Figure 7a,

8A is a third example of a current sampling circuit according to the present invention,

Figure 8b is a timing diagram for the circuit of Figure 8a.

Claims (10)

Current sampling transistor; A capacitor arrangement between a gate and a source of the current sampling transistor for storing a gate-source voltage corresponding to a current to be sampled; An amplifier provided in a feedback loop between the gate and source of the current sampling transistor; A switch arrangement for controlling the circuit to sample a gate-source voltage corresponding to a current sampled in the capacitor array; And And a sensor having a current output that is a current to be sampled, Wherein the capacitor array comprises a first capacitor circuit for sampling the gate source voltage in a first sampling phase and a second capacitor circuit, wherein the first capacitor circuit and the second capacitor circuit are arranged in a second sampling phase, Wherein one of the first capacitor circuit and the second capacitor circuit is arranged to serially include a first capacitor and a second capacitor, The switch arrangement being operative to move the operating point of the amplifier between first and second sampling phases based on a gate source voltage sampled in a first sampling phase, In the switch arrangement, A first amplifier output switch for connecting the output of the amplifier to the gate of the current sampling transistor for the first sampling phase; And And a second amplifier output switch for coupling the output of the amplifier in the second sampling phase to a junction between the first and second capacitor circuits, Wherein the switch arrangement is operative to supply a reset phase between first and second sampling phases to which the amplifier inputs and outputs are coupled together. delete The method according to claim 1, In the switch arrangement, A sampling switch for coupling the current sampling transistor to a source of current, and an output switch for coupling the current sampling transistor to an output of the circuit. The method according to claim 1, Wherein the switch arrangement comprises a switch for connecting a junction between the first and second capacitors to a reference potential. In the current sampling circuit, Current sampling transistor; A capacitor arrangement between a gate and a source of the current sampling transistor to store a gate-source voltage corresponding to a current to be sampled; An amplifier provided in a feedback loop between the gate and source of the current sampling transistor; A switch arrangement including a first switch, a second switch, a third switch, a fourth switch and a fifth switch for controlling to sample a gate-source voltage corresponding to a current sampled in the capacitor array; And And a sensor having a current output that is a current to be sampled, Wherein the capacitor array comprises first and second capacitors in series and the fourth switch couples the junction between the first and second capacitors to a reference potential, Wherein the first switch is connected between the source of the current sampling transistor and the sensor and the second switch connects the current sampling transistor to the output of the current sampling circuit and the third switch is connected to the amplifier And the fifth switch is connected between the input of the amplifier and the output of the amplifier. Using a sensor to perform a sensing function, thereby generating a current output; In a first sampling phase, an amplifier is used to amplify the source voltage of the current sampling transistor and supply the amplified voltage to the gate, sample the gate source voltage corresponding to the sampled current in the first capacitor circuit, Using the sampled gate source voltage to move the point; And In a second sampling phase, an amplifier is used to amplify the source voltage of the current sampling transistor and to supply an amplified voltage to the gate, and a current corresponding to the sampled current in the capacitor arrangement comprising the first capacitor circuit and the second capacitor circuit Sampling a gate source voltage to be applied to the gate; / RTI > The method according to claim 6, Connecting the first capacitor circuit between the source and the gate of the current sampling transistor in the first sampling phase before amplifying the source voltage of the current sampling transistor, Coupling an output of the amplifier to a gate of the current sampling transistor before amplifying a source voltage of the current sampling transistor; And Coupling the first and second capacitor circuits between the source and the gate of the current sampling transistor and connecting the output of the amplifier to a junction between the first and second capacitor circuits in the second sampling phase ; / RTI > The method according to claim 6, And providing a reset phase between the first and second sampling phases to which the amplifier inputs and outputs are coupled together. The method according to claim 6, Coupling the current sampling transistor to a source of current during a sampling phase and to an output of the circuit during a hold phase, Wherein one of the first and second capacitor circuits comprises a first and a second capacitor in series, The method comprises: And coupling a junction between the first and second capacitors to a reference potential during the sampling phase. Using a sensor to perform a sensing function, thereby generating a current output; In the sampling phase, an amplifier is used to amplify the source voltage of the current sampling transistor and to supply the amplified voltage to the gate, and a gate source corresponding to the sampled current in the capacitor circuit comprising the first and second capacitors in series. Sampling a voltage, wherein a junction between the first and second capacitors during the sampling phase is coupled to a reference potential; And Providing a sampled current as an output at the hold phase and isolating a junction between the first and second capacitors from the reference potential; / RTI >

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