KR101536649B1 - An X-ray image sensor with column ADC structures and the signal processing method thereof - Google Patents

Abstract

The present invention relates to an x-ray image sensor with a column ADC structure and a signal processing method thereof. The present invention includes: an x-ray sensor array unit having multiple x-ray cells receiving x-rays arranged in an array structure; a current source which receives a reset signal and an optical signal of each of the x-ray sensor cells from the x-ray sensor array unit through each column signal line and converts them into electrical analog signals; a free amp which amplifies the analog signals; and a plurality of CDS blocks storing the analog signals individually.

Description

An X-ray image sensor having a column ADC structure and an X-ray image sensor having a column ADC structure and a signal processing method therefor,

The present invention relates to an X-ray image sensor having a column ADC structure and a signal processing method thereof, and in constructing an X-ray image sensor using a column ADC structure, a signal transmitted from the X- CDS signals are processed in parallel operation through multiple CDS blocks by applying the same ramp signal of different voltage levels to each CDS block at the same time, A digital lower bit value is detected in the column ADC, a digital lower bit value following the detected digital upper bit value is calculated in the column ADC, and a digital signal value is outputted, An X-ray image sensor having a column ADC structure capable of improving ADC resolution and capable of processing an X-ray detection signal in high resolution, and And a signal processing method therefor.

Generally, an X-ray image sensor is a kind of image sensor for sensing a X-ray by a sensor cell (pixel) in a digital X-ray imaging apparatus and converting the X-ray into a digital image.

The integrated circuit of the X-ray image sensor senses an optical signal (charge) generated in the photodiodes of the respective X-ray sensor cells according to the incidence of X-rays in the X-ray sensor array of the X-ray image sensor, And outputs the final video signal in the form of digital data.

Since such an X-ray image sensor is usually applied to X-ray medical equipment such as a digital X-ray imaging apparatus, unlike an image sensor applied to a general digital camera, a large-sized X- An X-ray image sensor is required, and in addition, an X-ray image sensor supporting a high-resolution clear image is required.

FIG. 1 is a view showing the structure of a conventional X-ray image sensor.

As shown in FIG. 1, a conventional X-ray image sensor has a structure in which a plurality of X-ray sensor cells 11 are arrayed in a matrix array on a substrate of an image sensor, -Line sensor cell 11 is sequentially selected row by row by the low shift register 12 to output a reset signal and an X-ray optical signal from each X-ray sensor cell 11 in the active row unit And is transmitted to the current source source 13.

In the current source 13, the reset signal and the X-ray optical signal transmitted from the X-ray sensor cell 11 are converted into an electrical analog signal, and the reset signal and the X- (Correlated Double Sampling) block.

Here, the CDS block 14 is constituted by a combination of CDS circuits provided in units of column signal lines of the X-ray sensor array unit 10. [

The reset signal and the X-ray optical signal of the X-ray sensor cell 11 stored in the CDS block 14 are sequentially distributed to the ADC (Analog Digital Converter) 16 one by one via the multiplexer 15, The ADC 16 converts the CDS signal transmitted through the multiplexer 15 into a digital signal and outputs it to the outside.

The digital signal thus output can be imaged as a moving image or a still image by signal processing of an image signal processor (ISP) (not shown) and displayed on the screen.

The column shift register 17 shown in FIG. 1 controls the operation of sequentially selecting and delivering the column-specific CDS signals in the CDS block 14, and the control block 18 processes the signals through the above- FIG.

However, the structure of the conventional X-ray image sensor configured as described above is a situation where the speed of signal processing of the large area X-ray sensor cell is already at a limit, and in order to output a high resolution image, It is necessary situation.

The X-ray image sensor of Fig. 1 as described above can also be used to distribute the signals stored in each CDS circuit of the CDS block 14 to the ADC 16 via the multiplexer 15 by using one ADC 16. [ A very long signal line is required to transmit a signal from a plurality of CDS circuits to a single ADC 16 via the multiplexer 15 and signal loss and noise due to a long signal line occur have.

In addition, there is a problem that switching noise is generated by the switching operation for controlling the multiplexer 15.

In recent years, in order to reduce the signal loss and the noise components generated in the single ADC structure, a column ADC having a structure in which an ADC is disposed in each column signal line is provided. A CMOS image sensor disclosed in Korean Patent Laid-Open Publication No. 2009-0083817 has been developed to minimize the number of signal lines from the CDS block to the ADC and reduce the switching noise by removing the multiplexer. FIG. 2 is a diagram illustrating a conventional CMOS image sensor structure having a column ADC structure as described above.

As shown in FIG. 2, the CMOS image sensor of the columnar ADC structure has a structure in which the ADCs are arranged in each column signal line, so that the signal lines from the CDS block 14 to the column ADC 23 can be minimized, No multiplexer is required, and signal loss and noise can be reduced.

However, such a column ADC structure operates in a manner of counting a digital counter value in a ramping interval defined by a ramp generator 21 and a data counter 22, Is difficult to apply.

That is, the digital counter value is constantly increased in a given ramping interval, the digital counter value is stored at the moment when the ramp signal that increases and constantly increases the X-ray optical signal crosses the reset signal of the X-ray sensor cell The column ADC architecture has many limitations in increasing the resolution of the ADC.

In other words, for high-resolution X-ray equipment, the time required to process the signal in the column ADC increases exponentially by 2 times every time the resolution of the ADC is doubled, and the time required to process such a column ADC signal is reduced In order to increase the clock speed of the data counter 22, it is necessary to reduce the clock time. However, there is a limit to increase the clock speed of the data counter due to the technical limitations of the semiconductor manufacturing process.

Further, as the clock speed of the data counter 22 increases, it becomes more vulnerable to clock noise. Therefore, it is also limited to increase the clock speed of the data counter for high resolution.

Accordingly, in a medical X-ray apparatus in which high resolution is required due to the characteristics of the equipment, the column ADC structure shown in FIG. 2 is difficult to meet the high resolution required by the X-ray equipment. The same pipeline ADC architecture is applied in many cases.

Korean Patent Publication No. 2009-0083817 (Published on Aug. 4, 2009) "CMOS image sensor"

SUMMARY OF THE INVENTION The present invention has been conceived to solve the above problems, and it is an object of the present invention to provide an X-ray image sensor using a column ADC structure, in which a CDS block for storing signals transmitted from an X- The same ramp signal of different voltage level is simultaneously applied to each CDS block and the CDS signal is processed in parallel operation through multiple CDS blocks to detect the digital high bit value of the detection signal in the multi- , The column ADC calculates the digital lower bit value following the detected digital upper bit value and outputs the digital signal value to improve the ADC resolution without increasing the signal processing time as compared with the conventional X-ray image sensor , An X-ray image sensor having a column ADC structure capable of processing an X-ray detection signal with high resolution, and a signal processing method therefor It is an object to the ball.

According to an aspect of the present invention, there is provided an image sensor for detecting an X-ray image, the sensor comprising: a plurality of X-ray sensor cells for receiving X- A sensor array unit; A current source for receiving a reset signal and an optical signal of each X-ray sensor cell from the X-ray sensor array unit through respective column signal lines and converting the reset signal and the optical signal into an electrical analog signal; A preamplifier for amplifying the analog signal converted through the current source source; A plurality of CDS blocks constituted by a combination of CDS circuits provided in units of column signal lines of the X-ray sensor array section, each of the CDS blocks storing analog signals amplified through the preamplifier; A multi-step ramp generator that equally divides the entire CDS voltage level according to the number of the CDS blocks, and simultaneously applies the same ramp signals of the same voltage levels to the plurality of CDS blocks; A multi-CDS signal detector for detecting a point where the reset signal and the ramp signal input to the plurality of CDS blocks meet, and detecting and outputting a digital upper bit value; And a column ADC for calculating and outputting a digital lower bit value following the digital upper bit value detected by the multi CDS signal detecting unit.

The X-ray image sensor according to the present invention processes a signal in parallel through a multi-CDS block circuit structure having a plurality of CDS blocks, detects a digital high-order bit value through a multi-CDS signal detecting unit, By calculating the digital lower bit value following the detected digital upper bit value and outputting the digital signal value, the ADC resolution can be improved without increasing the signal processing time as compared with the conventional X-ray image sensor, The signal can be processed in a high resolution.

Further, the present invention further includes a multi-CDS error detector and an error correction counter to compensate for multi-CDS errors that may be caused by the multi-CDS block structure, thereby minimizing noise and providing a high- Can be obtained.

1 is a view showing a structure of an X-ray image sensor according to the related art;
2 is a view showing a structure of a CMOS image sensor having a column ADC structure according to the related art
3 is a view showing a structure of an X-ray image sensor having a column ADC structure according to an embodiment of the present invention;
4 is a view showing a CDS circuit structure constituting a CDS block in the structure of an X-ray image sensor according to an embodiment of the present invention;
5 is a diagram showing a signal processing process of a multi-CDS block in the structure of an X-ray image sensor according to an embodiment of the present invention.
6 is a diagram illustrating signal processing when a multi-CDS error occurs in a signal processing process through the multi-CDS block of FIG. 5

Hereinafter, the embodiments of the present invention will be described in detail, but the present invention is not limited to the following embodiments unless they depart from the gist of the present invention.

3 is a diagram illustrating a structure of an X-ray image sensor having a column ADC structure according to an embodiment of the present invention.

3, an X-ray image sensor having a columnar ADC 170 according to an embodiment of the present invention includes a plurality of X-ray sensor cells 111 receiving X-rays in a matrix form Ray sensor array part 110 arranged in an array structure of an X-ray sensor array part 110; A current source 120 for receiving a reset signal and an optical signal of each X-ray sensor cell 111 from the X-ray sensor array unit 110 through respective column signal lines and converting the optical signal into an electrical analog signal, ; A preamplifier 130 for amplifying the converted analog signal through the current source 120; A plurality of CDS blocks 140 configured by a combination of CDS circuits provided in units of column signal lines of the X-ray sensor array unit 110 and each storing analog signals amplified through the preamplifier 130; ; A multi-step ramp generator 140 for equally dividing the entire CDS voltage level according to the number of the CDS blocks 140, and simultaneously applying the same ramp signals of the same voltage levels to the plurality of CDS blocks 140, (150); A multi-CDS signal detector 160 for detecting a point where the reset signal and the ramp signal input to the plurality of CDS blocks meet, and detecting and outputting a digital upper bit value; And a column ADC 170 for calculating and outputting a digital lower bit value following the digital upper bit value detected by the multi CDS signal detecting unit 160. [

That is, the X-ray image sensor according to the present invention configured as described above includes a plurality of CDS blocks for storing signals transmitted from the X-ray sensor array unit, and each CDS block is divided into equally divided The CDS signal is processed in parallel operation through the multiple CDS blocks by simultaneously applying the same ramp signal at the same voltage level so that the digital upper bit value is detected in the multi CDS signal detecting unit, And outputting a digital signal value. Thus, the ADC resolution can be improved without increasing the signal processing time as compared with the conventional X-ray image sensor.

The X-ray sensor array unit 110 is formed in an aggregate structure in which a plurality of X-ray sensor cells 111 for receiving X-rays are two-dimensionally arranged.

3, an X-ray sensor cell 111 having the array structure as described above is selected in units of rows on one side of the X-ray sensor array unit 110, And a row shift register 210 for controlling the reset signal and the X-ray optical signal of the sensor cell 111 to be transmitted along a column signal line.

That is, the low shift register 210 is connected to a plurality of X-ray sensor cells 111 arranged in each row unit of the X-ray sensor array unit 110 via low signal lines, Ray sensor cell 111 is sequentially selected in units of rows by the control of the row shift register 210 so that the reset signal and the X-ray optical signal from each X- Lt; / RTI > to the current source source 120 via line.

The current source 120 receives the reset signal and the X-ray optical signal of each X-ray sensor cell 111 from the X-ray sensor array unit 110 through each column signal line and converts the signal into an electrical analog signal do.

The preamplifier 130 amplifies the converted analog signal through the current source 120 and transmits the amplified analog signal to the CDS block.

At this time, the X-ray optical signal amplified by the preamplifier 130 and the reset signal are all stored in the same CDS block 140.

In this case, the number of CDS blocks provided in a plurality may be 2 squares (2 = 1, 2, ...), and the signal processing speed increases as the number of CDS blocks increases. It is necessary to design the number of CDS blocks by adjusting the number of CDS blocks according to the design specifications of the X-ray image sensor.

3, a multi-CDS block structure including four CDS blocks 141, 142, 143 and 144 will be described as an example

Each of the CDS blocks 141, 142, 143 and 144 is constituted by a combination of CDS circuits provided in units of column signal lines of the X-ray sensor array unit 110 and stores analog signals amplified through the preamplifier 130.

4 is a diagram illustrating a CDS circuit structure of a CDS block in the structure of an X-ray image sensor according to an embodiment of the present invention.

4, each of the CDS circuits constituting the CDS block includes a first capacitor 310 for storing a reset signal of the X-ray sensor cell 111, a second capacitor 310 for storing an X- A capacitor 320 and an analog comparator 330 for comparing and outputting the reset signal and the X-ray optical signal.

That is, the CDS circuit is configured with the structure of FIG. 4 described above in order to reduce the error of the semiconductor mismatching of the CDSs arranged in the same column signal line in plural.

3, the multi-step ramp generator 150 generates a ramp signal for converting an X-ray optical signal transmitted from the X-ray sensor array unit 110 into a digital signal , And is configured to be able to change and control the slope and the section of the ramp by the program control.

The multi-step ramp generator 150 equally divides the entire CDS voltage level according to the number of the CDS blocks 140 and equally divides the same lamp signals of the different voltage levels equally divided into the plurality of CDS blocks 140 Simultaneously.

5 is a diagram illustrating a signal processing process of a multi-CDS block in the structure of an X-ray image sensor according to an embodiment of the present invention.

5, since the multi-step ramp generator 150 includes the four CDS blocks 141, 142, 143 and 144 in the present embodiment, the multi-step ramp generator 150 generates four sections The second CDS block 142, the third CDS block 143, and the fourth CDS block 144 at the same time by outputting the same ramp signal having the same voltage level to the first CDS block 141, the second CDS block 142, the third CDS block 143, .

That is, the four ramp signals have the same value between the voltage level (minimum ramp voltage level) at which ramping starts and the voltage level at which ramping ends (maximum ramp voltage level) are all the same and are applied to the four CDS blocks 141, 142, 143, The ramp slope of the ramp signal is also set to the same slope.

In FIG. 5, the slope of each ramp signal is shown to increase from the minimum ramp voltage level to the maximum ramp voltage level, but it is also applicable to decreasing the slope of the ramp signal from the maximum ramp voltage level to the minimum voltage level Of course.

In the four CDS blocks 141, 142, 143, and 144, reset signal values and X-ray optical signal values of the respective X-ray sensors transmitted from the X-ray sensor array unit 110 are stored in the same manner. As shown in the figure, when the lamp signals independently controlled in accordance with the four lamp periods are simultaneously applied to the first to fourth CDS blocks 141, 142, 143 and 144, the lamp signal increases in four independent lamp periods, A point of meeting occurs.

5, the ramp signal and the reset signal are in a period in which the third CDS block 143 is located in the first to fourth CDS block periods, and the third CDS block 143 is in a non- A comparison signal is detected in only one place to generate a CDS signal output and no signal is detected in the first CDS block 141, the second CDS block 142 and the fourth CDS block 144, 3 CDS block 143, the CDS output value is different.

3, the signals processed by the four CDS blocks 141, 142, 143 and 144 are transmitted to the multi-CDS signal detecting unit 160 through the column signal lines, and the multi-CDS signal detecting unit 160 detects the multi- 3 CDS block 143, the digital high bit value is detected through the CDS output value at the intersection of the ramp signal and the reset signal.

At the same time, the column ADC 170 calculates and calculates a digital lower bit value following the digital upper bit value detected by the multi-CDS signal detecting unit 160 from the CDS output value.

That is, the column ADC 170 subtracts the digital low-order bit value from the digital count value at the point where the CDS output signal is generated in the third CDS block 143, .

As described above, in this embodiment, a CDS signal is processed in parallel operation through a multi-CDS block structure having four CDS blocks 141, 142, 143 and 144, so that a multi-CDS signal detecting unit 160 detects a digital high- The column ADC 170 calculates the digital lower bit value following the digital upper bit value and outputs the digital signal value so that the final ADC bit number To support high-resolution X-ray equipment.

In the above description, the column shift register 220 shown in FIG. 3 controls the operation of sequentially selecting and transmitting column-by-column CDS signals in the plurality of CDS blocks 140, and the control block 230 controls the above- And a signal processing process through the configurations.

Meanwhile, when the CDS signal is processed by the parallel operation through the multi-CDS block structure, as shown in FIG. 5, when the point where the lamp signal and the reset signal meet in the four CDS sections occurs in one place, the signal is normally processed An error occurs when two or more points where the lamp signal and the reset signal meet in the four CDS sections occur. In this case, distortion may occur in the image due to noise.

Accordingly, the X-ray image sensor of the present invention is further provided with a multi-CDS error detection unit 180 and an error correction counter 190 for error correction.

CDS error detection unit 180 detects a multi-CDS error signal in which CDS output signals are generated in a process of performing signal processing on four CDS blocks, and an error correction counter 190 detects a multi- And outputs a digital error value by performing an error correction count on the basis of the multi-CDS error signal detected by the error detection unit.

FIG. 6 is a diagram illustrating signal processing when a multi-CDS error occurs in the signal processing through the multi-CDS block of FIG.

6, when the four CDS blocks 141, 142, 143, and 144 process signals at the same time, the reset signal is located at the boundary of the second CDS block 142 and the third CDS block 143, When the CDS output signal is detected in both the second CDS block 142 and the third CDS block 143 as a result of the detection of the multi-CDS error signal by the multi-CDS error detector 180, In this case, the first detected CDS output signal is regarded as the final CDS output signal, and the CDS output signal detected subsequently is ignored.

6, since the CDS output signal is first detected in the third CDS block 143 rather than the second CDS block 142, the CDS output signal is processed as detected in the third CDS block 143, In the CDS block 142, the CDS output signal is processed as not detected.

At this time, the multi-CDS signal detector 160 detects the digital high-order bit value through the CDS output signal of the third CDS block 143, and the column ADC 170 also outputs the CDS output signal of the third CDS block 143 It is recognized as an output value of the multi-CDS block, and the corresponding data counter value is stored.

As described above, the output signal detected from the multi-CDS block determines the digital high-order bit value and the value input to the column ADC 170. Even though the CDS output signal is detected in the second CDS block 142, The time between the CDS output signals of the third CDS block 143 and the second CDS block 142 through the error correction counter 190 is equal to the time difference between the CDS output signals of the second CDS block 142 and the second CDS block 142. In this case, The number of clocks of the data counter 200 is counted and output as a digital error value during the interval to correct the error in the process of calculating the output value of the ADC in the future.

At this time, the formula for calculating the ADC output value is as follows.

MSB: Digital high bit value

LSB: Digital lower bit value

ß: Multi CDS error correction factor

In Equation (1), ß is a coefficient used for correcting a multi-CDS error value. Usually, 2 can be used. However, when a multi-CDS error value occurs with a nonlinear numerical value, It goes without saying that appropriate numerical values can be used.

When a multi-CDS error does not occur, the digital error value in Equation (1) becomes "0 ", and the ADC output value is determined only by the digital upper bit value and the digital lower bit value.

As described above, the X-ray image sensor according to the present invention processes a signal in parallel through a multi-CDS block circuit structure having a plurality of CDS blocks, detects a digital high-order bit value through a multi-CDS signal detecting unit , The digital lower bit value following the detected digital upper bit value is calculated through the column ADC and the digital signal value is output to improve the ADC resolution without increasing the signal processing time as compared with the conventional X- Thus, there is an advantage that the X-ray detection signal can be processed with high resolution.

Further, the present invention further includes a multi-CDS error detector and an error correction counter to compensate for multi-CDS errors that may be caused by the multi-CDS block structure, thereby minimizing noise and providing a high- Can be obtained.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. .

110: X-ray sensor array unit 111: X-ray sensor cell
120: current source source 130: preamplifier
140: a plurality of CDS blocks 141: a first CDS block
142: second CDS block 143: third CDS block
144: fourth CDS block 150: multi-step ramp generator
160: Multi-CDS signal detecting unit 170: Column ADC
180: Multi CDS error detection unit 190: Error correction counter
200: Data counter 210: Low shift register
220: Column shift register 230: Control block
310: first capacitor 320: second capacitor
330: Analog comparator

Claims (10)

An image sensor for X-ray image detection,
An X-ray sensor array unit in which a plurality of X-ray sensor cells for receiving X-rays are arranged in a matrix-like array structure;
A current source for receiving a reset signal and an optical signal of each X-ray sensor cell from the X-ray sensor array unit through respective column signal lines and converting the reset signal and the optical signal into an electrical analog signal;
A preamplifier for amplifying the analog signal converted through the current source source;
A plurality of CDS blocks constituted by a combination of CDS circuits provided in units of column signal lines of the X-ray sensor array section, each of the CDS blocks storing analog signals amplified through the preamplifier;
A multi-step ramp generator that equally divides the entire CDS voltage level according to the number of the CDS blocks, and simultaneously applies the same ramp signals of the same voltage levels to the plurality of CDS blocks;
A multi-CDS signal detector for detecting a point where the reset signal and the ramp signal input to the plurality of CDS blocks meet, and detecting and outputting a digital upper bit value;
A column ADC for calculating and outputting a digital lower bit value following the digital upper bit value detected by the multi CDS signal detecting unit;
A multi-CDS error detector for detecting a multi-CDS error signal in which a plurality of CDS output signals are generated in a process of performing signal processing on the plurality of CDS blocks; And
An error correction counter for performing an error correction count based on the multi-CDS error signal detected by the multi-CDS error detector and outputting a digital error value;
And an X-ray image sensor having a column ADC structure.
The method according to claim 1,
Wherein the number of the plurality of CDS blocks is set to a number
(N = 1, 2, 3, ...). The X-ray image sensor has a column ADC structure.
3. The method of claim 2,
Wherein the number of the plurality of CDS blocks is set to a number
X-ray image sensor having a column ADC structure.
The method according to claim 1,
Each CDS circuit constituting the CDS block includes:
A first capacitor for storing a reset signal of the X-ray sensor cell;
A second capacitor for storing an X-ray optical signal; And
An analog comparator for comparing the reset signal and the X-ray optical signal and outputting the comparison result;
Ray image sensor having a column ADC structure.
The method according to claim 1,
Wherein the multi-step ramp generator comprises:
And the slope and the interval of the ramp signal can be controlled.
delete A signal processing method of an X-ray image sensor having a column ADC structure,
Receiving an X-ray optical signal and a reset signal from each X-ray sensor cell of the X-ray sensor array unit and converting the X-ray optical signal and the reset signal into an electrical analog signal through a current source;
Amplifying the X-ray optical signal and the reset signal converted into the analog signal through a preamplifier;
Storing the X-ray optical signal amplified by the preamplifier and the reset signal in the same plurality of CDS blocks;
Equally dividing the total CDS voltage level to the number of CDS blocks through the multi-step ramp generator to simultaneously apply the same ramp signal of different voltage levels equally divided into a plurality of CDS blocks;
Detecting a point where a reset signal and a ramp signal input to the plurality of CDS blocks meet in a multi-CDS signal detecting unit, detecting and outputting a digital upper bit value;
Calculating and outputting a digital lower bit value following the digital upper bit value in the column ADC;
Calculating and outputting an ADC output value based on the output digital upper bit value and the digital lower bit value;
, ≪ / RTI >
In a case where two or more points where a ramp signal and a reset signal meet in a plurality of CDS block periods are generated and multiple CDS output signals are detected,
Counting the number of clocks of the data counter during the time interval between the CDS output signal detected first through the error correction counter and the CDS output signal detected subsequently and outputting the digital error value;
Wherein the signal processing method further comprises the step of:
8. The method of claim 7,
In the step of calculating and outputting the digital lower bit value,
Wherein a digital lower bit value following the digital upper bit value detected by the multi-CDS signal detecting unit is calculated and output from a digital count value at a point where a ramp signal and a reset signal meet in a plurality of CDS block periods Ray image sensor.
delete 8. The method of claim 7,
Wherein when the digital error value is output, the ADC output value is obtained by the following equation.

MSB: Digital high bit value
LSB: Digital lower bit value
ß: Multi CDS error correction factor

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