KR101492694B1 - Organic Light Emitting Display Device and Driving Method thereof - Google Patents

Abstract

The present invention relates to a display device, A driving unit for driving the panel; A timing controller for controlling the driving unit; A power supply unit for supplying power to the panel; A compensation voltage supply unit for supplying a compensation voltage to the panel; A voltage sensing unit sensing the compensation voltage output from the compensation voltage supply unit, comparing the compensation voltage with a threshold voltage set therein, and outputting a resultant value; And a timing detector for controlling the driving unit and outputting a shutdown signal for turning off the power supply unit based on the resultant value.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting display,

The present invention relates to an organic light emitting display and a driving method thereof.

An organic electroluminescent device used in an organic electroluminescent display device is a self-luminous device in which a light emitting layer is formed between two electrodes located on a substrate. The organic light emitting display device may be a top emission type, a bottom emission type or a dual emission type depending on a direction in which light is emitted. It is divided into a passive matrix and an active matrix depending on the driving method.

The subpixel disposed in the organic light emitting display panel includes a transistor portion including a switching transistor, a driving transistor and a capacitor, and an organic light emitting diode including a lower electrode connected to the driving transistor included in the transistor portion, an organic light emitting layer, and an upper electrode .

The brightness of the organic light emitting display panel varies depending on the amount of current flowing through the organic light emitting diode. Since an organic light emitting display panel requires a higher current than a liquid crystal display panel, an overcurrent flows to a device included in a sub pixel when a short circuit occurs between the power sources. The cause of the short circuit between the power sources is that the internal structural factors such as particles, cracks, misalignment of the pad portions, narrow wiring layout, etc. introduced into the organic light emitting display panel during the manufacturing process (or module process) And external factors.

When an overcurrent flows in one subpixel due to a short circuit between the power supplies, the elements included in the corresponding subpixel are burnt. In the case of combustion occurring in a small region, although not initially recognized, when the organic light emitting display panel is driven continuously, the combustion is gradually diffused to neighboring subpixels.

Therefore, a problem of a short circuit between the power supplies requires a method of burning the sub-pixels included in the organic light emitting display panel and preventing the possibility of causing a fire.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems and it is an object of the present invention to provide an organic electroluminescent display device capable of eliminating the possibility that a local burnt of a device may spread to the front and lead to fire when a short circuit or an over- And to provide a driving method.

According to the present invention, A driving unit for driving the panel; A timing controller for controlling the driving unit; A power supply unit for supplying power to the panel; A compensation voltage supply unit for supplying a compensation voltage to the panel; A voltage sensing unit sensing the compensation voltage output from the compensation voltage supply unit, comparing the compensation voltage with a threshold voltage set therein, and outputting a resultant value; And a timing detector for controlling the driving unit and outputting a shutdown signal for turning off the power supply unit based on the resultant value.

The short detection unit compares the compensation voltage with the threshold voltage set therein and judges whether the minimum level and the maximum level of the compensation voltage are out of the allowable range.

The voltage sensing unit includes a first comparator for sensing the lowest level of the compensation voltage and a second comparator for sensing the highest level of the compensation voltage. The first comparator has a first terminal connected to the first threshold voltage terminal, And the second comparator has a first terminal connected to the output terminal of the compensation voltage supply unit, a second terminal connected to the second threshold voltage terminal, and an output terminal connected to the short detection unit. Can be connected.

The voltage supplied to the first threshold voltage terminal and the second threshold voltage terminal may be a negative voltage.

The compensation voltage may comprise at least one of an initialization voltage and a reference voltage supplied to the subpixels of the panel.

In another aspect, the invention provides a method comprising: displaying an image on a panel; Sensing a compensation voltage supplied to the panel; Comparing the compensation voltage and the threshold voltage; And outputting a shutdown signal for turning off the power supply unit that supplies power to the panel when the compensation voltage is out of the allowable range.

The step of comparing the compensation voltage with the threshold voltage may compare the compensation voltage and the threshold voltage to determine whether the minimum and maximum levels of the compensation voltage are out of the allowable range.

According to another aspect of the present invention, there is provided a plasma display panel comprising: A driving unit for driving the panel; A power supply unit for supplying power through power supply lines divided into blocks; A current sensing unit sensing a current flowing through the power supply lines divided by blocks and amplifying the sensed current for each block by an analog voltage per block; An analog-to-digital converter for converting the block-by-block analog voltage supplied from the current sensing unit into a block-by-block digital voltage and outputting the block voltage; And a timing controller for controlling the driving unit and outputting a shutdown signal for determining whether an overcurrent is generated using the digital voltage for each block supplied from the analog-to-digital converter and for turning off the power supply when the overcurrent is generated do.

The timing controller receives the digital voltage of each first block and the digital voltage of each second block through communication with the analog digital converter, compares the digital voltage of each first block with the digital voltage of each second block, The shutdown signal can be output when the difference between the values is outside the allowable range.

The digital voltage for each first block corresponds to the current per block sensed during the first blank period and the digital voltage for each second block corresponds to the current per block sensed during the second blank period.

In another aspect, the present invention provides a method of displaying an image on a panel, the method comprising: displaying an image on a panel; Sensing a digital voltage for each of the first blocks through a power supply line divided into blocks on a panel; Sensing a digital voltage for each of the second blocks through a power supply line divided into blocks on a panel; Comparing the digital voltage of the first block with the digital voltage of the second block and determining whether a difference between the digital voltage and the digital voltage of the second block is out of an allowable range; And outputting a shutdown signal for turning off a power supply unit for supplying power to the panel when a difference value between the digital voltage for each first block and the digital voltage for each second block is out of an allowable range, A method of driving a device is provided.

The digital voltage for each first block corresponds to the current per block sensed during the first blank period and the digital voltage for each second block corresponds to the current per block sensed during the second blank period.

The present invention provides an organic light emitting display device and a method of driving the same that can sense a compensation voltage supplied to a subpixel when a compensation circuit is used and control a power supply unit when a short circuit or an overcurrent occurs between the power supplies. The present invention also provides an organic electroluminescent display device capable of controlling a power supply part when a short circuit or an over-current is generated by comparing currents flowing through a first power supply wiring divided into blocks on a panel at least twice, Thereby providing an apparatus and a driving method thereof.

1 is a schematic view of an organic light emitting display device according to a first embodiment of the present invention;
Fig. 2 is a first example of a compensation voltage supply; Fig.
3 is a second example of a compensation voltage supply.
4 is an exemplary circuit configuration of a subpixel.
Figure 5 is an illustration of an example of the compensation circuit shown in Figure 4;
6 is a driving waveform diagram of the subpixel shown in FIG.
7 is a block diagram embodying a circuit according to a first embodiment of the present invention;
Fig. 8 is a diagram illustrating an exemplary circuit configuration of the compensation voltage supply unit and the voltage sensing unit shown in Fig. 7; Fig.
FIG. 9 is a view illustrating an organic light emitting display device according to a first embodiment of the present invention; FIG.
10 is an example of a minimum level and a maximum level of a reference voltage;
11 is a diagram for explaining the allowable range of the reference voltage.
12 is a diagram for explaining an output state of a power supply unit according to a shutdown signal;
13 is a flowchart illustrating a method of driving an organic light emitting display according to a first embodiment of the present invention.
FIG. 14 is a schematic configuration of an organic light emitting display according to a second embodiment of the present invention. FIG.
FIG. 15 is a view for schematically explaining the current sensing unit and the analog-digital conversion unit shown in FIG. 14; FIG.
Fig. 16 is a diagram illustrating an example of the circuit configuration of the first block current sensing unit shown in Fig. 15. Fig.
17 is a block diagram of an analog-to-digital converter, a timing controller, and a power supply.
18 is a waveform diagram for explaining a state in which the analog-to-digital converter operates in correspondence with the blank section.
19 and 20 are diagrams for explaining the output state of the power supply unit according to the determination result of the timing control unit.
FIG. 21 is a flowchart illustrating a method of driving an organic light emitting display according to a second embodiment of the present invention. FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

≪ Embodiment 1 >

FIG. 1 is a schematic configuration diagram of an organic light emitting display according to a first embodiment of the present invention, FIG. 2 is a first exemplary view of a compensation voltage supply unit, and FIG. 3 is a second exemplary view of a compensation voltage supply unit.

1, an organic light emitting display according to a first exemplary embodiment of the present invention includes an image processing unit 120, a power supply unit 125, a timing control unit 130, a data driving unit 150, a scan driving unit 140, a panel 160, a compensation voltage supply unit 170, and a voltage sensing unit 180.

The image processing unit 120 supplies the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, the clock signal CLK and the data signal DATA to the timing control unit 130 do. The image processing unit 120 is formed on the system board 110.

The timing controller 130 uses a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a clock signal CLK supplied from the image processing unit 120 And controls the operation timings of the data driver 150 and the scan driver 140. The timing controller 130 can determine the frame period by counting the data enable signal DE in one horizontal period so that the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside can be omitted. The control signals generated by the timing controller 130 include a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 150. [ ). The gate timing control signal GDC includes a gate start pulse, a gate shift clock, a gate output enable signal, and the like. The data timing control signal DDC includes a source start pulse, a source sampling clock, a source output enable signal, and the like.

The scan driver 140 sequentially generates the scan signals of the scan high voltage while shifting the level of the gate drive voltage in response to the gate timing control signal GDC supplied from the timing controller 130. The scan driver 140 supplies the scan signals through the scan lines SL1 to SLm connected to the subpixels SP included in the panel 160. [

The data driver 150 samples and latches the data signal DATA supplied from the timing controller 130 in response to the data timing control signal DDC supplied from the timing controller 130 and converts the sampled data signal into data of a parallel data system . The data driver 150 converts the data signal DATA into a gamma reference voltage. The data driver 150 supplies the data signal DATA through the data lines DL1 to DLn connected to the subpixels SP included in the panel 160. [

The power supply unit 125 converts an external voltage supplied from the outside to output a first potential voltage (e.g., 20V level), a second potential voltage (e.g., 3.3V level), and a low potential voltage (e.g. The first potential is the drain-level voltage supplied to the first power supply line EVDD, the second potential is the collector-level voltage supplied to the second power supply line VCC, and the low- , GND). The power supply unit 125 is formed on the system board 110 together with the image processing unit 120. The power outputted from the power supply unit 125 is used for the image processing unit 120, the timing control unit 130, the data driving unit 150, the scan driving unit 140, the panel 160 and the compensation voltage supply unit 170.

The compensation voltage supply unit 170 outputs the compensation voltages Vinit and Vref. The compensation voltages Vinit and Vref include an initialization voltage Vinit and a reference voltage Vref. The initialization voltage Vinit and the reference voltage Vref may have the same level or different levels. The initialization voltage Vinit and the reference voltage Vref output from the compensation voltage supply unit 170 are supplied to the compensation circuit included in the subpixels SP of the panel 160. The compensation voltage supply unit 170 may output the initialization voltage Vinit and the reference voltage Vref using the power source output from the power supply unit 125 as shown in FIG. 2B, the compensation voltage supplier 170 includes a first compensation voltage supplier 170a for outputting the initialization voltage Vinit using the power supplied from the power supplier 125 and a second compensation voltage supplier 170b for outputting the reference voltage Vref, And a second compensation voltage supply unit 170b for outputting the second compensation voltage. The compensation voltage supplier 170 may output the initialization voltage Vinit and the reference voltage Vref by using the power source output from the inside of the data driver 150 as shown in FIG.

The voltage sensing unit 180 senses and outputs the compensation voltages Vinit and Vref output from the compensation voltage supply unit 170. The voltage sensing unit 180 separately senses the initialization voltage Vinit output from the compensation voltage supply unit 170 and the reference voltage Vref. The compensation voltages Vinit and Vref sensed by the voltage sensing unit 180 are used as a scale for generating the shutdown signal SDS by which the timing control unit 130 turns off the power supply unit 125. [

The panel 160 includes sub-pixels SP arranged in a matrix form. The subpixels SP include red subpixels, green subpixels, and blue subpixels, and occasionally white subpixels. On the other hand, the panel 160 including the white subpixels can emit white light without emitting red, green, and blue light emission layers of the respective subpixels SP. In this case, the light emitted in white is converted into red, green and blue by the RGB color filter.

The sub-pixels included in the panel 160 are as follows.

FIG. 4 is a circuit diagram of a subpixel, FIG. 5 is an illustration of a compensation circuit shown in FIG. 4, and FIG. 6 is a driving waveform diagram of the subpixel shown in FIG.

One subpixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode D. When the compensation circuit CC is included, one scan line SL1 includes a first scan line EM, a second scan line INIT, and a third scan line SCAN.

The compensation circuit CC compensates the threshold voltage and the like of the driving transistor DT using the initialization voltage Vinit and the reference voltage Vref. The sub-pixel including the compensation circuit CC detects the threshold voltage of the driving transistor DT by a diode connection method or a source-follower method. The diode connection method has a lot of precedent data, so its explanation is omitted and a description is added to the source follower method as follows.

The source follower method connects a compensation capacitor between the gate-source electrode of the driving transistor DT and follows the source voltage of the driving transistor DT to the gate voltage when the threshold voltage is detected. Further, since the drain electrode of the driving transistor DT is separated from the gate electrode and is supplied with the power supply voltage from the first power supply line EVDD, the source follower scheme has not only a threshold voltage having a positive value but also a threshold having a negative value Voltage can be detected.

The source follower scheme floats the gate electrode of the driving transistor DT when the threshold voltage of the driving transistor DT is sensed and the compensation capacitor connected between the gate and source electrodes of the driving transistor DT and the driving transistor DT) parasitic capacitors to improve threshold voltage compensation capability.

The compensation circuit CC consists of one or more transistors and capacitors, which embodies the circuit configuration of the subpixel described in FIG. 4 above using an example of a compensation circuit using the source follower scheme described above.

As shown in FIG. 5, the compensation circuit CC includes a first transistor ST1, a second transistor ST2, a third transistor ST3, and a compensation capacitor Cgs. The first embodiment of the present invention is not limited to this but may be applied to a structure for compensating the threshold voltage of the driving transistor DT by using the reference voltage Vref All can be adopted.

The first transistor ST1 supplies the data voltage data stored in the node A (A) to the node B (B) in response to the emission control signal (em) supplied through the first scan line (EM). In the first transistor ST1, a gate electrode is connected to the first scan line EM, a first electrode is connected to the node A (A), and a second electrode is connected to the node B (B). The first transistor ST1 is a node voltage switching transistor.

The second transistor ST2 supplies the initialization voltage Vinit to the node C (C) in response to the initialization signal init supplied through the second scan line INIT. In the second transistor ST2, a gate electrode is connected to the second scan line INIT, a first electrode is connected to the node C, and a second electrode is connected to the initialization voltage stage VINIT. The second transistor ST2 is an initialization voltage supply transistor.

The third transistor ST3 supplies the reference voltage Vref to the node B (B) in response to the initialization signal init supplied through the second scan line INIT. The third transistor ST3 has the gate electrode connected to the second scan line INIT, the first electrode connected to the node B (B), and the second electrode connected to the reference voltage terminal VREF. The third transistor ST3 is a reference voltage supply transistor.

The compensation capacitor Cgs enables a source follower scheme when detecting the threshold voltage of the driving transistor DT and contributes to improvement of the compensation ability against the threshold voltage. The compensation capacitor Cgs is connected at one end to the gate electrode of the driving transistor DT and at the other end to the node C (C).

As the compensation circuit CC is configured as described above, the switching transistor SW supplies the data voltage Vdata to the node A (A) in response to the switching signal SCAN supplied through the third scan line SCAN do. In the switching transistor SW, a gate electrode is connected to the third scan line SCAN, a first electrode is connected to the node A (A), and a second electrode is connected to the first data line DL1. One end of the storage capacitor Cst is connected to the node A (A) and the other end is connected to the node C (C). In the driving transistor DT, a gate electrode is connected to the node B (B), a first electrode is connected to the node C (C), and a second electrode is connected to the first power supply line EVDD. In the organic light emitting diode OLED, the anode electrode is connected to the node C (C), and the cathode electrode is connected to the ground line EVSS. In the above description, the first electrode of the transistors is selected as the source electrode and the second electrode is selected as the drain electrode, but the present invention is not limited thereto.

6, the subpixel including the compensation circuit CC includes an initialization period Ti for initializing the nodes A, B and C (A, B, and C) to a specific voltage, A sensing period Ts for detecting and storing a threshold voltage, a programming period Tp for applying a data voltage Vdata, a driving current applied to the organic light emitting diode OLED using a threshold voltage and a data voltage Vdata, And a light emitting period Te for compensating the voltage regardless of the threshold voltage. Here, the light emission period Te is subdivided into the first and second light emission periods Te1 and Te2. For a more detailed discussion of the compensation circuit (CC), refer to Korean Application No. 10-2012-0095604.

As described above, the subpixel including the compensation circuit CC includes not only a normal power supply such as a general first power supply line EVDD and a ground line EVSS, but also a compensation voltage for compensating a threshold voltage of the driving transistor DT, (Vinit, Vref) are used.

Since a panel used for an organic light emitting display requires a higher current than a liquid crystal display panel, an overcurrent flows to a device included in a sub pixel when a short circuit occurs between the power sources. The cause of the short-circuit between the power sources is the internal structural factors such as particles, cracks, misalignment of the pad parts, narrow wiring layout, and external factors such as static electricity during the manufacturing process (or module process) A short occurs.

When a short circuit occurs between the power supplies, the compensation voltages (Vinit and Vref) also vary. The first embodiment of the present invention senses the compensation voltage (Vinit, Vref) influenced by a short circuit between power sources, senses whether or not there is a short circuit, and cuts off the power of the power supply unit. More specifically, .

FIG. 7 is a block diagram of a circuit according to the first embodiment of the present invention, FIG. 8 is a circuit diagram of the compensation voltage supply unit and the voltage sensing unit shown in FIG. 7, and FIG. And the constituent elements according to the example are constructed by organic electroluminescent display devices.

7, the compensation voltage supply unit 170 outputs compensation voltages Vinit and Vref including the initialization voltage Vinit and the reference voltage Vref. The compensation voltage supply unit 170 is selected as one of the examples shown in FIG. 2 or FIG.

The voltage sensing unit 180 includes a first voltage sensing unit 181 for sensing the initialization voltage Vinit and a second voltage sensing unit 182 for sensing the reference voltage Vref. The first and second voltage sensing units 181 and 182 compare the sensed compensation voltages Vinit and Vref with the threshold voltages set therein and output a resultant value.

The timing control section 130 includes a short detection section 135. The short detection unit 135 outputs a shutdown signal SDS that turns off the power supply unit 125 based on the resultant value output from the first and second voltage sensing units 181 and 182.

The first and second voltage sensing units 181 and 182 may differ only in the voltage supplied to the first and second threshold voltage stages and have the same or similar configuration. Therefore, the second voltage sensing unit 182 will be described below as an example.

As shown in FIG. 8, the compensation voltage supplier 170 amplifies the external power supply Vin and outputs a reference voltage Vref. The compensation voltage supply unit 170 may include an amplifier OPV and resistors R1, R2, and R3. The first resistor R1 is connected at one end to the external power supply Vin and at the other end to the first terminal (-) of the amplifier OPV. The second resistor R2 is connected at one end to the second terminal (+) of the amplifier OPV and at the other end to the third terminal O of the amplifier OPV. The third resistor R3 has one end connected to the third terminal O of the amplifier OPV and the other end connected to the output terminal.

The second voltage sensing unit 182 senses the reference voltage Vref. The second voltage sensing unit 182 includes a first comparator Comp1 sensing the lowest level of the reference voltage Vref and a second comparator Comp2 sensing the highest level of the reference voltage Vref. The first comparator Comp1 is connected to the first threshold voltage terminal -V1 through a first terminal -, the second terminal terminal + is connected to the output terminal of the compensation voltage supply unit 170, The output stage O is connected. In the second comparator Comp2, the first terminal - is connected to the output terminal of the compensation voltage supply unit 170, the second terminal + is connected to the second threshold voltage terminal -V2, and the output terminal is connected to the short detection unit do. The voltage supplied to the first threshold voltage terminal (-V1) and the second threshold voltage terminal (-V2) is selected as a negative voltage.

The first and second comparators Comp1 and Comp2 compare the sensed reference voltage Vref with the first and second threshold voltages set therein to determine whether the minimum level and the maximum level of the reference voltage Vref are out of the allowable range And outputs the result value.

As shown in FIG. 9, a plurality of scan drivers 140 are formed in the non-display area NA, which is outside both sides of the display area AA of the panel 160. The scan driver 140 is formed on the panel 160 together with the sub-pixel transistor process in a gate-in-panel manner. The data driver 150 is formed in a plurality of (for example, four) integrated circuits (ICs), mounted on a plurality of (for example, four) first flexible substrates 155, One side is attached and the other side is attached to a plurality (for example, two) of source circuit boards 157).

The timing control unit 130, the compensation voltage supply unit 170 and the voltage sensing unit 180 are formed on the control circuit board 134. The source circuit board 157 and the control circuit board 134 are connected by a second flexible substrate 137. The image processing unit 120 and the power supply unit 125 are formed on the system board 110. The control circuit board 134 and the system board 110 are connected by a third flexible board 115.

When the organic light emitting display device is configured as described above, the compensation voltage output from the compensation voltage supply unit 170 is supplied through the wiring formed up to the panel 160 via the control circuit board 134.

In the above description, the compensation voltage supply unit 170 and the voltage sensing unit 180 are formed on the control circuit board 134 as an example. However, the voltage sensing unit 180 may be formed at various positions such as being formed on the source circuit board 157.

Hereinafter, the output of the shutdown signal and the output state of the power supply unit will be described with an example of the lowest level and the highest level of the reference voltage and the case where the reference voltage is out of the allowable range.

FIG. 10 is a diagram for explaining a minimum level and a maximum level of a reference voltage, FIG. 11 is a view for explaining a tolerable range of a reference voltage, and FIG. 12 is a diagram for explaining an output state of a power supply unit according to a shutdown signal. Reference will now be made to Figs. 7 and 8 together with an understanding of the description.

As shown in FIG. 10, the reference voltage Vref is fixed to a specific voltage and output or is varied within a specific voltage range. Hereinafter, an example will be described in which the reference voltage Vref is fixed to -2.2V and output, the allowable range of the lowest level is set to -1V, and the allowable range of the highest level is set to -4V.

In such a case, the allowable range of the reference voltage Vref in Fig. 11 is? 3V level. Therefore, in FIG. 8, the first threshold voltage supplied to the first threshold voltage -V1 becomes -1V and the second threshold voltage supplied to the second threshold voltage -V2 becomes -4V.

- when the lowest and highest levels of the reference voltage are between -1V and -4V -

The lowest level reference voltage sensed by the first comparator Comp1 and the highest reference voltage sensed by the second comparator Comp2 are at a level between -1V and -4V. In this case, the short detection unit 135 regards the power supply of the panel as a normal state as shown in FIG. 11 and outputs a shutdown signal SDS of logic low L as in the first section T1 of FIG. 12 (Or no signal is output). At this time, the power supply unit 125 maintains the output of the output terminal Vout.

- When the minimum and maximum levels of the reference voltage are outside of -1 V to -4 V. -

The lowest level reference voltage sensed by the first comparator Comp1 and the highest reference voltage sensed by the second comparator Comp2 are outside the range of -1V to -4V. In this case, the short detection unit 135 regards the power supply of the panel as an abnormal state (Abnormal) as shown in FIG. 11 and outputs a shutdown signal SDS of logic high H like the second period T2 of FIG. 12 . At this time, the power supply unit 125 stops outputting the output terminal Vout and is turned off.

In the above description, the power supply unit 125 is turned off only when a shutdown signal SDS of logic high H is output. However, the power supply unit 125 may be designed to be turned off when the shutdown signal SDS of the logic low L is outputted.

Hereinafter, a method of driving the organic light emitting display according to the first embodiment of the present invention will be described.

13 is a flowchart illustrating a method of driving an organic light emitting display according to a first embodiment of the present invention. The driving method of FIG. 13 represents a method using at least one of the configurations described above, but the present invention is not limited thereto, and FIGS. 1 to 12 are also referred to together with the description of the driving method.

First, an image is displayed on the panel 160 (S110). Next, the compensation voltage (Vinit, Vref) supplied to the panel 160 is sensed (S120). Next, the compensation voltages Vinit and Vref are compared with the threshold voltages -V1 and -V2 (S130). Next, if the compensation voltages Vinit and Vref do not exceed the threshold voltages (-V1 and -V2) and satisfy the allowable range (N) (S150) The shutdown signal SDS for turning off the switch 125 is not output. Then, the panel 160 continues to display the image.

Alternatively, when the compensation voltages Vinit and Vref exceed the threshold voltages (-V1 and -V2) and are out of the allowable range (Y), it is determined that the operation is abnormal (S160) And outputs a shutdown signal SDS for turning off the switch 125 (S170). Thereafter, the panel 160 does not display the image.

The first embodiment of the present invention provides an organic light emitting display device and a method of driving the same that can sense a compensation voltage supplied when a compensation circuit is used for a subpixel to control a power supply unit when a short circuit or an overcurrent occurs between the power supply .

≪ Embodiment 2 >

FIG. 14 is a schematic configuration diagram of an organic light emitting display according to a second embodiment of the present invention, FIG. 15 is a view for schematically explaining the current sensing unit and the analog-digital conversion unit shown in FIG. 14, 15 is a circuit configuration diagram of the first block current sensing unit shown in FIG.

14, the organic light emitting display according to the second exemplary embodiment of the present invention includes an image processing unit 120, a power supply unit 125, a timing control unit 130, a data driving unit 150, a scan driving unit 140, a panel 160, a current sensing unit 190, and an analog-to-digital conversion unit 200.

In the case of the second embodiment, the subpixels SP included in the panel 160 may be configured with a structure including a compensation circuit as in the first embodiment, or may be configured with a conventional structure without a compensation circuit. However, the first power line (EVDD) wired to the panel 160 is divided into blocks and wired. In addition, the image processing unit 120, the power supply unit 125, the data driver 150, and the scan driver 140 may be configured to operate in the same manner as in the first embodiment, and thus description thereof will be omitted.

The current sensing unit 190 senses a current flowing through the first power supply line EVDD divided for each block and amplifies the sensed current for each block into an analog voltage for each block.

The analog-to-digital converter 200 converts the block-by-block analog voltage supplied from the current sensing unit 190 into a block-by-block digital voltage and outputs the digital voltage.

The timing controller 130 receives a digital voltage for each block through communication with the analog-to-digital converter 200, determines whether a short circuit or an overcurrent occurs in the panel 160 using a digital voltage for each block, And outputs a shutdown signal SDS that turns off the supply unit 125. [ Hereinafter, a communication interface between the timing controller 130 and the analog-to-digital converter 200 is selected as an SPI (Serial Peripheral Interface) of a serial communication system.

Unlike the first embodiment, the second embodiment is divided into the first power supply wiring (EVDD) blocks formed on the panel 160 and wired. The timing controller 130 determines whether an overcurrent occurs in the panel 160 through the current sensing unit 190 and the analog-digital converter 200 and turns off the power supply unit 125 when an overcurrent occurs.

As shown in FIG. 15, the data driver 150 includes a plurality of (for example, three) integrated circuits (ICs), a plurality of (for example, three) first flexible boards 155, Is attached to the pad portion of the panel (160). Although not shown, the other side of the first flexible substrate 155 is attached to the source circuit board.

The first power supply line EVDD is separated into a plurality of (e.g., three) power lines before passing through the plurality of first flexible boards 155. [ Accordingly, the first power supply line EVDD formed on the panel 160 is divided into blocks and wired. Hereinafter, the first power supply line EVDD formed on the panel 160 will be described as first to third block power supply lines EVDD1 to EVDD3.

The current sensing unit 190 includes a first block current sensing unit 190a to a third block current sensing unit 190c. The first block current sensing unit 190a senses the first block current i1 flowing through the first block power supply line EVDD1 and amplifies the sensed current by the first block analog voltage SV1. The second block current sensing unit 190b senses the second block current i2 flowing through the second block power supply line EVDD2 and amplifies the sensed current by the second block analog voltage SV2. The third block current sensing unit 190c senses the third block current i3 flowing through the third block power supply line EVDD3 and amplifies the sensed current by the third block analog voltage SV3.

The first to third block analog voltages (SV1 to SV3) sensed by the first block current sensing unit 190a to the third block current sensing unit 190c are supplied to the analog-digital conversion unit 200. [ The analog-to-digital converter 200 converts the first to third block analog voltages SV1 to SV3 into first to third block digital voltages. The first through third block digital voltages are supplied to the timing controller 130 through a communication line SPI between the analog-to-digital converter 200 and the timing controller 130.

The first block current sensing unit 190a to the third block current sensing unit 190c have the same configuration except that they are different in sensing position. Therefore, the first block current sensing unit 190a will be described below as an example.

As shown in FIG. 16, the first block current sensing unit 190a includes an amplifier OPR and resistors R1 through R6. The first block current sensing unit 190a senses the first block current i1 flowing between the first power supply line EVDD and the first block power supply line EVDD1 and flowing through the first block power supply line EVDD1, And converts it into a first block analog voltage SV1 and outputs it.

The first block current sensing unit 190a uses the voltage supplied to the positive voltage terminal V + and the negative voltage terminal V- when converting the current into the voltage. At this time, the voltage applied to the positive voltage terminal (V +) may be the scan high voltage output from the scan driver, but is not limited thereto.

In the meantime, the first block current sensing unit 190a is formed only of the amplifier OPR and the resistors R1 to R6. However, the first block current sensing unit 190a may further include capacitors and other passive elements.

The first and second resistors R1 and R2 are connected at one end to the first power supply line EVDD and at the other end to the first block power supply line EVDD1. The third resistor R3 is connected between one end of the first and second resistors R1 and R2 and the third terminal 3 of the amplifier OPR. The fourth resistor R4 is connected between one end of the first and second resistors R1 and R2 and the first terminal 1 of the amplifier OPR. The fifth resistor R5 is connected between the second and third terminals 2 and 3 of the amplifier OPR and the ground wiring. The sixth resistor R6 is connected between the first and fourth terminals 1 and 4 of the amplifier OPR and the ground line. The amplifier OPR has a first terminal 1 connected to a second terminal 2 at a negative voltage terminal V- and a fifth terminal 5 connected to a positive voltage terminal V + And outputs the block analog voltage SV1.

Hereinafter, a process of outputting the shutdown signal in conjunction with the analog-to-digital conversion unit, the timing control unit, and the power supply unit will be described.

FIG. 17 is a block diagram of an analog-to-digital converter, a timing controller, and a power supply unit, FIG. 18 is a waveform diagram for explaining a state in which the analog / digital converter operates in correspondence with a blank section, And the output state of the power supply unit according to the determination result.

As shown in FIGS. 17 to 20, the analog-to-digital converter 200 and the timing controller 130 send and receive commands via the bus lines SDI, SCLK, SDO, and CS included in the communication line SPI. At this time, the timing controller 130 is selected as the master and the analog-to-digital converter 200 is selected as the slave.

The timing controller 130 receives the first to n-th block digital voltages SV1 to SVn from the analog-digital converter 200 during the blank period VB. The timing controller 130 receives a digital voltage for each block for at least two blank periods VB and determines whether a short circuit or an overcurrent is generated based on the difference between the digital voltages. To this end, the timing controller 130 is supplied with a digital voltage for each block for at least two blank periods (VB) and receives the shutdown signal (VB) according to the result of the determination unit 131 and the determination unit 131, And a shutdown signal generation unit 136 for generating a shutdown signal SDS.

For example, the judging unit 131 judges whether or not the digital voltage (voltage) of the first to n < th > block digital voltages SV1 to SVn for the first order block from the analog / digital converting unit 200 during the first blanking period . After that, the determination unit 131 determines the digital voltage (s) for each of the first to the n-th block digital voltages (SV1 to SVn) for the second block from the analog-digital converter 200 during the second blank period .

The determination unit 131 compares the digital voltage of each first block with the digital voltage of each second block and if the difference is 0, the determination unit 131 determines that the panel is in a normal state in which no short or overcurrent occurs. At this time, the determination unit 131 supplies a logic low signal to the shutdown signal generation unit 136 or does not supply any signal. Accordingly, the output terminal Vout of the power supply unit 125 maintains the output.

Alternatively, when the difference between the digital voltage of the first block and the digital voltage of the second block is greater than 0 and the tolerance is out of range, the determination unit 131 determines that the panel is in an abnormal state Abnormal). At this time, the determination unit 131 supplies a signal of logic high to the shutdown signal generation unit 136. Accordingly, the output terminal Vout of the power supply unit 125 stops outputting and is turned off.

In FIG. 20, the first block digital voltage SV1 sensed during the second blank period VB rather than the first block digital voltage SV1 sensed during the first blank period VB is a voltage And has a value "Ab (V) ".

Since the first block digital voltage SV1 sensed during the second blank period VB has a voltage value Ab (V) that is out of the permissible range, the shutdown signal generator 136 outputs a logic low (L) And outputs the shutdown signal SDS of the logic high H. The output terminal Vout of the power supply unit 125 stops outputting and is turned off.

In the above description, the determination unit 131 and the shutdown signal generation unit 136 are functionally separated to facilitate understanding, and they can be integrated into one. In the present invention, the determination unit 131 and the shutdown signal generation unit 136 are included in the timing control unit 130, but they may be separately configured from the timing control unit 130. The allowable range described above can be set according to conditions such as a panel or an output power source.

Meanwhile, the components according to the second embodiment may be configured as an organic light emitting display device as in the first embodiment of FIG. At this time, both the current sensing unit 190 and the analog-digital converter 200 are formed on the control circuit board 134 or separately from the source circuit board 157 and the control circuit board 134.

Hereinafter, a driving method of an organic light emitting display according to a second embodiment of the present invention will be described.

21 is a flowchart illustrating a method of driving an organic light emitting display according to a second embodiment of the present invention. The driving method of FIG. 21 is only representative of a method using at least one of the configurations described above, and the present invention is not limited to this. For better understanding of the explanation, FIGS. 14 to 20 are also referred to.

First, an image is displayed on the panel 160 (S210). Next, the digital voltage for each first block is sensed through the first to third block power supply lines EVDD1 to EVDD3 on the panel 160 in step S220. Next, the digital voltage for each second block is sensed through the first to third block power supply lines EVDD1 to EVDD3 on the panel 160 (S230). Next, the digital voltage for each first block and the digital voltage for each second block are compared (S240). Next, it is determined whether the difference value between the digital voltage of the first block and the digital voltage of the second block exceeds the allowable range (S250). Next, if a difference between the digital voltage of the first block and the digital voltage of the second block is included in the allowable range (Y), a power supply unit (power supply unit The shutdown signal SDS that turns off the shutdown signal 125 is turned off. Then, the panel 160 continues to display the image.

Alternatively, if the difference between the digital voltage of the first block and the digital voltage of the second block exceeds the allowable range (N), it is determined that the abnormal operation (S270) And outputs a shutdown signal SDS for turning off the switch 125 (S280). Thereafter, the panel 160 does not display the image.

In the second embodiment of the present invention, the current flowing through the first power supply wiring divided into blocks on the panel is sensed at least twice and the power supply units can be controlled when a short circuit or an overcurrent occurs between the power supplies An organic electroluminescent display device and a driving method thereof.

The present invention provides an organic light emitting display device capable of eliminating the possibility that a local burnt of a device is spread to the front and leading to a fire by using a circuit for detecting whether a short circuit or an overcurrent is generated between power sources, There is an effect of providing a method.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

120: image processing unit 125: power supply unit
130: a timing controller 150: a data driver
140: scan driver 160: panel
170: compensation voltage supply unit 180: voltage sensing unit
Vinit, Vref: Compensation voltage 190: Current sensing unit
200: analog-to-digital conversion unit 135: short-
131: Determination unit 136: Shutdown signal generation unit
EVDD1 to EVDD3: first to third block power supply wiring

Claims (12)

panel;
A driving unit for driving the panel;
A power supply unit for supplying power to the panel;
A compensation voltage supplier for supplying a compensation voltage to the panel;
A voltage sensing unit that senses the compensation voltage output from the compensation voltage supply unit, compares the compensation voltage with a threshold voltage set therein, and outputs a resultant value; And
And a timing detector for controlling the driving unit and outputting a shutdown signal for turning off the power supply unit based on the result value,
The voltage sensing unit
And compares the compensation voltage with an internally set threshold voltage to determine whether a minimum level and a maximum level of the compensation voltage are out of the allowable range. delete The method according to claim 1,
The voltage sensing unit
A first comparator sensing a minimum level of the compensation voltage and a second comparator sensing a maximum level of the compensation voltage,
The first comparator has a first terminal connected to a first threshold voltage terminal, a second terminal connected to an output terminal of the compensation voltage supplier, an output terminal connected to the short detection unit,
Wherein the second comparator has a first terminal connected to an output terminal of the compensation voltage supply unit, a second terminal connected to a second threshold voltage terminal, and an output terminal connected to the short detection unit. The method of claim 3,
And the voltage supplied to the first threshold voltage terminal and the second threshold voltage terminal is a negative voltage. The method according to claim 1,
The compensation voltage
And an initialization voltage and a reference voltage supplied to the subpixels of the panel. Displaying an image on a panel;
Sensing a compensation voltage supplied to the panel;
Comparing the compensation voltage with a threshold voltage; And
And outputting a shutdown signal for turning off the power supply unit that supplies power to the panel when the compensation voltage is out of the allowable range,
The step of comparing the compensation voltage with the threshold voltage
And comparing the compensation voltage with the threshold voltage to determine whether a minimum level and a maximum level of the compensation voltage are out of a permissible range. delete A panel including power wiring separated by blocks;
A driving unit for driving the panel;
A power supply unit for supplying power through the power supply wiring divided into the blocks;
A current sensing unit for sensing a current flowing through the power supply wiring divided for each block, amplifying the sensed current for each block by an analog voltage for each block, and outputting the amplified current;
An analog-to-digital converter for converting the block-by-block analog voltage supplied from the current sensing unit into a block-by-block digital voltage and outputting the digital voltage; And
And a timing controller for controlling the driving unit and outputting a shutdown signal for determining whether an overcurrent is generated using the digital voltage for each block supplied from the analog-to-digital converter and for turning off the power supply when the overcurrent is generated, Display device. 9. The method of claim 8,
The timing control unit
The digital voltage for each of the first and second blocks and the digital voltage for the second block are supplied through the communication with the analog-
And compares the digital voltage of each of the first and second blocks with the digital voltage of each of the second blocks to output the shutdown signal when a difference between the digital voltage and the digital voltage of the second block is out of the allowable range. 10. The method of claim 9,
Wherein the digital voltage for each first block corresponds to a current per block sensed during a first blank period and the digital voltage for each second block corresponds to a current per block sensed during a second blank period. An electroluminescent display device. Displaying an image on a panel;
Sensing a digital voltage for each first block through a power supply line divided into blocks on the panel;
Sensing a digital voltage for each of the second blocks through a power supply line divided into blocks on the panel;
Comparing the digital voltage of the first block with the digital voltage of the second block and determining whether a difference between the digital voltage and the digital voltage of the second block is out of the allowable range; And
And outputting a shutdown signal for turning off the power supply unit for supplying power to the panel when the difference between the digital voltage of the first block and the digital voltage of the second block is out of the allowable range. A method of driving an electroluminescent display device. 12. The method of claim 11,
Wherein the digital voltage for each first block corresponds to a current per block sensed during a first blank period and the digital voltage for each second block corresponds to a current per block sensed during a second blank period. A method of driving an electroluminescent display device.

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