KR101477053B1 - Time to digital converter - Google Patents

Abstract

The present invention relates to a time-digital converter and a phase-locked loop circuit using the same.The time-digital converter according to an embodiment of the present invention includes: a first stage of delaying a start signal by a first delay time to compare a stop signal with the delayed start signal or delaying the stop signal by a second delay time to compare the delayed stop signal with the delayed start signal; a second stage of delaying the start signal output from the first stage by a third delay time to compare the stop signal output from the first stage with the third delayed start signal or delaying the stop signal output from the first stage by a forth delay time to compare the fourth delayed stop signal with the third delayed start signal; and a controller which circularly inputs the start signal and the stop signal output from the second stage a preset number of times, and changes the first to fourth delay times every circle.

Description

[0001] TIME TO DIGITAL CONVERTER [0002]

The present invention relates to a time-to-digital converter.

A time-to-digital converter is a circuit that converts time information into digital codes. If a start signal and a stop signal having different application times are input to the time-to-digital converter, the time-to-digital converter outputs a digital code corresponding to the time difference between the start signal and the stop signal.

There is a method of obtaining a digital code corresponding to a time difference between a start signal and a stop signal using a successive approximation register by a conventional time-digital conversion technique. However, the time-to-digital converter using this annual approximation method has a long time to be converted, and thus there is a limitation in applying to a high-performance ADPLL (All Digital Phase Locked Loop).

It is an object of the present invention to provide a time-to-digital converter having a shorter conversion time than that of the prior art.

It is an object of the present invention to provide a time-to-digital converter that can be implemented with a small circuit area.

The time-to-digital converter according to an embodiment of the present invention may delay the start signal by the first delay time, compare the stop signal with the delayed start signal, or delay the stop signal by the second delay time, A first stage for comparing the signal with a signal; A start signal output from the first stage is delayed by a third delay time, a stop signal output from the first stage is compared with a start signal delayed by the third delay time, A second stage for delaying the delayed signal by a fourth delay time and comparing the delayed signal with a start signal delayed by the third delay time; And a controller for cyclically inputting a start signal and a stop signal output from the second stage to the first stage by a predetermined number of times and changing the first to fourth delay times for each cycle.

The first stage includes: a first delay unit receiving the start signal and delaying the start signal by the first delay time; A second delay unit receiving the stop signal and delaying the stop signal by the second delay time; A first multiplexer receiving the stop signal and a stop signal delayed by the second delay time and outputting the stop signal; And a first phase comparing unit for receiving a start signal delayed by the first delay time and an output signal of the first multiplexing unit and comparing the received signals.

Wherein the second stage comprises: a third delay unit for receiving a start signal delayed by the first delay time and delaying the start signal by the third delay time; A fourth delay unit receiving the output signal of the first multiplexer and delaying the output signal by the fourth delay time; A second multiplexer for receiving an output signal of the first multiplexer and a stop signal delayed by the fourth delay time to output any one of the stop signals; And a second phase comparing unit receiving the start signal delayed by the third delay time and the output signal of the second multiplexing unit and comparing the received phase.

The first multiplexer receives the output signal of the second phase comparing unit as a control signal and can select either the stop signal or the stop signal delayed by the second delay time according to the control signal.

Wherein the second phase comparator outputs a first control signal when the start signal delayed by the third delay time is ahead of the output signal of the second multiplexer and the output signal of the second multiplexer is delayed by the third delay time If it is before the delayed start signal, it can output the second control signal.

Wherein when the first control signal is received from the second phase comparing unit, the first multiplexing unit selects and outputs the stopping signal, and when receiving the second control signal from the second phase comparing unit, It is possible to select and output the stop signal delayed by the second delay time.

The second multiplexer receives the output signal of the first phase comparator as a control signal and can select any one of the output signal of the first multiplexer and the stop signal delayed by the fourth delay time according to the control signal.

Wherein the first phase comparator outputs a first control signal when the start signal delayed by the first delay time is ahead of the output signal of the first multiplexer and the output signal of the first multiplexer is delayed by the first delay time If it is before the delayed start signal, it can output the second control signal.

Wherein the second multiplexer selects and outputs the output signal of the first multiplexer when receiving the first control signal from the first phase comparator and inputs the second control signal from the second phase comparator And if so, select and output a stop signal delayed by the fourth delay time.

Wherein the controller controls the first stage such that the first delay time is one half of the second delay time and the third delay time is one half of the first delay time, The second stage can be controlled to be half the second delay time.

The controller may control the first and second stages such that the first through fourth delay times are each one-fourth of the first through fourth delay times in the previous cycle for each cycle.

The time-to-digital converter may further include a counter receiving the start signal output from the second stage and counting the number of times the start signal is input.

The controller comprising:

The start signal is input to the first stage and the start signal output from the second stage is cyclically inputted to the first stage until the stop signal is ahead of the start signal in the second stage, Enabling the counter to count the number of times the start signal is input, maintaining the first through fourth delay times at the same value,

And when the stop signal precedes the start signal in the second stage, a start signal and a stop signal output from the second stage are cyclically input to the first stage by the predetermined number of times, and the counting of the counter is stopped The first to fourth delay times may be shortened for each cycle.

The time-to-digital converter according to an embodiment of the present invention can be used in a phase locked loop circuit.

According to the embodiment of the present invention, it is possible to shorten the time required for time-to-digital conversion compared with the conventional method.

According to embodiments of the present invention, a time-to-digital converter can be implemented with a small circuit area.

1 is an exemplary block diagram schematically illustrating a time-to-digital converter according to an embodiment of the present invention.
Figure 2 is an exemplary block diagram illustrating the time-to-digital converter in more detail in accordance with an embodiment of the present invention.
3 is an exemplary diagram for explaining a time relationship between a start signal and a stop signal applied to the first and second stages according to an embodiment of the present invention.
4 is an exemplary block diagram illustrating a time-to-digital converter in accordance with another embodiment of the present invention.
5 is an exemplary diagram for explaining a time relationship between a start signal and a stop signal applied to the first and second stages according to another embodiment of the present invention.

Other advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

Unless defined otherwise, all terms (including technical or scientific terms) used herein have the same meaning as commonly accepted by the generic art in the prior art to which this invention belongs. Terms defined by generic dictionaries may be interpreted to have the same meaning as in the related art and / or in the text of this application, and may be conceptualized or overly formalized, even if not expressly defined herein I will not.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms' comprise 'and / or various forms of use of the verb include, for example,' including, '' including, '' including, '' including, Steps, operations, and / or elements do not preclude the presence or addition of one or more other compositions, components, components, steps, operations, and / or components. The term 'and / or' as used herein refers to each of the listed configurations or various combinations thereof.

1 is an exemplary block diagram schematically illustrating a time-to-digital converter 100 according to one embodiment of the present invention.

As shown in FIG. 1, the time-to-digital converter 100 may include a first stage 110, a second stage 120, and a controller 130.

The first stage 110 may delay the start signal by a first delay time and then compare the stop signal with the delayed start signal or may compare the stop signal with the delayed start signal by delaying the stop signal by a second delay time .

The second stage 120 delays a start signal output from the first stage 110 by a third delay time and then outputs a stop signal output from the first stage to a start signal delayed by the third delay time Or may compare the stop signal output from the first stage with a start signal delayed by the third delay time by a fourth delay time.

The controller 130 cyclically inputs a start signal and a stop signal output from the second stage 120 to the first stage 110 by a predetermined number of times and outputs the first to fourth delay times Can be changed.

As described above, the time-to-digital converter 100 according to the embodiment of the present invention includes two stages 110 and 120, and processes the start signal and the stop signal in a cyclic structure, thereby performing fast time-to- Can be achieved.

2 is an exemplary block diagram illustrating the time-to-digital converter 100 in more detail in accordance with an embodiment of the present invention.

2, the first stage 110 may include a first delay unit 111, a second delay unit 112, a first multiplex unit 113, and a first phase comparison unit 114 have. The second stage 120 may include a third delay unit 121, a fourth delay unit 122, a second multiplex unit 123, and a second phase comparison unit 124.

The first delay unit 111 may receive a start signal and delay the received signal by a first delay time. The second delay unit 112 may receive the stop signal and delay the delay signal by a second delay time.

The first multiplexer 113 receives the stop signal and the stop signal delayed by the second delay time, and outputs the stop signal.

The first phase comparator 114 receives the start signal delayed by the first delay time and the output signal of the first multiplexer 113 and compares the received phase.

According to one embodiment, the first and second delay units 111 and 112 receive the control signal from the controller 130 and delay the start signal and the stop signal by a delay time determined based on the control signal . That is, the first and second delay times of the first and second delay units 111 and 112 may be adjusted by the controller 130. [

As shown in FIG. 2, the first stage 110 may further include a pulse generation unit 115 at the inputs of the first and second delay units 111 and 112. When the start signal and the stop signal are input to the pulse generation unit 115, the pulse generation unit 115 generates and outputs a pulse signal, and the pulse signal is supplied to the first and second delay units 111 and 112, .

The first multiplexer 113 receives the stop signal and the output signal of the second delay unit 112 and can output any one of the two signals.

According to an embodiment of the present invention, the first multiplexer 113 receives the output signal (output 2) of the second phase comparator 124 and outputs the stop signal and the second It is possible to select any one of the output signals of the delay unit 112 and output it.

The first phase comparator 114 receives the start signal delayed by the first delay unit 111 by the first delay time and the output signal of the first multiplexer 113 and compares the phases.

According to one embodiment, the first phase comparing unit 114 may compare the phases of the two received signals and output different signals according to the relationship between the two signals.

For example, when the output signal of the first delay unit 111 is ahead of the output signal of the first multiplexer 113, the first phase comparator 114 outputs a signal having a logic level of 0 When the output signal of the first multiplexer 113 is higher than the output signal of the first delay unit 111, the first phase comparator 114 may output a signal having the logic level 1. However, The logic level of the output signal (output 1) of FIG.

As shown in FIG. 2, the first delay unit 111 may further include a dummy multiplexer 116 corresponding to the first multiplexer 113 at an output end thereof. The dummy multiplexing unit 116 has the same circuit delay as that of the first multiplexing unit 113 so that the same circuit delay is applied to the start signal and the stop signal.

As described above, the second stage 120 may include a third delay unit 121, a fourth delay unit 122, a second multiplex unit 123, and a second phase comparison unit 124 .

The third delay unit 121 receives the start signal delayed by the first delay time and may delay the start signal by the third delay time. The fourth delay unit 122 may receive the output signal of the first multiplexer 113 and delay the received signal by a fourth delay time.

The second multiplexer 123 may receive one of the output signal of the first multiplexer 113 and the stop signal delayed by the fourth delay time.

The second phase comparator 124 receives the start signal delayed by the third delay time and the output signal of the second multiplexer 123, and compares the received phase.

According to one embodiment, the third and fourth delay units 121 and 122 receive a control signal from the controller 130 and delay the start signal and the stop signal by a delay time determined based on the control signal . In other words, as with the first and second delay times, the third and fourth delay times of the third and fourth delay units 121 and 122 may be adjusted by the controller 130 as well.

The second multiplexer 123 receives the output signal of the first multiplexer 113 and the output signal of the fourth delay unit 122 and outputs either one of the two signals.

According to an embodiment of the present invention, the second multiplexer 123 receives the output signal (output 1) of the first phase comparator 114 and outputs the output signal of the first multiplexer 113 And the output signal of the fourth delay unit 122, and output the selected signal.

The second phase comparator 124 receives the start signal delayed by the third delay unit 121 by the third delay time and the output signal of the second multiplexer 123 to compare phases.

According to an embodiment, the second phase comparator 124 may compare the phases of the two received signals and output different signals according to the relationship between the two signals.

For example, when the output signal of the third delay unit 121 is ahead of the output signal of the second multiplexer 123, the second phase comparator 124 outputs a signal having a logic level of 0 When the output signal of the second multiplexer 123 is higher than the output signal of the third delay unit 121, the first phase comparator 124 may output a signal having a logic level of 1, The logic level of the output signal (output 2) is not limited to this.

Like the first stage 110, the third delay unit 121 may further include a dummy multiplexer 125 corresponding to the second multiplexer 123 at an output end. The dummy multiplexer 125 has the same circuit delay as the circuit delay of the second multiplexer 123 so that the same circuit delay is applied to the start signal and the stop signal.

As described above, the first multiplexer 113 receives the output signal (output 2) of the second phase comparator 124 as a control signal, and outputs the stop signal and the stop signal in accordance with the second delay time And can select any one of the delayed stop signals.

According to one embodiment, when the start signal delayed by the third delay time is ahead of the output signal of the second multiplexer 123, the second phase comparator 124 outputs a first control signal And outputs a second control signal (e.g., a signal having a logic level of 1) when the output signal of the second multiplexer 123 is ahead of the start signal delayed by the third delay time can do.

In this case, when the first multiplexer 113 receives the first control signal from the second phase comparator 124, the first multiplexer 113 may select and output a stop signal among the two input signals. In contrast, when the second multiplexer 113 receives the second control signal from the second phase comparator 124, the first multiplexer 113 selects and outputs a stop signal delayed by the second delay time from the two input signals .

Similarly, the second multiplexer 123 receives the output signal (output 1) of the first phase comparator 114 as a control signal, and outputs the output signal of the first multiplexer 113 And a stop signal delayed by the fourth delay time.

According to one embodiment, when the start signal delayed by the first delay time is ahead of the output signal of the first multiplexer 113, the first phase comparator 114 outputs a first control signal And outputs a second control signal (e.g., a signal having a logic level of 1) when the output signal of the first multiplexer 113 is ahead of the start signal delayed by the first delay time can do.

In this case, when the first multiplexer 123 receives the first control signal from the first phase comparator 114, the second multiplexer 123 selects the output signal of the first multiplexer 113 among the two input signals And output it. In contrast, when the second multiplexer 123 receives the second control signal from the second phase comparator 124, the second multiplexer 123 selects and outputs a stop signal delayed by the fourth delay time from the two input signals .

As described above, the output signal (output 1) output from the first phase comparing unit 114 of the first stage 110 is input to the second multiplexing unit 123 of the second stage 120, And the output signal (output 2) output from the second phase comparing unit 124 of the second stage 120 is supplied to the first multiplexing unit 113 of the first stage 110 It is possible to determine whether the stop signal is input and delayed by the second delay time.

The controller 130 may cause the first stage 110 to cyclically input a start signal and a stop signal output from the second stage 120 by a predetermined number of times.

As shown in FIG. 2, the first stage 110 may further include a third multiplexer 117 and a fourth multiplexer 118 at an input end.

The third multiplexer 117 receives the start signal and the start signal output from the second stage 120, and outputs one of the signals. The fourth multiplexer 118 receives the stop signal and the stop signal output from the second stage 120, and outputs the stop signal.

According to one embodiment, the third and fourth multiplexers 117 and 118 receive a control signal from the controller 130, select one of the two input signals based on the control signal, .

For example, when the start signal and the stop signal are not input to the time-to-digital converter 100, the controller 130 selects the start signal and the stop signal from the third and fourth multiplexers 117 and 118, respectively .

As described above, when the start signal and the stop signal are circulated through the first and second stages 110 and 120, the third and fourth multiplexers 117 and 118 respectively output the 2 stage 120 and the start signal and the stop signal output from the two stages 120 can be controlled.

When the start signal and the stop signal are cyclically processed a predetermined number of times, the third and fourth multiplexers 117 and 118 may respectively control the start signal and the stop signal to be selected.

As described above, the start signal and the stop signal may be sequentially and cyclically processed by the controller 130 through the first and second stages 110 and 120 a predetermined number of times.

According to an embodiment of the present invention, the controller 130 may change the first to fourth delay times for each cycle of the start signal and the stop signal.

In this case, the first and third delay times for the start signal may be set shorter than the second and fourth delay times for the stop signal, respectively.

For example, the controller 130 may control the first stage 110 such that the first delay time is half of the second delay time. Also, the controller 130 may control the second stage 120 such that the third delay time is half of the fourth delay time.

The controller 130 may control the second stage 120 such that the third delay time is half of the first delay time and the fourth delay time is half of the second delay time have.

Further, the controller 130 controls the first and second stages 110 and 120 so that the first through fourth delay times become one fourth of the first through fourth delay times in the previous cycle Can be controlled.

FIG. 3 is an exemplary diagram illustrating a time relationship between a start signal and a stop signal applied to the first and second stages 110 and 120 according to an embodiment of the present invention.

As shown in FIG. 3, the start signal applied to the first stage 110 for the first time is ahead of the stop signal by the time T (see (i) of FIG. 3).

According to one embodiment, the controller 130 sets a first delay time at the first rotation to the T _1/2, and the second delay time to set, and the third delay time to T ₁ to T _1/4 And the fourth delay time can be set to T _1/2 . Here, T ₁ may be a predetermined time.

As a result, the start signal is delayed by the first delay time T _1/2 by the first delay unit 111 in the first stage 110, and the stop signal is delayed by the second delay unit 112 Delayed by the second delay time T ₁ . The first multiplexer 113 selects a non-delayed pause signal among the two input signals.

Therefore, even if the first delay time is delayed by T _{1/2, since the} start signal is still ahead of the stop signal (see (ii) in FIG. 3), the first phase comparator 114 compares the first And outputs a control signal.

Then, the start signal is delayed by the third delay time of T _1/4 by a third delay unit 121 in the second stage 120, the stop signal by the fourth delay unit 122 And is delayed by the fourth delay time T _1/2 .

However, since the first phase comparator 114 outputs the first control signal having the logic level of 0, the second multiplexer 123 outputs the first control signal having the first logic level of 0, And selects an output signal of the multiplexing unit 113. [

As a result, in the third delay time of T _1/4 delayed start signal as is, because becomes far behind stop signal (see (iii) in Fig. 3), the second phase comparator 124 is logic level 1 claim 2 control signal.

Thus, when the first circulation is completed, the start signal and the stop signal output from the second stage 120 are input to the first stage 110 again.

In this case, setting the controller 130 sets a first delay time for the second cycle as T _1/8, and sets a second delay time to T _1/4, and the third delay time to T _1/16 and second by setting the fourth delay time by T _1/8, the two first to fourth first to latency such that one-fourth of the fourth delay time and the delay time of each of the first cycle at the time of the second cycle Change it.

Wherein the beginning of re-entering the first stage 110, the signal is delayed by a first delay time of T _1/8 by the first delay unit 111, a stop signal is a second by a delay unit 112 It is delayed by a delay time of T _1/4.

Since the second phase comparator 124 outputs the second control signal having the logic level of 1, the first multiplexer 113 selects the output signal of the second delay unit 112 from among the two input signals do.

Accordingly, the first (see (iv) in Fig. 3) a delay time of T _1/8 delayed start signal as is ahead than the delayed signal to stop again by a second delay time of T _1/4, the first phase comparator (114) outputs a first control signal having a logic level of 0.

In this way, the start signal and the stop signal input to the time-to-digital converter 100 are cyclically processed a predetermined number of times, and the controller 130 changes the first to fourth delay times at every cycle.

Wherein the first delay time is set to half of the second delay time, the third delay time is set to half of the first delay time, and the fourth delay time is set to half of the second delay time Lt; / RTI > And, the first to fourth delay times for each cycle are each set to 1/4 of the first to fourth delay times in the previous cycle.

According to one embodiment of the present invention, the controller 130 sets the third and fourth delay times of the second stage 120 when the start signal and the stop signal are processed in the first stage 110, When the start signal and the stop signal are processed in the second stage 120, the first and second delay times of the first stage 110 can be set.

As a result, the delays required for setting the delay time in each stage can be removed, and the start signal and the stop signal can be continuously and seamlessly processed in the first and second stages 110 and 120 without interruption.

4 is an exemplary block diagram illustrating a time-to-digital converter 100 according to another embodiment of the present invention.

The time-to-digital converter 100 shown in Fig. 4 further includes a counter 140 in the time-to-digital converter 100 shown in Fig.

The counter 140 may receive the start signal output from the second stage 120 and may count the number of times the start signal is input. In other words, the counter 140 may count the number of cycles of the start signal.

According to this embodiment, the time-to-digital converter 100 may perform another time-to-digital conversion operation using the counter 140 prior to the time-to-digital conversion operation described with reference to FIG.

For example, the controller 130 may control the output of the second stage 120 from the second stage 120 until the start signal is input to the first stage 110 and the stop signal precedes the start signal in the second stage 120. [ To the first stage (110).

3, in which the start signal is input to the first stage 110 and the second signal is input to the second stage 120. In this embodiment, Repeatedly processes the start signal until the stop signal becomes ahead of the start signal.

Also, the controller 130 may enable the counter 140 to count the number of times the counter 140 counts the number of times the start signal is input. As a result, the counter 140 counts the number of cycles of the start signal and outputs the count.

At this time, the controller 130 may maintain all the first through fourth delay times at the same value. That is, in the time-digital conversion using the counter 140, the first to fourth delay times are always equal to T ₀ . Here, the T ₀ may be a time determined in advance.

As a result, the time difference between the start signal and the stop signal obtained by the time-digital conversion using the counter 140 is 2T ₀ (the sum of the first and third delay times) the number of times the cyclic process starting signal N 2T ₀ × N.

Then, when the stop signal is ahead of the start signal in the second stage 120, the controller 130 outputs the start signal and the stop signal output from the second stage 120 to the first stage 110 And can be cyclically input a predetermined number of times.

That is, when the stop signal is ahead of the start signal in the second stage 120, the time-to-digital converter 100 may perform the time-to-digital conversion operation described with reference to FIG.

At this time, the controller 130 may disable the counter 140 to stop counting the counter 140. And, as described above, the first to fourth delay times can be changed, that is, shortened every cycle.

5 is an exemplary diagram for explaining the time relationship between the start signal and the stop signal applied to the first and second stages 110 and 120 according to another embodiment of the present invention.

As shown in FIG. 5, the start signal applied to the first stage 110 is ahead of the stop signal by time T '(see (i) of FIG. 5).

In this embodiment, the controller 130 receives the start signal from the second stage 120 until the start signal is input to the first stage 110 and the stop signal precedes the start signal in the second stage 120, To the first stage (110).

The counter 140 counts the number of times the start signal is input and outputs the counted number.

Also, the first to fourth delay times set in the first to fourth delay units 111, 112, 121, and 122 are all maintained at the same value T ₀ .

As a result, the start signal input to the first stage 110 is delayed by the first delay time T ₀ and applied to the second stage 120 (see (ii) of FIG. 5). Similarly, the start signal input to the second stage 120 is delayed by the third delay time T ₀ , and is then applied to the first stage 110 again.

The cyclic process of the same start signal is the second, and the stop signal from the stage 120 repeated N times until ahead of the start signal, so that the start signal is delayed by 2T ₀ per one rotation (Fig. 5 (iii ), (iv)).

When the stop signal is ahead of the start signal in the second stage 120, the start signal and the stop signal output from the second stage 120 are cyclically input to the first stage 110 (v)).

At this time, the counter 140 is disabled and stops counting, and outputs a binary code corresponding to N-1 obtained by subtracting 1 from N, which is the number of cycles of the start signal.

The operation performed at this point is the same as the time-to-digital conversion operation described with reference to Fig. 3 (see Fig. 5 (vi)).

The time-to-digital converter 100 according to an embodiment of the present invention receives a start signal and a stop signal and outputs the time difference between the signals to a digital code output from the first and second phase comparators 114 and 124, To the digital code output from the counter 140 and the first and second phase comparison units 114 and 124. [

According to the embodiment of the present invention, it is possible to realize a time-to-digital converter having a shorter conversion time with a smaller circuit area than the conventional one.

And, the time-to-digital converter according to the embodiment of the present invention can be used in a phase locked loop circuit.

100: time-to-digital converter
110: First stage
111: first delay unit
112: second delay unit
113: first multiplexer
114: first phase comparison unit
115:
116: dummy multiplexing unit
117: third multiplexer
118: fourth multiplexer
120: second stage
121: third delay unit
122: fourth delay unit
123: second multiplexer
124: second phase comparison unit
125: dummy multiplexing unit
130:
140: Counter

Claims (14)

A first stage for delaying a start signal by a first delay time, comparing a stop signal with a phase of the delayed start signal, or delaying the stop signal by a second delay time and comparing the phase with the delayed start signal;
A start signal output from the first stage is delayed by a third delay time, a stop signal output from the first stage is compared with a phase of a start signal delayed by the third delay time, A second stage for delaying the stop signal by a fourth delay time and comparing the phase with a start signal delayed by the third delay time; And
A controller for cyclically inputting a start signal and a stop signal output from the second stage to the first stage by a predetermined number of times and changing the first to fourth delay times for each loop;
To-digital converter. The method according to claim 1,
The first stage comprises:
A first delay unit receiving the start signal and delaying the start signal by the first delay time;
A second delay unit receiving the stop signal and delaying the stop signal by the second delay time;
A first multiplexer receiving the stop signal and a stop signal delayed by the second delay time and outputting the stop signal; And
A first phase comparator for receiving a start signal delayed by the first delay time and an output signal of the first multiplexer and comparing the received signals;
To-digital converter. 3. The method of claim 2,
The second stage comprising:
A third delay unit receiving a start signal delayed by the first delay time and delaying the start signal by the third delay time;
A fourth delay unit receiving the output signal of the first multiplexer and delaying the output signal by the fourth delay time;
A second multiplexer for receiving an output signal of the first multiplexer and a stop signal delayed by the fourth delay time to output any one of the stop signals; And
A second phase comparing unit receiving a start signal delayed by the third delay time and an output signal of the second multiplexing unit and comparing phases of the signals;
To-digital converter. The method of claim 3,
Wherein the first multiplexer receives the output signal of the second phase comparator as a control signal and selects either the stop signal or the stop signal delayed by the second delay time according to the control signal. 5. The method of claim 4,
Wherein the second phase comparison unit comprises:
And outputs a first control signal when the start signal delayed by the third delay time precedes the output signal of the second multiplexer,
And outputs a second control signal when the output signal of the second multiplexing unit is ahead of the start signal delayed by the third delay time. 6. The method of claim 5,
Wherein the first multiplexer comprises:
When receiving the first control signal from the second phase comparing unit, selecting and outputting the stopping signal,
And a stop signal delayed by the second delay time when the second control signal is received from the second phase comparing unit. The method of claim 3,
Wherein the second multiplexer receives the output signal of the first phase comparator as a control signal and selects one of the output signal of the first multiplexer and the stop signal delayed by the fourth delay time according to the control signal, Digital converter. 8. The method of claim 7,
Wherein the first phase comparator comprises:
And outputs a first control signal when the start signal delayed by the first delay time precedes the output signal of the first multiplexer,
And outputs a second control signal when the output signal of the first multiplexer is ahead of the start signal delayed by the first delay time. 9. The method of claim 8,
Wherein the second multiplexer comprises:
And outputs the first control signal when the first control signal is received from the first phase comparing unit,
And a stop signal delayed by the fourth delay time when the second control signal is received from the second phase comparing unit. The method according to claim 1,
The controller comprising:
Controlling the first stage such that the first delay time is half of the second delay time,
Wherein the third delay time is half of the first delay time and the fourth delay time is half of the second delay time. The method according to claim 1,
The controller comprising:
Wherein the first and second delay times are controlled so that the first to fourth delay times are one-fourth of the first to fourth delay times in the previous cycle for each cycle. The method according to claim 1,
Further comprising: a counter receiving the start signal output from the second stage and counting the number of times the start signal is input. 13. The method of claim 12,
The controller comprising:
The start signal is input to the first stage and the start signal output from the second stage is cyclically inputted to the first stage until the stop signal is ahead of the start signal in the second stage, Enabling the counter to count the number of times the start signal is input, maintaining the first through fourth delay times at the same value,
And when the stop signal precedes the start signal in the second stage, a start signal and a stop signal output from the second stage are cyclically input to the first stage by the predetermined number of times, and the counting of the counter is stopped To disable the counter, and to shorten the first to fourth delay times for each cycle. delete

Images