KR101441385B1 - Driving apparatus for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof, which can improve a picture quality by compensating a charging rate of an image signal according to a display region of an image while maintaining a driving period of each frame at a constant level.

To this end, a liquid crystal display device of the present invention includes: a liquid crystal panel formed with a plurality of pixel regions; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; And supplying data and gate control signals to the data driver so that the charging period of the video signal is reduced or increased according to the video display region of the liquid crystal panel, And a timing controller for generating and controlling the data and the gate driver.

Timing controller, gate and data control signal, horizontal period (1H)

Description

[0001] The present invention relates to a driving apparatus for a liquid crystal display device and a method of driving the same,

The present invention relates to a liquid crystal display device, and more particularly, to a driving device of a liquid crystal display device capable of improving image quality by compensating a charging rate of a video signal according to a display region of an image while maintaining a constant driving period of each frame, Driving method.

Description of the Related Art [0002] In recent years, lightweight thin flat panel displays have been mainly used as image display devices used in monitors for personal computers, portable terminals, and various information devices. As such flat panel display devices, a liquid crystal display, a light emitting display, a plasma display panel, a field emission display, and the like are emerging.

Among them, the liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel having a plurality of pixel cells and displaying an image, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner and a pixel cell is positioned in an area defined by vertically crossing gate lines and data lines. Pixel electrodes and a common electrode for applying an electric field to each pixel cell are formed. Each pixel electrode is connected to a thin film transistor (TFT) as a switching element. The TFT is turned on by the scan pulse of the gate line so that the video signal from the data line is charged to the pixel electrode.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a timing controller for supplying a control signal for controlling the gate driver and the data driver.

Here, the data driver converts image data from the timing controller into an analog image signal, and then selects a gamma voltage having a predetermined level according to the gradation value of the analog image signal. Then, the selected gamma voltages are supplied to the data lines as video signals, respectively.

The gate driver sequentially generates a plurality of scan pulses and sequentially supplies the plurality of scan pulses to a plurality of gate lines. In other words, the gate driver sequentially supplies a scan pulse, for example, a gate-on voltage in accordance with a control signal supplied from the timing controller. Then, the gate-off voltage is supplied during a period in which the gate-on voltage is not supplied to each gate line.

The timing controller arranges image data from the outside so as to be suitable for driving the liquid crystal panel and supplies the image data to the data driver. A gate control signal and a data control signal are generated using external synchronization signals to control the data driver and the gate driver.

However, the liquid crystal display having the above-described structure and displaying an image has a disadvantage in that the image quality is lowered due to the RC time constant applied to the gate and data lines of the liquid crystal panel.

Specifically, recently, as the liquid crystal display becomes larger and higher in resolution, the load including the resistance (R) and the capacitor (C) components of the liquid crystal panel increases and the scan pulse or image signals applied to the respective pixel cells are distorted do. In particular, the gate and data lines increase as the distance from the timing controller, gate, and data driver increases. Accordingly, the brightness of a displayed image in a region located far away from the timing controller, the gate, and the data driver becomes more uneven, flicker and unevenness occur, and image quality deteriorates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a driving apparatus for a liquid crystal display device capable of improving image quality by compensating a charging rate of a video signal according to a display region of an image, And a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving a liquid crystal display, including: a liquid crystal panel including a plurality of pixel regions; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; And supplying data and gate control signals to the data driver so that the charging period of the video signal is reduced or increased according to the video display region of the liquid crystal panel, And a timing controller for generating and controlling the data and the gate driver.

Wherein the timing controller comprises: an image processor for aligning the image data from the outside using at least one of synchronizing signals inputted from the outside to suit the driving of the liquid crystal panel and supplying the image data to the data driver; A data control signal generator for generating the data control signal so as to gradually increase the supply period of the video signal and supplying the data control signal to the data driver using at least one of the synchronization signals, And a gate control signal generator for generating the gate control signal so as to gradually increase the output period of the gate-on voltage and supplying the gate control signal to the gate driver.

The data control signal generation unit may include a line counter for generating a counter signal in units of horizontal periods using at least one of the synchronization signals, a first setting value for each horizontal line stored in advance, And a SOE generator for converting a pulse width according to the line-specific setting value to generate a converted SOE signal.

The gate control signal generator includes a second look-up table for storing a second set value for each line and outputting a corresponding line-dependent setting value according to a counter signal input from the line counter, and a second look- And a GOE generator for converting the pulse width according to the line-specific setting value input from the GOE generator to generate a converted GOE signal.

The setting value of at least one of the first and second setting values may be set such that an initial horizontal period (1H) is reduced to a minimum period in which an image can be displayed, and a subsequent horizontal period is set in a range And is a counter value or a delay value set to be gradually increased.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display (LCD) device including a liquid crystal panel, a data driver, a gate driver, and a timing controller The method comprising: aligning image data input from the outside in accordance with driving of the liquid crystal panel; And controlling the data and gate driver to generate a data and gate control signal so that the charging period of the video signal is reduced or increased according to the video display area of the liquid crystal panel.

The data and gate driver control step may include generating the data control signal such that the supply period of the video signal is gradually increased by using at least one of synchronous signals input from the outside and supplying the data control signal to the data driver, And generating the gate control signal so that the output period of the gate-on voltage is gradually increased by using at least one of the synchronization signals, and supplying the gate control signal to the gate driver.

The data control signal generation step may include generating a counter signal in units of horizontal periods by using at least one of the synchronization signals, storing a first set value for each predetermined horizontal line, setting each line according to the counter signal, And converting the pulse width according to the line-specific setting value to generate a converted SOE signal and supplying the converted SOE signal to the data driver.

The gate control signal generation step includes the steps of: storing a preset second set value for each line and outputting a set value for each line according to the counter signal; and converting the pulse width according to the corresponding line- And supplying the gate driver to the gate driver.

The setting value of at least one of the first and second setting values may be set such that an initial horizontal period (1H) is reduced to a minimum period in which an image can be displayed, and a subsequent horizontal period is set in a range And is a counter value or a delay value set to be gradually increased.

In the driving apparatus and the driving method of the liquid crystal display apparatus according to the present invention, the charging rate of the video signal is compensated according to the video display region of the liquid crystal panel while the driving period of one frame is kept constant It is possible to prevent the luminance unbalance phenomenon and the flicker and to improve the display quality of the image.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention having the above-described features and effects will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

The liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 2 formed with a plurality of pixel regions; A data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; The gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2 and the image data RGB inputted from the outside are arranged in accordance with the driving of the liquid crystal panel 2, And data and gate control signals (GCS, DCS) are generated to reduce or increase the charging period of the video signal according to the video display area of the liquid crystal panel 2, And a timing controller 8 for controlling the timing controller 8.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies a data signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating film interposed therebetween. Alternatively, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

The data driver 4 is connected to the timing controller 8 using a source start pulse SSP and a source shift clock SSC among data control signals DCS from the timing controller 8. [ And converts the image data (Data), which are arrayed from the image data, into an analog voltage, that is, a video signal. Then, the image signal is supplied to each of the data lines DL1 to DLm in response to a transform source output enable (tSOE) signal whose pulse width increases every horizontal period. At this time, the data driver 4 increases the period of outputting the video signal according to the tSOE signal. The output period of the video signal gradually increases in every horizontal period. Specifically, the data driver 4 latches the image data Data input in accordance with the SSC, and thereafter supplies a scan pulse to each of the gate lines GL1 to GLn in response to the tSOE signal, To each of the data lines DL1 to DLm. At this time, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gray level of the image data Data, and supplies the selected gamma voltage to each of the data lines DL1 to DLm as a video signal do. Here, the period during which the video signal is supplied to the data lines DL1 to DLm increases in every horizontal period according to the tSOE signal. In other words, each horizontal period is gradually increased in accordance with the tSOE signal.

The gate driver 6 outputs a scan pulse in response to a gate control signal GCS from the timing controller 8, for example, a gate start pulse (GSP) and a gate shift clock (GSC) And a pulse width of the scan pulses is controlled in accordance with a transition gate output enable (tGOE) signal input with a pulse width increasing every horizontal period. Then, the scan pulses whose pulse widths are controlled are again supplied with the gate-on voltages sequentially to the gate lines GL1 to GLn. In other words, the period during which the gate-on voltage is applied to each of the gate lines GL1 to GLn gradually increases in every horizontal period according to the tGOE signal. Specifically, the gate driver 6 shifts the GSP from the timing controller 8 according to the GSC to sequentially generate scan pulses. On the basis of the tGOE signal, the pulse widths of the scan pulses are controlled to sequentially supply the gate-on voltages whose pulse widths are controlled to the gate lines GL1 to GLn. At this time, the horizontal period in which each gate-on voltage is output is gradually increased in accordance with the tGOE signal. On the other hand, the gate-off voltage is supplied during the period when no gate-on voltage is supplied to the gate lines GL1 to GLn.

The timing controller 8 arranges image data (RGB) from the outside so as to be suitable for driving the liquid crystal panel 2 and supplies it to the data driver 4. [ Then, by using synchronizing signals (DCLK, DE, Hsync, Vsync) from the outside, the gate period and the scanning period are repeated for every horizontal period in accordance with the video display region of the liquid crystal panel 2, And controls the data driver 4 and the gate driver 6 by generating data control signals GCS and DCS. Specifically, the timing controller 8 generates the tGOE signal and the tSOE signal so that the pulse width gradually increases in units of horizontal periods in addition to the SSP, SSC, GSP, and GSC, and supplies them to the gate and data drivers 4 and 6 . The timing controller 8 will be described in more detail with reference to the accompanying drawings.

2 is a block diagram showing the timing controller of the present invention shown in FIG.

The timing controller 8 shown in FIG. 2 receives image data RGB from the outside of the liquid crystal panel 2 using at least one of synchronization signals DCLK, DE, Hsync, and Vsync input from the outside. And supplies the video signal to the data driver 4 using at least one of the synchronization signals DCLK, DE, Hsync, and Vsync so that the supply period of the video signal gradually increases A data control signal generator 14 for generating a data control signal DCS to be supplied to the data driver 4 so as to increase the data rate of the data to be written to the data driver 4 and using at least one of the synchronization signals DCLK, DE, Hsync, And a gate control signal generator 16 for generating a gate control signal GCS so as to gradually increase the output period of the gate-on voltage and then supplying the gate control signal GCS to the gate driver 4. [

The image processing unit 12 uses at least one of an external synchronizing signal, for example, a dot clock DCLK, a data enable signal DE, and vertical and horizontal synchronizing signals Vsync and Hsync, And arranges the image data (RGB) supplied on a period basis in accordance with the size and resolution of the liquid crystal panel 2 or the like. Then, the image data (Data) is sequentially supplied to the data driver 4 in units of horizontal periods.

The data control signal generator 14 generates a data control signal DCS using at least one of the synchronization signals DCLK, DE, Hsync, and Vsync, for example, SSP, SSC, tSOE, and POL signals , And supplies it to the data driver 4. The data control signal DCS is a signal for controlling the driving timing of the data driver 4. [ Here, the POL signal is a signal for converting the polarity of a video signal supplied to each of the data lines DL1 to DLm. The tSOE signal is a pulse width-converted signal so that the horizontal period is increased every horizontal period, and the supply period of the image signal is increased every horizontal period. Specifically, the pulse width of the tSOE signal is increased by a predetermined width at every horizontal period. At this time, the increased pulse width can be set in advance according to the size and resolution of the liquid crystal panel 2 and the like. The pulse width of the tSOE signal may be increased only during one of the high and low periods. In the present invention, the pulse width of the t SOE signal is increased in the low period.

The gate control signal generator 16 generates a gate control signal GCS, for example, a GSP, a GSC, and a tGOE signal using at least one of the synchronization signals DCLK, DE, Hsync, and Vsync, And supplies it to the gate driver 6. The gate control signal GCS is a signal for controlling the driving timing of the gate driver 6. Here, the tGOE signal is a signal whose pulse width is changed so that the supply period of the gate-on voltage is increased every horizontal period. Specifically, the pulse width of the tGOE signal is increased by a predetermined width at every horizontal period. At this time, the increased pulse width can be set in advance according to the size and resolution of the liquid crystal panel 2 and the like. The pulse width of the tGOE signal may be increased only in one of the high and low sections. In the present invention, the pulse width of the tGOE signal is increased in the low section.

3 is a block diagram showing the data control signal generator and the gate control signal generator shown in FIG.

The data control signal generating unit 14 shown in FIG. 3 generates a counter signal LCS by using at least one of synchronous signals DCLK, DE, Hsync, and Vsync input from the outside, Up table 22 for storing a predetermined horizontal line setting value SSet and outputting a corresponding line-specific setting value SV in accordance with a counter signal LCS input from the line counter 22, Up table 22 and a SOE generator 26 for converting a pulse width according to a set value SV input from the first look-up table 22 to generate a tSOE signal.

The line counter 22 is supplied with a data enable (DE) signal and a horizontal synchronization signal (Hsync) among synchronization signals DCLK, DE, Hsync, and Vsync input from the outside. Then, the counter signal LDC is generated in units of horizontal periods according to the data enable (DE) signal and the horizontal synchronizing signal Hsync and supplied to the first look-up table 24. For example, the line counter 22 generates a counter signal LDC according to a horizontal synchronizing signal Hsync. At this time, one period of the horizontal synchronizing signal Hsync is set to one horizontal period to generate a horizontal synchronizing signal Hsync The counter signal LDC may be generated on a cycle-by-cycle basis. In the present invention, the line counter 22 is provided in the data control signal generating section 14, but the line counter 22 is provided outside the data control signal generating section 14, As shown in FIG.

In the first look-up table 24, the video signal supply period for each horizontal line is preset (SSet) by the user again in accordance with the size and resolution of the liquid crystal panel 2, and the like. The first look-up table 24 sequentially supplies the horizontal line-specific setting values SV to the SOE generating unit 26 when the counter signal LDC is input in units of horizontal periods from the line counter 22 . Here, the set value SV for each horizontal line may be a counter value or a delay value set for the supply period of the video signal. It is preferable that the value SV set in advance by the user is set within a range in which the duration of each frame does not change. In other words, the value SV preset by the user decreases the initial horizontal period to the minimum period in which the image can be displayed, and gradually increases the subsequent horizontal period in a range where the period of one frame does not change .

The SOE generating unit 26 includes a clock generator such as a generator and generates a tSOE signal whose pulse width is converted in accordance with the setting value SV input in the horizontal period unit from the first look- Occurs. Here, the high period of the tSOE signal is generated while being kept constant for the predetermined period, but the low period of the tSOE signal is generated differently according to the setting value SV input every horizontal period unit. In other words, the row period of the tSOE signal may gradually become longer in every horizontal period due to the counter value or the delay value of the supply period of the video signal. The tSOE signal generated so that the pulse width increases every horizontal period is supplied to the data driver 4 to control the output period of the video signal.

The gate control signal generator 16 shown in FIG. 3 stores the preset line-by-line setting value GSet and sets the line-specific setting value GV according to the counter signal LCS input from the line counter 22 Up table 23 and a GOE generator 25 for generating a tGOE signal by converting the pulse width according to the line-specific setting value GV input from the second look-up table 23, .

On the second look-up table 23, the supply period of the gate-on voltage for each horizontal line is preset (GSet) by the user again in accordance with the size and resolution of the liquid crystal panel 2, The second look-up table 23 sequentially supplies the horizontal line-specific setting values GV to the GOE generating unit 25 when the counter signal LDC is input in units of horizontal periods from the line counter 22 . Here, the horizontal line setting value GV may be a counter value or a delay value for which the supply period of the gate-on voltage is set. It is preferable that the value GV preset by the user is set within a range in which the period of each frame does not change. In other words, the value GV preset by the user decreases the initial horizontal period to the minimum period in which the image can be displayed, and gradually increases the subsequent horizontal period in a range in which the period of one frame does not change .

The SOE generating unit 26 includes a clock generator such as a generator and receives the tGOE signal whose pulse width is converted in accordance with the setting value GV input from the second look- Occurs. Here, the high period of the tGOE signal is generated while being kept constant for the predetermined period, but the low period of the tGOE signal is generated differently according to the setting value (GV) input every horizontal period unit. In other words, the row period of the tGOE signal may be gradually lengthened every horizontal period by the counter value or the delay value of the supply period of the gate-on voltage. The tGOE signal generated so that the pulse width increases every horizontal period is supplied to the gate driver 6 to control the output period of the gate-on voltage.

4 is a block diagram showing the gate driver shown in FIG.

The gate driver 6 shown in FIG. 4 includes a shift register 32 for sequentially generating scan pulses in response to GSP and GSC from the gate control signal generator 16, (NOT_G) for inverting and outputting the phase of the tGOE signal, and a tGOE signal having a phase inverted through the NOT gate (NOT_G) to control the width of the scan pulse sequentially input in accordance with the gate- (Vdot1 to Voutn).

Here, the gate driver 6 is a level shifter for shifting the levels of the gate-on voltages Vdot1 to Voutn to a constant level in order to stabilize the level of the gate-on voltages Vdot1 to Voutn sequentially output from the output controller 16. [ On voltages Vdot1 to Voutn to prevent distortion of the gate-on voltages Vdot1 to Voutn from the level shifters in accordance with the RC time constants of the gate lines GL1 to GLn, . The level shifter and the output buffer are provided so as to correspond to the respective gate lines GL1 to GLn.

The shift register 32 includes a plurality of stages ST1 to STn which are connected to each other to shift the GSP inputted from the gate control signal generator 16 according to the GSC and sequentially output scan pulses. Each of the plurality of stages ST1 to STn may be constituted by at least one flip flop F / F and may be constituted by at least one node and a switching circuit composed of NMOS or PMOS transistors. In addition, the shift register 12 may be constituted by a circuit in which at least one logic operation gate (AND_Gate, OR_Gate, XOR_Gate, NOR_Gate) is combined.

The output control unit 34 includes a plurality of stages (ST1 to STn) for controlling the widths of scan pulses sequentially input from the plurality of stages ST1 to STn in accordance with the tGOE signal, which is provided at the output stage of each of the plurality of stages ST1 to STn, And an AND gate (AND_G). Each of the plurality of AND gates AND_G outputs each scan pulse at the gate-on voltages Vdot1 to Voutn during a period in which the tGOE signal is input high. Here, since the high period of the tGOE signal becomes gradually longer for each horizontal period, the output period of the gate-on voltages (Vdot1 to Voutn) also gradually becomes longer for each horizontal period. The plurality of gate-on voltages Vdot1 to Voutn are supplied to the gate lines GL1 to GLm through the level shifter and the output buffer.

On the other hand, the shift register 32 and the output control unit 34 as described above may be provided in the data driver 4. [ In other words, when the shift register 32 and the output control unit 34 are provided in the data driver 4, the shift register 32 and the output control unit 34 input the latched image data Data on a horizontal line basis, And outputs it. At this time, since the low period of the tSOE signal gradually becomes longer for each horizontal period, the output period of the video signal also becomes longer for each horizontal period in accordance with the low period of the tSOE signal.

5 is an input / output waveform diagram of the timing controller, gate, and data driver shown in FIG.

As shown in FIG. 5, the tGOE signal generated from the gate control signal generator 16 is supplied to the gate driver 6 in increments of a pulse width in units of horizontal periods. Specifically, the tGOE signal is generated so that the row period is increased in every horizontal period by the set value GV set in the second look-up table 23. Accordingly, the shortest pulse width can be generated in the first horizontal period (1H), and the pulse width can be gradually increased from the second horizontal period (2H). The tGOE signal is inverted in the NOT gate (NOT_G) of the gate driver 6 and sequentially inverted in the gate-on voltages Vout1 to Voutn so as to be synchronized with the high period of the inverted tGOE signal in the output controller 34 . Likewise, sequentially outputted gate-on voltages Vout1 to Voutn may be supplied to the first gate line GL1 for a shortest period of time, and gradually increase from the second gate line GL2.

On the other hand, the tSOE signal generated from the data control signal generator 14 is supplied to the data driver 4 in increments of a pulse width in units of horizontal periods. Specifically, the tSOE signal is generated so that the low period is increased in every horizontal period by the set value SV set in the first look-up table 24. [ Accordingly, it can be generated with the shortest pulse width in the first horizontal period (1H) and can be generated with the pulse width gradually increasing from the second horizontal period (2H). The tSOE signal is supplied to the data driver 4 together with the SSP and the SSC and the data driver 4 supplies the video signal to the data lines DL1 to DLm so as to be synchronized with the low period of the tSOE signal. Accordingly, the video signal supplied to each of the data lines DL1 to DLm is supplied most shortly in the first horizontal period (1H), but gradually increases from the second horizontal period (2H).

As described above, according to the driving apparatus of the liquid crystal display apparatus and the driving method thereof according to the embodiment of the present invention, the charging period of the image data is gradually increased according to the display region of the image of the liquid crystal panel 2, Rate can be compensated. In other words, in the present invention, in the region close to the timing controller 8 and the gate and data drivers 6 and 4, the periods for displaying the image are shortened, but in the region away from the gate and data drivers 6 and 4, The video display period is gradually increased. Accordingly, the present invention can improve the display quality of an image by preventing a luminance unbalance phenomenon, a flicker, etc. by compensating a charging rate of a video signal according to a display region of a video while maintaining a constant period of one frame.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 is a configuration diagram illustrating a liquid crystal display device according to an embodiment of the present invention;

Fig. 2 is a configuration diagram showing the timing controller of the present invention shown in Fig. 1. Fig.

FIG. 3 is a block diagram showing a data control signal generating unit and a gate control signal generating unit shown in FIG. 2. FIG.

4 is a configuration diagram showing the gate driver shown in FIG.

5 is an input / output waveform diagram of the timing controller, gate, and data driver shown in FIG. 1;

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

2: liquid crystal panel 4: data driver

6: Gate driver 8: Timing controller

12: image processor 14: data control signal generator

16: gate control signal generating unit 22: line counter

23: second look-up table 24: first look-up table

25: GOE generator 26: SOE generator

32: shift register 34: output control section

Claims (10)

A liquid crystal panel formed with a plurality of pixel regions; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; And And a controller for generating a data control signal so that a charging period of a video signal is reduced or increased according to a video display area of the liquid crystal panel, And a timing controller for controlling the data driver and controlling the gate driver by generating a gate control signal so that the charging period of the video signal is reduced or increased, The data control signal generator may include a line counter for generating a counter signal in units of horizontal periods using at least one of synchronous signals input from outside, a first setting value for each horizontal line, A first look-up table for outputting a line-by-line setting value, and an SOE generator for converting a pulse width according to the line-specific setting value to generate a converted SOE signal. The method according to claim 1, The timing controller An image processor for aligning the image data from the outside using the at least one of the synchronization signals so as to be suitable for driving the liquid crystal panel and supplying the image data to the data driver, A data control signal generator for generating the data control signal so as to gradually increase the supply period of the video signal using at least one of the synchronization signals and supplying the data control signal to the data driver, And a gate control signal generator for generating the gate control signal so that the output period of the gate-on voltage is gradually increased by using at least one of the synchronization signals and supplying the gate control signal to the gate driver. Device for driving a device. delete 3. The method of claim 2, The gate control signal generator A second look-up table for storing a preset second set value for each line and outputting a set value for each line according to a counter signal inputted from the line counter, and And a GOE generator for generating a converted GOE signal by converting a pulse width according to a corresponding line-specific setting value input from the second look-up table. 5. The method of claim 4, At least one setting value of the first and second setting values is Is a counter value or a delay value which is set so as to gradually decrease an initial horizontal period (1H) to a minimum period in which an image can be displayed and to gradually increase the subsequent horizontal period within a range in which the period of one frame does not change. A driving device for a display device. A driving method of a liquid crystal display device having a liquid crystal panel for displaying an image, a data driver, a gate driver, and a timing controller, Aligning image data input from the outside in accordance with driving of the liquid crystal panel; And The data driver controls the data driver to generate a data control signal so that the charging period of the video signal is reduced or increased according to the video display area of the liquid crystal panel, And controlling the gate driver, The data control signal generating step may include generating a counter signal in units of horizontal periods using at least one of synchronous signals input from the outside, storing a first set value for each horizontal line, Outputting a line-by-line setting value, and converting the pulse width according to the line-by-line setting value to generate a converted SOE signal and supplying the converted SOE signal to the data driver. The method according to claim 6, The data and gate driver control step Generating the data control signal so that the supply period of the video signal is gradually increased by using at least one of the synchronization signals and supplying the data control signal to the data driver; And generating the gate control signal so that the output period of the gate-on voltage is gradually increased by using at least one of the synchronization signals, and then supplying the gate control signal to the gate driver. Driving method. delete 8. The method of claim 7, The gate control signal generation step Storing a predetermined second line-specific setting value and outputting a line-specific setting value according to the counter signal, and And converting the pulse width according to the line-specific setting value to generate a converted GOE signal to supply the converted GOE signal to the gate driver. 10. The method of claim 9, At least one setting value of the first and second setting values is Is a counter value or a delay value which is set so as to gradually decrease an initial horizontal period (1H) to a minimum period in which an image can be displayed and to gradually increase the subsequent horizontal period within a range in which the period of one frame does not change. A method of driving a display device.

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