KR101421439B1 - Liquid Crystal Display and Driving Method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device including liquid crystal cells including liquid crystal cells in which a plurality of data lines and a plurality of gate lines intersect and are arranged in a matrix form; A data driving circuit for converting the digital video data and the black data into a positive / negative gamma compensation voltage in response to the polarity control signal to supply positive / negative data voltages and positive / negative black gradation voltages to the data lines, in; A gate driving circuit for supplying a gate pulse to the gate lines in response to the gate timing control signal; And a timing controller for generating a data timing control signal including the polarity control signal to control the data driving circuit and generating a gate timing control signal to control the gate driving circuit. Wherein the liquid crystal cells are charged with the black gradation voltage of positive polarity during the (N + 1) th frame period after the black gradation voltage of negative polarity is charged during N (N is an integer) frame period.

Irregular stain, black data

Description

[0001] The present invention relates to a liquid crystal display and a driving method thereof,

The present invention relates to a liquid crystal display device capable of driving in an impulse manner and preventing irregular smear, and a driving method thereof.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is rapidly applied to a television, thereby rapidly replacing a cathode ray tube.

As shown in FIG. 1, a liquid crystal display device uses a thin film transistor (TFT) formed for each liquid crystal cell Clc to switch data voltages supplied to the liquid crystal cells to actively control data, thereby improving the display quality of a moving image . 1, reference numeral "Cst" denotes a storage capacitor (Cst) for holding a data voltage charged in the liquid crystal cell Clc, "DL" denotes a data line to which a data voltage is supplied, and "GL" Quot; refers to a gate line to which a scan voltage is supplied.

In the display image of the liquid crystal display device, irregular unevenness may appear. When a DC voltage of the same polarity is applied to the liquid crystal layer for a long time, impurity ions in the liquid crystal layer are divided according to the polarity of the liquid crystal, and ions of different polarities are accumulated in the pixel electrode and the common electrode in the liquid crystal cell. When a direct current voltage is applied to the liquid crystal layer for a long time, the amount of accumulation of ions is increased, and the orientation film is deteriorated, resulting in deterioration of the alignment property of the liquid crystal. Accordingly, if a direct current voltage is applied to the liquid crystal display for a long time, irregular unevenness occurs. In order to solve the problem of irregular smear, a liquid crystal material having a low dielectric constant is developed and a method of improving orientation materials and orientation methods is being planned. However, such a method requires much time and expense to develop materials, and lowering the dielectric constant of the liquid crystal may cause another problem that the driving characteristic of the liquid crystal is deteriorated. Experimental findings reveal that the point of appearance of the indefinite smear becomes faster as the impurity ionized in the liquid crystal layer is larger and the acceleration factor is larger. The acceleration factor is temperature, time, direct current driving of the liquid crystal, and the like. Accordingly, the irregular smudges appear and become worse as the temperature is high or the DC voltage of the same polarity is applied to the liquid crystal layer. The irregular smudges appear irregularly even among the panels manufactured through the same manufacturing line. Therefore, the driving method for suppressing the direct current driving of the liquid crystal is most effective because it can not be solved only by a new material development or a process improvement method.

In the liquid crystal display device, a blurring phenomenon in which a screen is not clear and blurry appears in a moving image due to the retention characteristics of a liquid crystal. The CRT emits phosphors only for a very short time to display data in the cell, and then displays the image in impulsive driving without light emission in the cell. On the other hand, the liquid crystal display device displays an image in the hold drive in which data charged in the liquid crystal cell is held for the remaining field period (or frame period) after the data is supplied to the liquid crystal cell during the scanning period.

Since the moving picture displayed on the CRT is displayed by impulse driving, the perceived image of the viewer is sharpened. On the other hand, in the liquid crystal display device, the contrast of the perception image felt by the spectator due to the retention characteristic of the liquid crystal in the video is not clear and blurred. The difference of these perceptual images is due to the integration effect of the images which are temporally continuous in the eye following the movement. Therefore, even if the response speed of the liquid crystal display device is fast, the viewer sees a blurred image due to mismatch between the motion of the eyes and the static image of each frame. In order to improve the motion blur phenomenon in such a liquid crystal display device, it is also necessary to apply the impulse driving method to the liquid crystal display device.

Disclosure of Invention Technical Problem [8] The present invention provides a liquid crystal display device and a method of driving the same, which can be driven in an impulse manner and prevent irregular spots.

A liquid crystal display panel including liquid crystal cells in which a plurality of data lines and a plurality of gate lines are crossed and arranged in a matrix form; A data driving circuit for converting the digital video data and the black data into a positive / negative gamma compensation voltage in response to the polarity control signal to supply positive / negative data voltages and positive / negative black gradation voltages to the data lines, in; A gate driving circuit for supplying a gate pulse to the gate lines in response to a gate timing control signal; And a timing controller for generating a data timing control signal including the polarity control signal to control the data driving circuit and generating the gate timing control signal to control the gate driving circuit.

The liquid crystal cells are charged with the black gradation voltage of positive polarity during the (N + 1) th frame period after the black gradation voltage of negative polarity is charged during N (N is an integer) frame period.

Wherein the polarity control signal is generated with low logic for each black data after being latched in the data driving circuit during the Nth frame period, and is generated for each black data after being latched in the data driving circuit during the (N + 1) Logically generated.

The polarity control signal is inverted in units of one horizontal period while the digital video data is being consecutive for the Nth frame period and is maintained in the same low logic for approximately two horizontal periods synchronized with the black data and the preceding digital video data Th frame period during the (N + 1) < th > frame period.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes generating a data timing control signal including a gate timing control signal and a polarity control signal; Converting the digital video data and the black data into a positive / negative gamma compensation voltage in response to the polarity control signal to supply a positive / negative data voltage and a positive / negative black gradation voltage to the data lines ; And supplying gate pulses to the gate lines in response to the gate timing control signal.

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The liquid crystal display device and the driving method thereof according to the embodiment of the present invention charge the black data and impulse drive the black data, modulate the polarity control signal in the black data, and invert the polarity of the black data every frame, It is possible to minimize irregular speckles.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 9. FIG.

Referring to FIG. 8, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13. The data driving circuit 12 includes a plurality of source drive ICs. The gate drive circuit 13 includes a plurality of gate drive ICs 131 to 135.

In the liquid crystal display panel, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes mxn liquid crystal cells Clc arranged in a matrix form by an intersection structure of m data lines 14 and n gate lines 15. [

Data lines 14, gate lines 15, TFTs, and a storage capacitor Cst are formed on a lower glass substrate of a liquid crystal display panel. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The IPS (In Plane Switching) mode and the FFS (Fringe Field Switching) Mode is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel, a polarizing plate orthogonal to the optical axis is attached, and an alignment film is formed to set a pre-tilt angle of the liquid crystal at the interface with the liquid crystal.

The display screen of the liquid crystal display panel is dividedly driven into a plurality of blocks BL1 to BL5 according to a gate timing control signal applied to the gate drive ICs 131 to 135. [ These blocks BL1 to BL5 are sequentially driven in the order of data display, data holding, and black insertion when the black data insertion ratio BDI% is less than 20%. The blocks BL1 to BL5 are sequentially driven in the order of data display, data holding, black insertion and black holding when the black data insertion ratio BDI% is 20% or more.

The timing controller 11 receives timing signals such as vertical / horizontal synchronizing signals Vsync and Hsync, a data enable signal, a dot clock signal DCLK and a fixed clock signal FCLK, 12), and the gate driving circuit (13). These control signals include a gate timing control signal and a data timing control signal. In addition, the timing controller 11 supplies digital video data (RGB) and black data to the data driving circuit 12. One black data is inserted between k (k is an integer of 2 or more) digital video data (RGB) in the data stream transmitted from the timing controller 11 to the data driving circuit 12. [ To this end, the timing controller 11 delays the digital video data (RGB) using a memory and generates "00000000 ", i.e., black data, and inserts the black data into the digital video data.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like.

The gate start pulse GSP is applied to the first gate drive IC 131 to indicate the start line at which the scan starts so that the first gate pulse is generated from the first gate drive IC 131. [ The gate shift clock signal GSC is a clock signal for shifting the gate start pulse GSP. The shift register of the gate drive ICs 131 to 135 shifts the gate start pulse GSP and the gate pulse to the next stage at the rising edge of the gate shift clock signal GSC. The second to fifth gate drive ICs 132 to 135 receive the final stage output of the gate drive IC of the preceding stage as a gate start pulse (GSP) to generate a first gate pulse. The gate output enable signal GOE is applied to the gate drive ICs 131 to 135 individually. The gate drive ICs 131 to 135 output the gate pulse during the low logic period of the gate output enable signal GOE, that is, just after the polling time of the previous pulse, but just before the rising time of the next pulse. During the high logic period of the gate output enable signal GOE, the gate drive ICs 131 to 135 do not generate gate pulses.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP indicates a starting pixel in one horizontal line where data is to be displayed. The source sampling clock SSC indicates the latch operation of data in the data driving circuit 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the analog video data voltage output from the data driving circuit 12. [ The pulses of the polarity control signal POL are synchronized with the digital video data (RGB) and the black data after the latches in the data driving circuit 12. The pulse of the polarity control signal POL synchronized with the black data has the same logical value for one frame period, while the logical value is inverted every frame. The source output enable signal SOE controls the output of the source drive IC.

Each of the data drive ICs of the data driving circuit 12 includes a shift register, a latch, a digital-analog converter, an output buffer, and the like. The data driving circuit 12 latches the digital video data RGB and the black data under the control of the timing controller 11. [ The data driving circuit 12 supplies the charge sharing voltage to the data lines 14 in response to the source output enable signal SOE and outputs the digital video data RGB and the black Data is converted into an analog positive / negative gamma compensation voltage to generate positive / negative analog data voltages and black gradation voltages, and supplies the voltages to the data lines 14. Here, the data driving circuit 12 converts the digital video data (RGB) or black data to the positive gamma compensation voltage during the high logic period of the polarity control signal POL, while the low logic period The digital video data (RGB) or the black data is converted into a negative gamma compensation voltage. The data driving circuit 12 supplies the data voltages to the data lines 14 during the scan time of the blocks BL1 to BL5 driven by the data display block and supplies the data voltages to the data lines 14 of the blocks BL1 to BL5 driven by the black insertion block And supplies black gradation voltages to the data lines 14 during the scan time.

The data driving circuit 12 converts the black data to the gamma compensation voltage of one polarity during the odd frame period in response to the polarity control signal POL and converts the black data to the gamma compensation voltage of the opposite polarity during the odd frame period . Therefore, the present invention minimizes the occurrence of an irregular smudge because DC is suppressed by the black gradation voltage in which all the liquid crystal cells of one screen are polarized in every frame.

Each of the gate drive ICs 131 to 135 includes a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer (not shown) connected between the level shifter and the gate line 15. [ Respectively. The gate drive ICs 131 to 135 sequentially supply gate pulses to the gate lines 15 in response to gate timing control signals. These gate drive ICs 131 to 135 supply the blocks BL1 to BL5 with data of gate start pulse GSP and gate output enable signals GOE1 to GOE5 of the gate timing control signal varying in accordance with the frame frequency A display block, a data holding block, a black insertion block, and a black holding block.

2 is a waveform diagram showing the gate timing control signal shown in FIG. 3 shows a gate timing control signal for controlling the gate drive ICs 131 to 135 serving as data display blocks and a gate timing control signal for controlling the gate drive ICs 131 to 135 responsible for the black display blocks Fig.

Referring to FIGS. 2 and 3, the gate start pulse GSP includes a first pulse P1 for controlling the scanning start time of the block to which the video data voltage is charged, a first pulse P1 for controlling the scanning start time of the block to which the black gradation voltage is charged And a second pulse P2 for controlling the second pulse P2.

The pulse width of the first pulse P1 is approximately one horizontal period, and the pulse width of the second pulse P2 is approximately k horizontal periods. The gate drive ICs 131 to 135 sequentially shift the first pulse P1 in accordance with the gate shift clock GSC. Blocks BL1 to BL5 where scanning is started by the gate drive ICs 131 to 135 starting to operate in response to the first pulse P1 are driven into a data display block. In the blocks BL1 to BL5 driven by the data display block, the gate pulses are sequentially applied to the gate lines one by one.

In addition, the gate drive ICs 131 to 135 sequentially shift the second pulse P2 according to the gate shift clock GSC. The blocks BL1 to BL5 for charging the black gradation voltage by the gate drive ICs 131 to 135 starting to operate in response to the second pulse P2 are driven by the black insertion block. The gate pulses in the blocks BL1 to BL5 driven by the black insertion block are partially overlapped according to the correlation between the second pulse P2 having a wide pulse width and the gate shift clock GSC generated in a period of approximately one horizontal period. For example, in the blocks (BL1 to BL5) driven by the black insertion block, the gate pulse applied to the i-th (i is an integer) gate line and the gate pulse applied to the (i + 1) -th gate line are partially overlapped. N gate pulses successively applied to the data display blocks BL1 to BL5 are sequentially applied to the gate driver ICs 131 to 135 by the gate output enable signals GOE1 to GOE5 individually applied to the gate drive ICs 131 to 135, N gate pulses are simultaneously applied to the insertion blocks BL1 to BL5, and then N gate pulses are sequentially applied to the data display blocks BL1 to BL5. By repeating this operation, the gate drive ICs 131 to 135 serving as data display blocks and the gate drive ICs 131 to 135 serving as black insertion blocks alternately apply gate pulses.

The gate output enable signals GOE1 to GOE5 are sequentially shifted. The gate output enable signals GOE1 to GOE5 include a first section T1 for on / off controlling the output of the gate drive ICs 131 to 135 responsible for the data display block, A second section T2 for shutting off the output of the gate drive ICs 131 to 135 for turning on and off the gate outputs of the gate drive ICs 131 to 135 responsible for the black insertion block And a third section T3.

During the first section T1 of the gate output enable signals GOE1 to GOE5, the timing controller 11 generates pulses of the gate output enable signals GOE1 to GOE5 every rising time of the gate start pulse GSC . During the row logic period between these pulses, the gate tribe ICs 131 to 135 responsible for the data display block generate gate pulses. Therefore, during the first interval T1, the gate drive ICs 131 to 135 responsible for the data display block shift the gate start pulse GSP every rising time of the gate shift clock GSC, Are sequentially applied. The data drive ICs 131 to 135 supply data lines with analog data voltages synchronized with gate pulses applied to the data display block. Thus, the liquid crystal cells of the data display block charge the analog data voltage.

During the second section T2 of the gate output enable signals GOE1 to GOE5, the timing controller 11 generates the gate output enable signals GOE1 to GOE5 with a DC voltage of high logic. Therefore, the gate drive ICs 131 to 135 that are responsible for the data display block do not generate gate pulses. During this second period T2, the data drive ICs output the analog data voltage to be displayed in the other data display block and the black gradation voltage to be charged in the liquid crystal cells of the black display block.

During the third period T3 of the gate output enable signals GOE1 to GOE5, the timing controller 11 applies a gate pulse to each of the gate lines in the data display block while sequentially applying gate pulses to the four gate lines, And generates pulses of the gate output enable signals GOE1 to GOE5 in the drive ICs 131 to 135 with a pulse width of approximately N horizontal periods. In the example of Fig. 3, the pulse widths of the gate output enable signals GOE1 to GOE5 for controlling the outputs of the gate drive ICs 131 to 135 responsible for the black display block are four horizontal periods. As a result, during the third period T3, the gate drive ICs 131 to 135 which are responsible for the black display block do not output gate pulses, and gate pulses are sequentially applied to the gate lines of the data display block during that period do. On the other hand, during this period, the gate drive ICs 131 to 135 which are responsible for the black display block do not output gate pulses, but the shift registers therein provide gate start pulses (GSP) and gate start pulses Shifting to the stage. Following a pulse having a pulse width of four horizontal periods, the timing controller 11 keeps the gate output enable signals GOE1 to GOE5 at a low logic voltage for approximately one horizontal period. At this time, the gate drive ICs 131 to 135 which are responsible for the black display block simultaneously output the gate pulses shifted while being partially overlapped in the internal shift registers to the four lines, and the data drive ICs And simultaneously outputs synchronized black gradation voltages.

4 and 5 are waveform diagrams showing a data timing control signal for controlling the data driving circuit 12 in the odd frame period and the odd frame period and an output waveform of the data driving circuit 12, respectively. Fig. 6 is a waveform diagram showing a polarity control signal divided into an odd frame period and an even frame period. And FIG. 7 is a waveform diagram showing a data voltage and a black gradation voltage charged in one liquid crystal cell during a plurality of frame periods.

4 to 7, the timing controller 11 generates pulses of the source output enable signal SOE at intervals of approximately one horizontal period, and supplies the pulses of the source output enable signal SOE to the source output enable signal SOE in approximately one horizontal period And generates a polarity control signal POL from a later point in time. The data driving circuit 12 latches the digital video data RGB and black data from the timing controller 11 for one horizontal period and then outputs the latched data in response to the polarity control signal POL to the positive polarity / Polarity analog gamma compensation voltage.

The polarity control signal POL is inverted in one horizontal period unit in synchronism with the data voltages during the Nth frame period as shown in Figs. 4 and 6, and is fixed at low logic at the black gradation voltage. 5 and 6, the polarity control signal POL is generated in a state in which the phase is inverted from the Nth frame period during the (N + 1) th frame period, and the logic is controlled in units of one horizontal period in synchronization with the data voltages Inverted and fixed to the high logic at the black gradation voltage. The polarity control signal POL is inverted in approximately one horizontal period while the digital video data is continuous, but has the same logic value for approximately two horizontal periods synchronized with the black data and the preceding digital video data.

In the Nth frame period, the digital video data RGB to be charged in the data display block are supplied to the positive polarity analog gamma compensation voltage and the negative polarity analog gamma compensation voltage so that the polarity thereof is reversed in units of one horizontal period in response to the polarity control signal POL. And the black gradation voltage to be charged in the black display block is converted to the negative analog gamma compensation voltage only in response to the polarity control signal POL. In the (N + 1) th frame period, the digital video data RGB to be charged in the data display block is converted into the analog gamma compensation voltage having the polarity opposite to the polarity of the data voltage charged in the Nth frame period, The black gradation voltage to be charged is converted only to the positive analog gamma compensation voltage in response to the polarity control signal POL. Accordingly, the liquid crystal cells are charged with the negative black gradation voltage after the positive or negative data voltage is charged during the Nth frame period as shown in FIG. 7, and then the positive or negative polarity data voltage is applied during the (N + After charging, the positive black gradation voltage is charged.

As shown in FIGS. 4 to 7, the liquid crystal display according to the embodiment of the present invention charges all the liquid crystal cells with a black gradation voltage whose polarity is inverted in units of one frame period. As a result, the liquid crystal display device of the present invention is driven in an impulse manner, and does not cause motion blurring phenomenon and suppresses direct current drive, resulting in no irregular smearing.

8 shows voltages charged in five blocks BL1 to BL5 that are divided and driven by the gate drive ICs 131 to 135 during the odd frame period.

Referring to FIG. 8, if the screen is divided into five blocks BL1 to BL5 by five gate drive ICs 131 to 135, the blocks BL1 to BL5 are divided into five sub- Divisionally driven in the frame periods SF1 to SF5.

The timing controller 11 supplies the first gate drive IC 131 serving as the first block BL1 simultaneously with the start of the first sub frame period SF1 of the Nth frame period to the first gate drive IC 131 And supplies the pulse P1 and the first section signal T1 of the first gate output enable signal GOE1. At this time, the time difference between the first pulse P1 and the second pulse P2 of the gate start pulse GSP is approximately four subframe periods. The gate start pulse (GSP) generated during the (N-1) th frame period is shifted to the second gate drive IC 132 via the first gate drive IC 131. Thus, simultaneously with the start of the first sub-frame SF1 of the N-th frame period, the second gate drive IC 132 receives the second pulse P2 of the gate start pulse GSP and the second gate output enable signal GOE2 Is supplied with the third interval signal T3.

During the first sub frame period SF1 of the Nth frame period, the first block BL1 is turned on during the first period P1 of the gate start pulse GSP and the first period of the first gate output enable signal GOE And charges the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the gate pulses sequentially generated one line at a time according to the signal T1. The second block BL2 is connected to the gate pulses overlapping N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the second gate output enable signal GOE2 And charges negative black gradation voltages from the data drive ICs. The third block BL3 is turned on in the third sub frame period SF3 of the (N-1) th frame period according to the second interval signal T2 of the third gate output enable signal GOE for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. The fourth block BL4 is turned on in the fourth sub frame period SF4 of the (N-1) th frame period in accordance with the second interval signal T2 of the third gate output enable signal GOE for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. The fifth block BL5 is turned on in the fifth sub frame period SF5 of the (N-1) th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE5 for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. Accordingly, during the first sub frame period SF1, the first, third, and fifth blocks BL1, BL3, BL4, and BL5 are driven by a data display block that charges or holds the positive / And the second block BL2 is driven by a black display block for charging the negative black gradation voltage.

During the second sub frame period (SF2) of the Nth frame period, the first block (BL1) is driven in accordance with the second section signal (T2) of the first gate output enable signal GOE1 And maintains the positive / negative analog data voltage charged in one subframe period SF1. The second block B1 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the second gate output enable signal GOE2, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. The third block B3 includes a third block B3 and a third block B3 which are connected to gate pulses overlapping N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the third gate output enable signal GOE And charges negative black gradation voltages from the data drive ICs. The fourth block BL4 is turned on in the fourth sub frame period SF4 of the (N-1) th frame period in accordance with the second interval signal T2 of the fourth gate output enable signal GOE4 for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. The fifth block BL3 is turned on in the fifth sub frame period SF5 of the (N-1) th frame period in accordance with the second interval signal T2 of the fifth gate output enable signal GOE5 for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. Therefore, during the second sub frame period SF2, the first, second, fourth and fifth blocks BL1, BL2, BL4 and BL5 are driven by a data display block for charging or holding the positive / And the third block BL3 is driven by a black display block for charging the negative black gradation voltage.

During the third sub-frame period SF3 of the N-th frame period, the first block BL1 is turned on in response to the second section signal T2 of the first gate output enable signal GOE1 blocking the output of the gate pulse. And maintains the positive / negative analog data voltage charged in one subframe period SF1. The second block BL2 has a positive polarity / negative polarity which was charged in the second sub frame period SF2 in accordance with the second interval signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block B3 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the third gate output enable signal GOE, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. The fourth block B4 includes a first block B3 and a fourth block B4 which are connected to gate pulses superposed by N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fourth gate output enable signal GOE And charges negative black gradation voltages from the data drive ICs. The fifth block BL5 is turned on in the fifth sub frame period SF5 of the (N-1) th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. Therefore, during the third sub-frame period SF3, the first through third and fifth blocks BL1, BL2, BL3, and BL5 are driven by a data display block for charging or holding the positive / negative polarity data voltage, And the fourth block BL4 is driven by a black display block for charging the negative black gradation voltage.

During the fourth sub frame period SF4 of the N-th frame period, the first block BL1 is turned off according to the second interval signal T2 of the first gate output enable signal GOE1, And maintains the positive / negative analog data voltage charged in one subframe period SF1. The second block BL2 has a positive polarity / negative polarity which was charged in the second sub frame period SF2 in accordance with the second interval signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block BL3 has a positive polarity / negative polarity which was charged in the third sub frame period SF3 in accordance with the second interval signal T2 of the third gate output enable signal GOE that blocks the output of the gate pulse. Maintain analog data voltage. The fourth block B4 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the fourth gate output enable signal GOE4, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. The fifth block B5 is connected to gate pulses overlapping N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fifth gate output enable signal GOE5 And charges negative black gradation voltages from the data drive ICs. Therefore, during the fourth sub frame period SF4, the first through fourth blocks BL1 through BL4 are driven by a data display block which charges or holds the positive / negative polarity data voltage, and the fifth block BL5 is driven by the data display block And driven by a black display block for charging the polarity black gradation voltage.

During the fifth sub-frame period SF5 of the N-th frame period, the first block BL1 is turned on during the third period of the second pulse P2 of the gate start pulse GSP and the first gate output enable signal GOE1 And charges negative black gradation voltages from the data drive ICs while being scanned by gate pulses superimposed N lines in accordance with the signal T3. The second block BL2 has a positive polarity / negative polarity (negative polarity) charge in the second sub frame period SF2 in accordance with the second interval signal T2 of the second gate output enable signal GOE for interrupting the output of the gate pulse Maintain analog data voltage. The third block BL3 has a positive polarity / negative polarity which was charged in the third sub frame period SF3 in accordance with the second interval signal T2 of the third gate output enable signal GOE that blocks the output of the gate pulse. Maintain analog data voltage. The fourth block BL3 has a positive polarity / negative polarity which was charged in the fourth sub frame period SF4 in accordance with the second interval signal T2 of the fourth gate output enable signal GOE for interrupting the output of the gate pulse. Maintain analog data voltage. The fifth block B5 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the fifth gate output enable signal GOE5, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. Therefore, during the fifth sub-frame period SF5, the second through fifth blocks BL2 through BL5 are driven by a data display block which charges or holds the positive / negative polarity data voltage, And driven by a black display block for charging the polarity black gradation voltage.

During the (N + 1) -th frame period, all the liquid crystal cells of the liquid crystal display device are charged with the data voltage of the polarity opposite to the data voltage charged in the Nth frame period, and then charged into the positive polarity black gradation voltage.

9 shows voltages charged in five blocks BL1 to BL5 that are divided and driven by the gate drive ICs 131 to 135 during the even frame period.

Referring to FIG. 9, during the first sub frame period SF1 of the (N + 1) th frame period, the first block BL1 is supplied with the first pulse P1 of the gate start pulse GSP and the first gate output enable And charges the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the gate pulses sequentially generated one line at a time according to the first interval signal T1 of the signal GOE. The second block BL2 is connected to the gate pulses overlapping N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the second gate output enable signal GOE2 And charges the positive polarity black gradation voltage from the data drive ICs. The third block BL3 is turned on in the third sub frame period SF3 of the (N-1) th frame period according to the second interval signal T2 of the third gate output enable signal GOE for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. The fourth block BL4 is turned on in the fourth sub frame period SF4 of the (N-1) th frame period in accordance with the second interval signal T2 of the third gate output enable signal GOE for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. The fifth block BL5 is turned on in the fifth sub frame period SF5 of the (N-1) th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE5 for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. Accordingly, during the first sub frame period SF1, the first, third, and fifth blocks BL1, BL3, BL4, and BL5 are driven by a data display block that charges or holds the positive / 2 block BL2 is driven by a black display block for charging the positive black gradation voltage.

During the second sub frame period SF2 of the (N + 1) -th frame period, the first block BL1 is connected to the second section signal T2 of the first gate output enable signal GOE1, And holds the positive / negative analog data voltage charged in the first sub frame period SF1. The second block B1 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the second gate output enable signal GOE2, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. The third block B3 includes a third block B3 and a third block B3 which are connected to gate pulses overlapping N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the third gate output enable signal GOE To charge the positive polarity black gradation voltage from the data driver ICs. The fourth block BL4 is turned on in the fourth sub frame period SF4 of the (N-1) th frame period in accordance with the second interval signal T2 of the fourth gate output enable signal GOE4 for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. The fifth block BL3 is turned on in the fifth sub frame period SF5 of the (N-1) th frame period in accordance with the second interval signal T2 of the fifth gate output enable signal GOE5 for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. Therefore, during the second sub frame period SF2, the first, second, fourth and fifth blocks BL1, BL2, BL4 and BL5 are driven by a data display block for charging or holding the positive / And the third block BL3 is driven by a black display block for charging the positive polarity black gradation voltage.

During the third sub frame period SF3 of the (N + 1) -th frame period, the first block BL1 is connected to the second section signal T2 of the first gate output enable signal GOE1 for interrupting the output of the gate pulse And holds the positive / negative analog data voltage charged in the first sub frame period SF1. The second block BL2 has a positive polarity / negative polarity which was charged in the second sub frame period SF2 in accordance with the second interval signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block B3 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the third gate output enable signal GOE, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. The fourth block B4 includes gate pulses P3 and P4 which are overlapped by N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fourth gate output enable signal GOE, And charges the positive polarity black gradation voltage from the data drive ICs. The fifth block BL5 is turned on in the fifth sub frame period SF5 of the (N-1) th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE for interrupting the output of the gate pulse Maintains the charged positive / negative analog data voltage. Therefore, during the third sub-frame period SF3, the first through third and fifth blocks BL1, BL2, BL3, and BL5 are driven by a data display block for charging or holding the positive / negative polarity data voltage, 4 block BL4 is driven by a black display block for charging the positive black gradation voltage.

During the fourth sub frame period SF4 of the (N + 1) th frame period, the first block BL1 is connected to the second section signal T2 of the first gate output enable signal GOE1 for interrupting the output of the gate pulse And holds the positive / negative analog data voltage charged in the first sub frame period SF1. The second block BL2 has a positive polarity / negative polarity which was charged in the second sub frame period SF2 in accordance with the second interval signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block BL3 has a positive polarity / negative polarity which was charged in the third sub frame period SF3 in accordance with the second interval signal T2 of the third gate output enable signal GOE that blocks the output of the gate pulse. Maintain analog data voltage. The fourth block B4 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the fourth gate output enable signal GOE4, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. The fifth block B5 is connected to gate pulses overlapping N lines in accordance with the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fifth gate output enable signal GOE5 And charges the positive polarity black gradation voltage from the data drive ICs. Therefore, during the fourth sub frame period SF4, the first to fourth blocks BL1 to BL4 are driven to the data display block for charging or holding the positive / negative polarity data voltage, and the fifth block BL5 is driven And driven by a black display block for charging the polarity black gradation voltage.

During the fifth sub frame period SF5 of the (N + 1) -th frame period, the first block BL1 outputs the second pulse P2 of the gate start pulse GSP and the first gate output enable signal GOE1 The positive polarity black gradation voltages from the data drive ICs are charged while being scanned by the gate pulses superposed by N lines in accordance with the three-interval signal T3. The second block BL2 has a positive polarity / negative polarity (negative polarity) charge in the second sub frame period SF2 in accordance with the second interval signal T2 of the second gate output enable signal GOE for interrupting the output of the gate pulse Maintain analog data voltage. The third block BL3 has a positive polarity / negative polarity which was charged in the third sub frame period SF3 in accordance with the second interval signal T2 of the third gate output enable signal GOE that blocks the output of the gate pulse. Maintain analog data voltage. The fourth block BL3 has a positive polarity / negative polarity which was charged in the fourth sub frame period SF4 in accordance with the second interval signal T2 of the fourth gate output enable signal GOE for interrupting the output of the gate pulse. Maintain analog data voltage. The fifth block B5 includes a first pulse P1 of the gate start pulse GSP and a first pulse signal T1 of the fifth gate output enable signal GOE5, To charge the positive / negative polarity analog data voltages from the data drive ICs while being scanned by the data driver ICs. Therefore, during the fifth sub-frame period SF5, the second through fifth blocks BL2 through BL5 are driven by a data display block for charging or holding the positive / negative polarity data voltage, And driven by a black display block for charging the polarity black gradation voltage.

The liquid crystal display device and the driving method thereof according to another embodiment of the present invention are designed to drive the liquid crystal cells in a vertical 2 dot-inversion manner, And generates a polarity control signal with the same logic value for approximately three horizontal periods synchronized with the black data and the two digital video data preceding the black data.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention;

Fig. 2 is a waveform diagram showing the gate timing control signal shown in Fig. 1; Fig.

Fig. 3 is a waveform diagram showing in detail the gate timing control signal shown in Fig. 8 in the data display block and the black display block; Fig.

Figs. 4 and 5 are waveform diagrams showing the data timing control signal for controlling the data driving circuit 12 in the odd frame period and the even frame period, and the output waveforms of the data driving circuit. Fig.

6 is a waveform diagram showing a polarity control signal divided into an odd frame period and an excellent frame period;

7 is a waveform diagram showing a data voltage and a black gradation voltage charged in one liquid crystal cell during a plurality of frame periods.

FIGS. 8 and 9 are diagrams illustrating voltages charged in liquid crystal cells for each block in an odd frame period and an even frame period; FIG.

Description of the Related Art

11: timing controller 12: data driving circuit

13: Gate drive circuit

Claims (6)

A liquid crystal display panel including liquid crystal cells in which a plurality of data lines and a plurality of gate lines intersect and are arranged in a matrix form; A data driving circuit for converting the digital video data and the black data into a positive / negative gamma compensation voltage in response to the polarity control signal to supply positive / negative data voltages and positive / negative black gradation voltages to the data lines, in; A gate driving circuit for supplying a gate pulse to the gate lines in response to a gate timing control signal; And And a timing controller for generating a data timing control signal including the polarity control signal to control the data driving circuit and generating the gate timing control signal to control the gate driving circuit, Wherein the liquid crystal cells are charged with the black gradation voltage of negative polarity for the (N + 1) th frame period after filling the black gradation voltage of negative polarity for N (N is an integer) frame period. The method according to claim 1, The polarity control signal, Logic low for each block data latched in the data driving circuit during the N-th frame period, And is generated with high logic for every black data latched in the data driving circuit during the (N + 1) -th frame period. 3. The method of claim 2, The polarity control signal, During the N-th frame period, the digital video data is inverted in units of one horizontal period while being maintained in the same row logic for two horizontal periods synchronized with the black data and the preceding digital video data, Th frame period during the N + 1 < th > frame period. Claim 4 has been abandoned due to the setting registration fee. 1. A method of driving a liquid crystal display (LCD) device including a liquid crystal display panel including liquid crystal cells arranged in a matrix, wherein a plurality of data lines and a plurality of gate lines cross each other, Generating a data timing control signal including a gate timing control signal and a polarity control signal; Converting the digital video data and the black data into a positive / negative gamma compensation voltage in response to the polarity control signal to supply a positive / negative data voltage and a positive / negative black gradation voltage to the data lines ; And And supplying gate pulses to the gate lines in response to the gate timing control signal, Wherein the liquid crystal cells are charged with the black gradation voltage of negative polarity during the Nth (N is an integer) frame period, and then the black gradation voltage of positive polarity is charged during the (N + 1) Driving method. Claim 5 has been abandoned due to the setting registration fee. 5. The method of claim 4, The polarity control signal, Logic low for every black data latched in the data driving circuit during the N-th frame period, And the gray data is generated with high logic for every black data latched in the data driving circuit during the (N + 1) th frame period. Claim 6 has been abandoned due to the setting registration fee. 6. The method of claim 5, The polarity control signal, During the N-th frame period, the digital video data is inverted in units of one horizontal period while being maintained in the same row logic for two horizontal periods synchronized with the black data and the preceding digital video data, Th frame period during the N + 1 < th > frame period. ≪ IMAGE >

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