KR101402697B1 - Independent and symmetric double gated electron-hole bilayer tunnel field effect transistor and its fabrication method - Google Patents
Independent and symmetric double gated electron-hole bilayer tunnel field effect transistor and its fabrication method Download PDFInfo
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- KR101402697B1 KR101402697B1 KR1020120143844A KR20120143844A KR101402697B1 KR 101402697 B1 KR101402697 B1 KR 101402697B1 KR 1020120143844 A KR1020120143844 A KR 1020120143844A KR 20120143844 A KR20120143844 A KR 20120143844A KR 101402697 B1 KR101402697 B1 KR 101402697B1
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- effect transistor
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- 230000005669 field effect Effects 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 7
- 229910052787 antimony Inorganic materials 0.000 claims description 6
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052797 bismuth Inorganic materials 0.000 claims description 6
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- -1 Si 3 N 4 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910008310 Si—Ge Inorganic materials 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 1
- 230000005641 tunneling Effects 0.000 abstract description 11
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66931—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a tunnel field effect transistor having an independent and symmetrical double gate structure and a method of manufacturing the same. More particularly, the present invention relates to a method of forming a tunnel effect transistor by forming a double layer of an electron layer and a hole layer in one channel by applying voltages having different polarities to two independent and symmetrical double gates respectively.
With the development of photolithography technology, the semiconductor industry has been doubling the chip density every 24 months as a way to reduce channel length in accordance with Moore's Law. However, the increased integration and faster operation speed of these chips are not suitable for mobile applications where low power semiconductor devices should be applied. A low-power device refers to maintaining a subthreshold slope below a threshold voltage at a low operating voltage.
As one of the alternative methods, a tunnel field effect transistor using interband tunneling is being studied. A tunnel field effect transistor is a device that drives a device using tunneling at a junction between a source and a channel, unlike a conventional MOSFET using a drift-diffusion method. In a tunnel field effect transistor, a steep subthreshold slope may be less than a threshold voltage of 60 mv / dec compared to a conventional MOSFET having a threshold value (60 mV / dec) to improve the subthreshold slope.
A typical tunnel field-effect transistor structure has a p-i-n junction in which impurities are implanted into a source (p +), a channel (intrinsic), and a drain (n +). The device operates by applying a reverse voltage across the diode and tunneling the electrons from the valance band to the conduction band.
However, unlike conventional classical phenomena that receive energy above the energy barrier and cross the barrier, tunneling is the principle that a part of the carrier passes through the energy barrier. Therefore, the tunnel field effect transistor It has a fatal disadvantage. Therefore, it is essential to study the tunnel field effect transistor in order to actually use it.
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of solving realistic manufacturing process unavailability for an existing electron-hole double-layer field effect transistor. Although the previously disclosed electron-hole double-layer tunnel field effect transistor has an asymmetric structure of the double gate and the channel, it is impossible to fabricate an actual device. However, the present invention is not limited to the above- To provide a manufacturing process.
It is still another object of the present invention to provide a semiconductor device capable of improving the subthreshold slope and significantly increasing the operation current by increasing the surface area at which tunneling occurs compared to a conventional tunnel effect transistor .
In order to achieve the above object, a semiconductor device according to the present invention is characterized in that, in a pin structure having independent and symmetrical double gates based on a fin field effect transistor (FinFET) structure, in order to form a double layer in a channel region, And have the same polarity and different polarities.
The semiconductor device according to the present invention has two gates made of the same material, and the gate and the channel have a symmetrical structure, thereby realizing the actual manufacturing process realization.
Also, if tunneling occurs in a horizontal direction to the gate at the junction of the source and the channel in the conventional tunneling field transistor, the semiconductor device according to the present invention applies only the gate voltage in the intrinsic region, By making tunneling occur, the total surface area at which tunneling occurs can be increased. This can improve the subthreshold slope to a value close to 0 mV / dec and increase the magnitude of the operating current.
In addition, since tunneling may occur in both the vertical and horizontal directions with respect to the gate, vertical or horizontal silicon pillars may be formed on the silicon substrate depending on the application, thereby effectively improving the degree of integration.
FIG. 1 is a flowchart illustrating a method of manufacturing an electron-hole double-layered field effect transistor using an independent and symmetrical double gate structure according to the present invention.
2 is a view showing a process of forming a fin pattern and depositing a gate oxide.
3 is a view showing a process of depositing a gate electrode.
4 is a view showing a process of implanting impurities into a source region and a drain region.
FIG. 5 is a configuration diagram of an electron-hole double-layer tunnel field effect transistor using an independent and symmetric double gate structure according to the present invention.
6 is a graph simulated using a TCAD tool sentaurus of Synopsys, a semiconductor device simulation tool.
7 is a graph simulated using a TCAD tool sentaurus of Synopsys, a semiconductor device simulation tool.
An electron-hole double-layer field effect transistor using a symmetrical double gate structure, a method of manufacturing the transistor, and a driving method according to the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a flowchart illustrating a method of manufacturing an electron-hole double-layered field effect transistor using a symmetrical double gate structure according to the present invention. The fabrication method includes the steps of preparing the
At this time, the
2 illustrates a process of forming a silicon fin and depositing a
FIG. 3 is a view illustrating a process of depositing a
After the
4 illustrates a process of implanting impurities into the
When the
FIG. 5 illustrates a structure of an electron-hole double-layer tunnel field effect transistor using a symmetrical double gate structure according to the present invention. The
The
The
The P-type impurity is doped into the
In the method of driving a transistor, voltages of different polarities are applied to the
6 and 7 are graphs simulated using TCAD tool sentaurus of Synopsys, a semiconductor device simulation tool. It can be confirmed as shown in FIG. 6 that the electron-major bilayer is formed according to the gate voltage with the device proposed in the present invention. When the off state and the on state according to the voltage condition are compared, it can be seen that electrons and holes are separated and two layers are generated.
7, the drain current according to the gate voltage of the device proposed in the present invention can be confirmed. It can be seen that the subthreshold slope below the threshold voltage is improved to close to 0 mV / dec and the ratio between the on current and the off current is 10 9 times or more.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it should be understood that various changes and modifications will be apparent to those skilled in the art. Obviously, the invention is not limited to the embodiments described above. Accordingly, the scope of protection of the present invention should be construed according to the following claims, and all technical ideas which fall within the scope of equivalence by alteration, substitution, substitution, Range. In addition, it should be clarified that some configurations of the drawings are intended to explain the configuration more clearly and are provided in an exaggerated or reduced size than the actual configuration.
100: substrate 110: lower oxide (layer)
200: Si layer 210: Silicon fin (Si-fin)
220: source region 230: drain region
240: gate oxide (layer) 241: first gate oxide
242: second gate oxide 300: gate electrode
310: first gate electrode 320: second gate electrode
Claims (18)
(i) preparing a substrate;
(ii) depositing a lower oxide layer;
(iii) depositing a Si layer;
(iv) forming a silicon pin (Si-fin) protruding upward using a photolithography process;
(v) oxidizing the surface of the silicon fin to form a gate oxide layer;
(vi) depositing a gate electrode in the gate region of the Si-fin;
(vii) removing a gate oxide layer at a portion where a source region and a drain region are formed in the silicon fin (Si-fin);
(viii) implanting a P-type impurity into the source region using a source mask;
(ix) implanting an N-type impurity into the drain region using a drain mask;
removing a gate electrode and a gate oxide layer formed on the silicon fin by a horizontal cross-section on the substrate so that a (x) double gate is formed;
Wherein the electron-hole double-layer tunnel field effect transistor is fabricated using a symmetric double gate structure.
Wherein the substrate of step (i) is formed of any one of a Si substrate, a Si-Ge substrate, and a III-V compound semiconductor substrate
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
The gate oxide layer in the step (v)
SiO 2, Si 3 N 4, Al 2 O 3, HfO 2 and ZrO 2 And at least one of < RTI ID = 0.0 >
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
In the step (vi), the material of the gate electrode may include at least one of polysilicon or metal material doped with impurities
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
Wherein the metal material is at least one of molybdenum (Mo), nickel (Ni), platinum (Pt), ruthenium oxide (RuO2), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum And wherein the step
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
Characterized in that the impurity comprises at least one of arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb)
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
The removal of the gate oxide layer in the step (vii) is performed by wet etching using HF
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
The P-type impurity in the step (viii) includes at least one of aluminum (Al), boron (B), indium (In), and gallium (Ga)
The dose is 1 x 10 18 atom / cm 3 ~ 5X10 20 atom / cm < 3 >
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
The n-type impurity in the step (ix) includes at least one of arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb)
The dose is 1 x 10 18 atom / cm 3 To 5X10 < 20 > atoms / cm < 3 >
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
The removal of the gate electrode and the gate oxide layer in the step (x) includes a chemical mechanical polishing (CMP) process.
Method for fabricating electron - hole double - layer field effect transistor using symmetric double gate structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120143844A KR101402697B1 (en) | 2012-12-11 | 2012-12-11 | Independent and symmetric double gated electron-hole bilayer tunnel field effect transistor and its fabrication method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120143844A KR101402697B1 (en) | 2012-12-11 | 2012-12-11 | Independent and symmetric double gated electron-hole bilayer tunnel field effect transistor and its fabrication method |
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| Publication Number | Publication Date |
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| KR101402697B1 true KR101402697B1 (en) | 2014-06-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020120143844A KR101402697B1 (en) | 2012-12-11 | 2012-12-11 | Independent and symmetric double gated electron-hole bilayer tunnel field effect transistor and its fabrication method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101827811B1 (en) * | 2016-08-31 | 2018-02-12 | 서강대학교 산학협력단 | Tunnel field-effect transistors and fabrication methods of the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040012900A (en) * | 2001-06-21 | 2004-02-11 | 인터내셔널 비지네스 머신즈 코포레이션 | Double gated transistor and method of fabrication |
| KR100605108B1 (en) | 2004-03-23 | 2006-07-28 | 삼성전자주식회사 | FinFET AND METHOD OF FABRICATING THE SAME |
| KR100773009B1 (en) * | 2003-07-21 | 2007-11-05 | 인터내셔널 비지네스 머신즈 코포레이션 | Fet channel having a strained lattice structure along multiple surfaces |
-
2012
- 2012-12-11 KR KR1020120143844A patent/KR101402697B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040012900A (en) * | 2001-06-21 | 2004-02-11 | 인터내셔널 비지네스 머신즈 코포레이션 | Double gated transistor and method of fabrication |
| KR100773009B1 (en) * | 2003-07-21 | 2007-11-05 | 인터내셔널 비지네스 머신즈 코포레이션 | Fet channel having a strained lattice structure along multiple surfaces |
| KR100605108B1 (en) | 2004-03-23 | 2006-07-28 | 삼성전자주식회사 | FinFET AND METHOD OF FABRICATING THE SAME |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101827811B1 (en) * | 2016-08-31 | 2018-02-12 | 서강대학교 산학협력단 | Tunnel field-effect transistors and fabrication methods of the same |
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