KR101386115B1 - fabrication method of SiC UMOSFET with low resistance gate electrode - Google Patents

Abstract

A method of manufacturing a silicon carbide (SiC) UMOSFET using a trench gate structure, the method comprising: forming a SiC wafer with a screen oxide film and a trench etch resistant hard mask layer ; A second step of defining a region where the trench is to be formed as a photoresist, etching the SiC wafer to form a trench, and then forming a gate insulating film on the inner wall surface of the trench; A third step of successively depositing a polysilicon and a metal film so that the material is filled in the trench; A fourth step of polishing and removing the metal film and the polysilicon by chemical mechanical polishing (CMP) to planarize the metal film and the polysilicon; A source contact is formed on the front surface of the SiC wafer and a drain electrode is formed on the back surface of the wafer and heat treatment is performed to form an ohmic contact to the source contact and drain electrodes while simultaneously causing a reaction between the polysilicon and the metal in the trench, 5 steps; A sixth step of forming a source-gate insulating film on the trench; And a seventh step of forming a source electrode by depositing a metal film on the front surface of the SiC wafer so as to be electrically insulated from the gate electrode by the source-gate insulating film, thereby forming a SiC UMOSFET having a low gate resistance The method is a technical point. Thus, polysilicon and a metal film are sequentially stacked in the trench of the SiC UMOSFET and heat-treated to form a silicide between the interface of the polysilicon and the metal film, thereby forming the silicide and the metal film as a part of the gate electrode, . In addition, the present invention proposes a simplified manufacturing method for forming the gate structure. Specifically, an etching-resistant hard mask for trench etching is used as a CMP stop layer when a gate insulating film growth process and a chemical mechanical polishing (CMP) process of a polysilicon / metal film are performed on a trench, The process has advantages such as trench etching, gate oxide growth, and CMP process of polysilicon / metal layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a SiC UMOSFET having a low gate resistance,

The present invention relates to a method of manufacturing a SiC UMOSFET having a low gate resistance and more particularly to a method of forming a silicide between a polysilicon and a metal film by sequentially laminating a polysilicon and a metal film in a trench of a SiC UMOSFET, A SiC UMOSFET fabrication method having a low gate resistance in which a gate resistance is reduced by forming a silicide and a metal film as a part of a gate electrode.

In general, a power source is a semiconductor device that performs power conversion or control, and a rectifier diode, a power transistor, and a triac are widely used in various fields such as industry, information, communication, traffic, power, and home. In recent years, metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) and power integrated circuits (ICs) have become the center of power devices. In particular, trench type gates A U-shaped metal oxide semiconductor field effect transistor (MOSFET) is specifically referred to as a 'UMOSFET'.

Among these MOS devices, particularly, MOS devices capable of high-speed switching and low loss of driving circuits are attracting attention. Among the MOS devices, the UMOSFETs using trench technology can easily control large power by connecting a plurality of them in parallel Therefore, the unit power UMOSFETs are mainly connected in parallel in order to increase the operating speed of the device while allowing the large power to flow.

Among these UMOSFET devices, there is a SiC UMOSFET device in the prior art. In the SiC UMOSFET device, a channel is formed in a sidewall of a trench. For this purpose, a gate insulating film is formed on the sidewall of the trench, An electrode is formed.

The SiC UMOSFET according to the prior art is filled with polysilicon doped at a high concentration into the trench and utilized as an electrode material.

That is, in the SiC UMOSFET according to the related art, generally, as shown in FIG. 1, a trench 60 is formed on a SiC substrate, a gate insulating film 61 is formed on a wall surface of the trench, Thereby forming a gate electrode.

Trench 60 is the "Process technology for silicon carbide devices" (Published by INSPEC, 2002 London) in chapter 4 "Wet and dry etching of SiC" published in 2002: As outlined in the (By SJ Pearton), CF ₄ , A raw material gas containing fluorine ions such as CHF ₃ , SF ₆ and NF ₃ or a raw material gas containing chlorine ions such as Cl ₂ or a raw material gas containing halogen elements such as ICl and IBr Is generally formed by a plasma etching technique.

After the etching of the trench 60 is completed, a gate insulating film 61 is formed on the sidewalls and bottom surfaces of the trench. Generally, in the silicon UMOSFET, SiO ₂ is grown by an oxidation process. In the case of a SiC UMOSFET, Utilize a SiO ₂ deposition process. Or silicon oxynitride, Si ₃ N ₄ Or the like may be formed in the trench by a vapor deposition process.

For more information on the gate insulating film formation process, refer to chapter 5 "Thermally grown and deposited dielectrics on SiC" of "Process technology for silicon carbide devices" (Published by INSPEC, 2002 London) E. Sveinbjand C.-M. Zetterling.

After the formation of the gate insulating film 61, a gate electrode is formed. In the silicon process, a process using a heavily doped polysilicon 62 as a gate material is well established. The SiC UMOSFET fabrication process is also similar to the silicon process Borrow.

Polysilicon for use as a gate electrode is typically deposited by a low-pressure chemical vapor deposition (LPCVD) process at a temperature in the range of 500 ° C to 700 ° C. During or during the deposition process, boron (B), phosphorus (P), and arsenic (As) are doped at a high concentration of 1 x 10 ²⁰ / cm ³ or more to have the maximum electrical conductivity.

Although the undoped polysilicon has a high resistivity of almost insulator level, for example, polysilicon doped with phosphorus (P) at a concentration of 1 x 10 ²¹ / cm ³ has a relatively low specific resistance of about 400 μΩ · cm It can be used as an electrode sufficiently. Also, since the low pressure chemical vapor deposition method is an excellent deposition method with a step coverage, there is little possibility of problems such as void formation even when the trench 60 is deposited.

After the deposition of the polysilicon 62 for forming the gate electrode, a photolithography process and an etching process are performed to confine the polysilicon to the inside of the trench 60 or nearby, thereby completing the trench gate structure finally.

As described above, in the conventional Si UMOSFET and SiC UMOSFET, the polysilicon deposition is almost exclusively used to form the gate electrode in the trench. However, even with highly doped polysilicon, the lowest resistivity is about 400 μΩ · cm, which is approximately 10 to 100 times higher than the resistivity of metals commonly used in semiconductor processing (Al: 2.7 μΩ · cm, Cu: 1.67 占 占 cm m, Ti: 55.6 占 占 cm m, Ni: 6.9 占 占 · m, etc.).

In addition, as in the case of a memory semiconductor or a logic semiconductor, the area of a chip of the power semiconductor is also continuously decreasing. Accordingly, the width of the trench 60 is gradually reduced. In this case, the resistance of the polysilicon gate line inevitably increases, which adversely affects the operation characteristics of the UMOSFET device.

That is, when the resistance of the gate line increases, the current density that can be maximally flowed due to the power loss and the heat generation due to the decrease is decreased. As the gate current decreases, the switching speed of the UMOSFET decreases. However, in the future, when the strategy of reducing the area of the chip is adopted in order to maximize the performance of the SiC UMOSFET device, the resistance of the gate line Are expected to become important.

Therefore, a SiC UMOSFET device is required which can improve the switching speed of the device and alleviate heat generation at the gate electrode.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which comprises: forming a silicide between an interface of polysilicon and a metal film by sequentially depositing polysilicon and a metal film in a trench of SiC UMOSFET, It is an object of the present invention to provide a SiC UMOSFET fabrication method having a low gate resistance in which a gate resistance is reduced by forming a silicide and a metal film as a part of a gate electrode.

According to an aspect of the present invention, there is provided a method of manufacturing a silicon carbide (SiC) UMOSFET using a trench gate structure, the method comprising: a first step of forming a screen oxide film and a trench etch-resistant hard mask layer on a SiC wafer; A second step of defining a region where the trench is to be formed as a photoresist, etching the SiC wafer to form a trench, and then forming a gate insulating film on the inner wall surface of the trench; A third step of successively depositing a polysilicon and a metal film so that the material is filled in the trench; A fourth step of polishing and removing the metal film and the polysilicon by chemical mechanical polishing (CMP) to planarize the metal film and the polysilicon; A source contact is formed on the front surface of the SiC wafer and a drain electrode is formed on the back surface of the wafer and heat treatment is performed to form an ohmic contact to the source contact and drain electrodes while simultaneously causing a reaction between the polysilicon and the metal in the trench, 5 steps; A sixth step of forming a source-gate insulating film on the trench; And a seventh step of forming a source electrode by depositing a metal film on the front surface of the SiC wafer so as to be electrically insulated from the gate electrode by the source-gate insulating film, thereby forming a SiC UMOSFET having a low gate resistance The method is a technical point.

It is preferable to use silicon nitride as the trench etch-resistant hard mask layer.

The trench etch-resistant hard mask layer formed in the first step may be used as a CMP stopping layer in the CMP process of the fourth step.

The trench etch preventing hard mask formed in the first step protects the remaining portion except for the inner wall surface of the trench in the gate insulating film forming process of the second stage so that finally the gate insulating film remains in the final device structure except the inner wall surface of the trench It is preferable not to include it.

The gate insulating layer is preferably a silicon dioxide layer formed by an oxidation process.

It is preferable that the gate insulating film is a silicon oxide film formed by a deposition process.

It is preferable that the metal film formed in the third step is any one of Ni, Ti, W, Co, Ta and Pt.

The screen oxide layer and the trench etch-resistant hardmask layer formed in the first step are preferably included in the final device structure.

Thus, polysilicon and a metal film are sequentially stacked in the trench of the SiC UMOSFET and heat-treated to form a silicide between the interface of the polysilicon and the metal film, thereby forming the silicide and the metal film as a part of the gate electrode, .

According to the present invention, the polysilicon and the metal film are sequentially stacked in the trench of the SiC UMOSFET and heat-treated to form a silicide between the interface of the polysilicon and the metal film, thereby forming the silicide and the metal film as a part of the gate electrode The gate resistance can be greatly reduced, thereby increasing the current density that can flow through the gate electrode, thereby increasing the switching speed of the SiC UMOSFET and also relieving the heat generation problem due to the high resistance.

FIG. 1 is a cross-sectional view briefly showing the structure of a conventional SiC UMOSFET, showing a shape in which a polysilicon gate electrode is formed in a trench,
FIG. 2 is a view showing a shape in which a gate electrode is formed of polysilicon, a silicide layer, and a metal layer in a trench according to the present invention,
FIG. 3 is a view illustrating a state where a region where a trench is to be etched by a photoresist is etched to etch the trench on a SiC wafer,
FIG. 4 is a view showing a state where a gate insulating film is formed after etching a trench on a SiC wafer,
FIG. 5 is a view showing a state in which polysilicon and a metal film are stacked on a trench in three steps for making the structure of FIG. 2,
FIG. 6 is a view showing a state where the polysilicon and the metal film are removed by CMP until reaching the trench etching prevention mask for planarization and insulation, and FIG.
FIG. 7 shows a state in which the source contact and the drain electrode are formed on the rear surface, and FIG. 7 shows the state of the source contact and the drain electrode in the fifth step for forming the structure of FIG. 2. As a part of the process for forming the source contact and the drain electrode, And FIG. 5B is a view showing a state in which a silicide layer is formed by reaction.
FIG. 8 is a view illustrating a state where a source-gate insulating film is formed on a trench to electrically isolate a gate electrode composed of a polysilicon + silicide layer + a metal layer from a source electrode in six steps for forming the structure of FIG.
FIG. 9 is a seventh step for forming the structure of FIG. 2, showing a state in which a source electrode is formed and is in electrical contact with a source contact.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a view showing a shape in which a gate electrode is formed of polysilicon, a silicide layer and a metal layer in a trench according to the present invention. FIG. 3 is a first step for forming the structure of FIG. FIG. 4 is a view illustrating a state in which a gate insulating film is formed after a trench is etched on a SiC wafer, which is a step for forming a structure of FIG. 2. FIG. , FIG. 5 is a view showing a state in which a polysilicon and a metal film are laminated on a trench, and FIG. 6 is a diagram showing four steps for forming the structure of FIG. 2, FIG. 7 is a view showing a state in which the silicon and the metal film are removed by CMP until reaching the trench etching prevention mask. FIG. 7 is a step for forming the structure of FIG. 2, 8 shows a state in which the drain electrode is formed on the rear surface and a silicide layer is formed by reacting polysilicon and a metal layer while performing a heat treatment process as a part of a process for forming a source contact and a drain electrode, 9 is a view showing a state in which a source-gate insulating film is formed on the trench in order to electrically isolate the gate electrode composed of the polysilicon + silicide layer + metal layer from the source electrode, as a sixth step for making the structure of FIG. 7 is a view showing a state in which a source electrode is formed and brought into electrical contact with a source contact.

As shown, the method for fabricating a SiC UMOSFET having a low gate resistance according to the present invention comprises: a first step of forming a screen oxide film and a trench etch-resistant hard mask layer on a SiC wafer; A second step of defining a region where the trench is to be formed as a photoresist, etching the SiC wafer to form a trench, and then forming a gate insulating film on the inner wall surface of the trench; A third step of successively depositing a polysilicon and a metal film so that the material is filled in the trench; A fourth step of polishing and removing the metal film and the polysilicon by chemical mechanical polishing (CMP) to planarize the metal film and the polysilicon; A source contact is formed on the front surface of the SiC wafer and a drain electrode is formed on the back surface of the wafer and heat treatment is performed to form an ohmic contact to the source contact and drain electrodes while simultaneously causing a reaction between the polysilicon and the metal in the trench, 5 steps; A sixth step of forming a source-gate insulating film on the trench; And a seventh step of forming a source electrode by depositing a metal film on the front surface of the SiC wafer so as to be electrically insulated from the gate electrode by the source-gate insulating film.

The structure proposed in the present invention is different from the conventional structure in which only the polysilicon 62 is filled in the trench 60 in which the gate insulating film 61 is formed as shown in FIG. (64), and a metal film (63).

As shown in FIG. 3, when the polysilicon 62 and the metal film 63 are in contact with each other, a silicide layer 64 is formed on the contact surface between the polysilicon 62 and the metal film 63, . Silicide is a compound of silicon and metal. It has a low resistivity (TiSi ₂ : 13 to 20 μΩ · cm, CoSi ₂ : 16 to 18 μΩ · cm, NiSi: 15 to 18 μΩ · cm) It is widely used in the submicron Si process because it greatly reduces the contact resistance between metals.

When the polysilicon 62, the silicide layer 64, and the metal film 63 function together as a gate electrode, as compared with the case where only the polysilicon 62 is used as the gate electrode as in FIG. 1, Thus, the gate electrode can be improved in conduction capacity, heat generation can be reduced, and the switching speed of the SiC UMOSFET can be improved.

In the present invention, a simplified manufacturing method that can easily form the structure of FIG. 2 is presented. According to the method presented in the present invention, the trench etch-resistant hard mask 44 can be successively used for trench etching, gate insulating film 61 growth, polysilicon 62 and metal film 64 CMP processes, A SiC UMOSFET having a gate electrode can be manufactured.

To facilitate understanding of the present invention, an embodiment showing a concrete implementation method of the above structure is presented below.

The present embodiment is only one example for helping to understand the concept presented in the present invention, and the core idea of the present invention is not limited to this.

1) Step 1:

A first conductivity type SiC region 42 is formed on a SiC wafer composed of a first conductivity type SiC substrate 20, a first conductivity type SiC layer 30 and a second conductivity type SiC layer 40 as shown in Fig. 3 It is formed by ion implantation. The SiC substrate 20 of the first conductivity type serves as a substrate of a SiC MOSFET structure to be formed thereon, and a high resistivity substrate is used with a resistivity of about 0.02? · Cm. The first conductive SiC layer 30 supports the voltage applied to the SiC UMOSFET as a power semiconductor. The thickness and concentration of the layer are selected according to the voltage rating of the SiC UMOSFET, 100 탆, and the doping concentration is in the range of 1 x 10 ¹⁴ / cm ³ to 1 x 10 ¹⁶ / cm ³ . The second conductive SiC layer 40 is a portion where a channel of the SiC UMOSFET is to be formed. The thickness of the second conductive SiC layer 40 is 0.5 to 3 μm and the doping concentration is 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁷ / cm ³ . ≪ / RTI > The first conductive type SiC region 42 formed on the first conductive type SiC region 42 is a region to serve as a source of the SiC UMOSFET and is generally doped with a high concentration of 1 x 10 ¹⁹ / cm ³ or more using an ion implantation technique.

A screen oxide film 43 is formed on a SiC wafer having such a structure, and a trench etch-resistant hard mask layer 44 is formed thereon. The purpose of forming the screen oxide film 43 is to protect the surface of a SiC wafer in a subsequent subsequent step. Generally, an oxide film is grown to a thickness of about 100 Å at a temperature of 1000 to 1200 ° C. by using oxygen or steam. . The trench etch-preventing hard mask layer 44 formed on the trench etch preventing mask 44 is masked so that portions other than the portions where the trenches 60 are to be formed are not etched in the subsequent trench etch process, and a gate insulating film 61 is formed on the inner walls of the trenches And also protects the surface of the SiC wafer when the polysilicon 62 and the metal film 63 are CMP. It is most preferable to use a silicon nitride film (Si ₃ N ₄ ) deposited by low-pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (CVD) method for the trench etch- Plasma Enhanced Chemical Vapor Deposition (PECVD)). However, the present invention is not limited to the silicon nitride film, and any material that can simultaneously perform the trench etching prevention, the oxide film formation prevention, and the CMP stopping layer as described in the present invention may be used.

A photoresist 80 pattern is then formed on the trench etch-resistant hardmask layer 44 to define the trench 60 region.

2) Step 2:

As shown in FIG. 4, the trench etching is performed using the photoresist 80 mask formed in the first step to define the trench 60. The trench 60 is formed by a dry etch method using plasma. In general, the source gas containing halogen elements such as SF ₆ , CF ₄ , CHF ₃ , and Cl ₂ , and O ₂ , H ₂ , He, Ar and the like are mixed and used. The trench etch process may be performed at one time using a photoresist 80 mask or if it is difficult to define a trench etch resistant hardmask layer 44 with a photoresist 80 mask followed by a photoresist 80 mask And the trench 60 may be etched using the trench etch-resistant hard mask layer 44 to perform a two-step etching process.

Thereafter, a gate insulating film 61 is formed in the trench 60 through an oxidation process. The gate insulating film 61 used for the SiC UMOSFET is substantially SiO _{2. In} this embodiment, description will be made only in the case where SiO ₂ formed by the oxidation process is used as a gate insulating film. The oxidation process of SiC usually proceeds by dry oxidation or wet oxidation at a high temperature of 1100 占 폚 or higher. At this time, the portion of the silicon nitride film covered with the trench anti-etching hard mask 44 is not oxidized.

After the gate insulating film 61 is formed by the oxidation process, the defect state of the interface between SiC and SiO ₂ is reduced through a post-oxidation annealing process. In general, the post-oxidation heat treatment process is performed at a temperature of 1100 to 1200 ° C for 30 minutes to 3 hours using N ₂ O or NO. It is known that the defect level of SiC and SiO ₂ interface is passivated by nitrogen ions after annealing process after oxidation, so that the concentration of defect level is greatly reduced and device characteristics of SiC UMOSFET are improved. At this time, it is very difficult for the nitrogen ions to diffuse and penetrate into the portion covered with the silicon nitride film trench etch-resistant hard mask 44, so that the characteristics of the ohmic contact are deteriorated due to the nitrogen ions in the formation of the N- The possibility of being excluded.

3) Step 3:

As shown in Fig. 5, the polysilicon 62 and the metal film 63 are sequentially deposited. The deposition process of the polysilicon 62 is well established in the silicon semiconductor process and is generally performed by low pressure chemical vapor deposition (LPCVD) to decompose the source gas such as SiH ₄ , SiH ₂ Cl ₂ , Respectively. In this case, a method of doping N type or P type dopant mixed with gases such as PH ₃ and B ₂ H ₆ is widely used in the process of depositing polysilicon. Alternatively, the polysilicon 62 is doped at a high concentration of 1 x 10 ²⁰ / cm ³ or more through ion implantation or heat treatment using POCl ₃ or the like. After the highly doped polysilicon 62 is formed, the metal film 63 is deposited to fill the trench 60 with the metal film as shown in FIG. The material of the metal film 63 is preferably, but not limited to, a metal, such as Ni, Ti, Co, W, which is widely used for silicide formation in a silicon semiconductor process. When depositing the metal film 63, it is important to apply an evaporation technique with excellent step coverage so that voids not filled in the trench 60 are not formed.

4) Step 4:

The polysilicon 62 and the metal film 63 are removed by the CMP technique as shown in FIG. 6 to simultaneously planarize while limiting the polysilicon 62 and the metal film 63 around the trench 60 . First, the metal film (63) is subjected to CMP followed by polysilicon CMP. Metal CMP is generally based on Al ₂ O ₃ slurry. The type of dispersion solution, pH, and slurry concentration are varied depending on the type of metal used. Polysilicon CMP is generally based on SiO ₂ slurry and proceeds at pH 11-12.

5) Step 5:

The screen oxide film 43 and the trench etch preventing hard mask 44 are not removed but continue to be used as a part of the final device even after the above four steps.

A source contact 51 is formed on the front surface through a photo / etch process to define a source region as shown in FIG. 7, a metal film is deposited on the entire back surface to form a drain electrode 10, A heat treatment process is performed to lower the contact resistance. In this process, the polysilicon 62 and the metal film 63 in the trench 60 react with each other to form the silicide layer 64, thereby lowering the resistance of the trench gate.

The source contact 51 and the drain electrode 10 are formed of a metal such as Ni, Ti, Pt, W, Ta, Mo, Au, etc. frequently used for forming an ohmic junction using a silicide formation reaction in a SiC element And in the case of the source contact 51, an ohmic contact can be formed simultaneously with the first conductivity type SiC region 42 and the second conductivity type SiC layer 40. The thickness of the metal film for forming the source contact 51 is generally in the range of 100 nm or less and the drain electrode 10 on the back surface is used by depositing a thick metal film of 1 μm or more in order to conduct a large amount of current Most cases. The heat treatment process for inducing silicide formation is generally performed at a high temperature of 900 ° C or higher in an SiC device and proceeds in an inert atmosphere such as Ar or N ₂ . When rapid thermal annealing is used, the heat treatment time is greatly shortened compared to when using a furnace, and the silicidation reaction can be completed within 3 minutes.

6) Step 6:

A source-gate insulating film 52 is formed as shown in FIG. 8 to electrically isolate the gate electrode composed of {the polysilicon 62 + the silicide 64 + the metal 63} from the source electrode. The source-gate insulating film 52 is formed by patterning an SiO ₂ film having a thickness of about 1 μm generally deposited by a PECVD method.

7) Step 7:

A metal film is deposited to form a source electrode 53 as shown in FIG. The source electrode 53 is generally formed by depositing a thick Al film with a thickness of 1 탆 or more by sputtering and then patterning through a photo / etch process by using a silicon semiconductor process. In the subsequent packaging process, wire bonding ). ≪ / RTI >

When the SiC UMOSFET is fabricated by the above method, the resistance of the trench gate electrode can be greatly reduced, thereby increasing the current density that can flow through the gate electrode, thereby increasing the switching speed of the SiC UMOSFET. It may also alleviate heat problems due to high resistance.

10: drain electrode 20: first conductivity type SiC substrate
30: first conductivity type SiC layer 40: second conductivity type SiC layer
42: first conductivity type SiC region 43: screen oxide film
44: trench etch-resistant hard mask 51: source contact
52: source-gate insulating film 53: source electrode
60: Trench 61: Gate insulating film
62: polysilicon 63: metal film
64: silicide layer 80: photoresist

Claims (8)

A silicon carbide (SiC) UMOSFET fabrication method using a trench gate structure,
A first step of forming a screen oxide film and a trench etch-resistant hard mask layer on a SiC wafer;
A second step of defining a region where the trench is to be formed as a photoresist, etching the SiC wafer to form a trench, and then forming a gate insulating film on the inner wall surface of the trench;
A third step of successively depositing polysilicon and a metal film so that the polysilicon and the metal film are filled in the trench;
A fourth step of polishing and removing the metal film and the polysilicon by chemical mechanical polishing (CMP) to planarize the metal film and the polysilicon;
A source contact is formed on the front surface of the SiC wafer and a drain electrode is formed on the back surface of the wafer and heat treatment is performed to form an ohmic contact to the source contact and drain electrodes while simultaneously causing a reaction between the polysilicon and the metal in the trench, Forming a silicide layer on the substrate;
A sixth step of forming a source-gate insulating film on the trench; And,
And a seventh step of forming a source electrode by depositing a metal film on the front surface of the SiC wafer and electrically insulated from the gate electrode by the source-gate insulating film. [7] The SiC UMOSFET Gt; The method according to claim 1,
Characterized in that a silicon nitride is used as said trench etch-resistant hardmask layer. The method according to claim 1,
Wherein the trench etch-resistant hardmask layer formed in the first step is used as a CMP stopping layer in the CMP process of the fourth step. The method according to claim 1,
The trench etch preventing hard mask formed in the first step protects the remaining portion except for the inner wall surface of the trench in the gate insulating film forming process of the second stage so that finally the gate insulating film remains in the final device structure except the inner wall surface of the trench Wherein the SiC UMOSFET has a low gate resistance. The method according to claim 1,
Wherein the gate insulating layer is a silicon dioxide layer formed by an oxidation process. The method according to claim 1,
Wherein the gate insulating layer is a silicon oxide layer formed by a deposition process. The method according to claim 1,
Wherein the metal film formed in the third step is one of Ni, Ti, W, Co, Ta, and Pt. The method according to claim 1,
Wherein the screen oxide layer and the trench etch-resistant hardmask layer formed in the first step are included in the final device structure.

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