KR101377403B1 - Integrating current regulator and method for regulating current - Google Patents

Abstract

The present invention relates to a current regulator and related method for regulating current through a load. The current regulator includes, for example, a first circuit configured to measure the amount of current flowing through the load and a second circuit configured to apply a voltage across the load having a duty cycle that depends on the amount of current flowing through the load. can do.

Description

INTEGRATING CURRENT REGULATOR AND METHOD FOR REGULATING CURRENT}

The present invention relates to a current regulator and associated method for regulating the current through a load.

Hysteresis regulators or two-point regulators for the purpose of regulating current through inductive loads are well known. In the case of such a regulator, a supply voltage is periodically applied to the load, in which case the current flowing through the load is measured. In this case, the supply voltage is switched off when the current exceeds a predetermined upper limit and switched on when the current falls below a predefined lower limit. Under ideal conditions, i.e., in the current of exactly triangular profiles going up when the supply voltage is applied and going down when the supply voltage is not applied, the average value of the current corresponds to the average value of the upper and lower hysteresis thresholds.

More complex regulators have a closed control loop. In the case of these regulators, the supply voltage is periodically applied to the load and the current flowing through the load is measured. The regulator is used to generate a pulse width modulated drive signal from the measurements obtained in this way, which drive the switch periodically connected to the load to apply a supply voltage to the load.

Various embodiments of the current regulator for regulating current through a load are disclosed herein. For example, the current regulator includes a first circuit for measuring the amount of current flowing through the load, and a second circuit for applying a voltage across the load with a duty cycle that depends on the amount of current flowing through the load. Also disclosed herein is a method performed by a current regulator embodiment.

These and other features will be described in detail below.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The drawings are used to illustrate the basic principles of the invention and do not represent all the circuit components necessary for a functional configuration. In the drawings, unless otherwise specified, like reference numerals denote like signals and circuit components having the same meaning.

One embodiment of a current regulator according to aspects of the present invention is shown in FIG. 1. This current regulator has connection terminals 11, 12 for connecting the load, in particular for connecting an inductive load or at least a load with inductance. Such inductive loads or loads with inductance are explicitly shown in FIG. 1 for the purpose of understanding and are indicated by reference numeral 10. The current regulator also has a switching circuit 30 for applying a pulse-width-modulated supply voltage V10 to the load 10 between the connection terminals 11, 12. The switching circuit 30 is designed to generate this pulse width modulation voltage V10 from the input voltage Vin of the current regulator, the input voltage being a terminal for the first supply potential V and a second supply potential GND. It is applied between the terminals. The first supply potential V is, for example, a positive supply potential. The second supply potential GND can be the reference of all voltages occurring in the circuit, for example as a reference potential, in particular a ground potential. In this case, the magnitude of the input voltage Vin corresponds to the magnitude of the supply potential V.

In order to generate the pulse width modulation supply voltage from the input voltage Vin, the switching circuit 30 is connected to the connection terminals 11 and 12 in such a manner that the load 10 is connected in series with the load if present. Has In the example shown, this switch is connected between the second connection terminal 12 and the terminal for the second supply potential GND. In this case, the first connection terminal 11 of the current regulator is connected to the terminal for the first supply potential V.

The switch 31 is driven by the pulse width modulation drive signal S30 generated by the drive circuit 32 in the manner described below. When the switch 31 is periodically opened and closed by the drive signal S30, during the drive cycle, the switch is closed for the switched-on period and opened for the switching off period following the switching on. Assuming that the unavoidable line resistance is much smaller than the resistance of the load 10, when the switch 31 is closed, approximately the entire supply voltage Vin is applied between the connecting terminals 11 and 12 to be connected across the load. Is approved. During these switching on periods, the pulse width modulation supply voltage V10 is approximately at a first voltage level corresponding to the input voltage Vin. When the switch 31 is opened, approximately the entire input voltage Vin is applied across the switch 31 so that the voltage between the connecting terminals 11, 12, ie across the load 10, is at least approximately zero. . This corresponds to the second voltage level of the pulse width modulated supply voltage V10 during the switching off period.

The switch 31 is, for example, a semiconductor switch such as a MOSFET or an IGBT.

The current regulator shown in FIG. 1 is also designed to detect a resistive current I 10 flowing through the load 10 and generate a current measurement signal S 20 that depends on this current, in particular proportional to this current I 10. It has a current measuring circuit 20. The inductive load 10 consumes electrical energy during the switching on period. To avoid the high voltage across the switch 31 generated by the energy still stored in the inductive load 10 after the switch 31 is switched off, a freewheeling element such as a diode, for example. 13 may be provided. In order to be able to detect current through the load during the switching on period and the switching off period, the freewheeling element 13 has a series circuit comprising the load 10 and the current measuring circuit 20 when the load 10 is present. It is connected so as to be connected in parallel. To this end, according to this example, the freewheeling element 13 is between one of the connecting terminals, ie between the first connecting terminal 12 and the connecting portion of the current measuring circuit 20 which is spaced apart from the other connecting terminal 13. Is connected to.

The current measuring signal S20 generated by the current measuring circuit 20 is provided to the driving circuit 32 of the switching circuit 30 together with the reference current signal ST. In this case, the reference current signal ST predetermines a desired value for the average value of the current flowing through the load 10. The drive circuit 32 is designed to generate a drive signal S30 for the switch 31 based on the time integration of the current measurement signal S20 and the time integration of the reference current signal ST. The driving circuit 32 measures, for example, the time integration of the reference current signal ST and the time integration of the current measurement signal S20 during the driving cycle, and compares at least the integrals obtained during the switching off period of the driving signal. , It is designed to start a new drive cycle when the integration of the current measurement signal S20 is less than the integration of the reference current signal ST. Thus, the duty ratio of the pulse width modulation supply voltage V10, i.e., the ratio between the switch-on period and the switch-off period or the period between the switching-on period and the period of the driving cycle, is determined by the current measurement signal S20 in the case of this current regulator. It depends on the integration and the integration of the reference current signal ST.

In the current regulator shown in FIG. 1, the switch 31 of the switching circuit 30 and the current measuring circuit 20 are connected between the second connection terminal 12 and the terminal for the second supply potential GND. This is just one example. Thus, the current measuring circuit 20 and the switch 31 may also be connected between the terminal for the first supply potential V and the first connection terminal 11, wherein one of these two circuit components is connected to the first supply potential ( V) and the first connection terminal 11 can be connected, and another one of these circuit components can be connected between the second connection terminal 12 and the terminal for the second supply potential GND.

Referring to FIG. 2, the current measuring circuit 20 has, for example, a current measuring resistor 21 connected in series with the load 10 and the switch 31. The current measuring resistor 21 is, for example, a nonreactive resistor, and the voltage drop V21 across the current measuring resistor is a load current flowing through the load 10 when the switch 31 is closed. Directly proportional to I10). In order to detect this voltage drop V21 and provide a current measuring signal S20, the current measuring circuit 20 also includes a current measuring amplifier 22, for example in the form of an operational amplifier, which current The measuring resistor 21 is connected to be located between the inputs of the current measuring amplifier 22. The current measuring signal S20 can be obtained at the output of the current measuring amplifier 22.

Referring to FIG. 2, the drive circuit 32 has a first integrator for receiving a current measurement signal S20 and providing a first integrated signal S33 depending on the current measurement signal S20, for example. . The drive circuit 32 also has a second integrator 34 which is supplied with a reference current signal ST and provides a second integrated signal S34 which depends on this reference current signal ST. Integral signals S33 and S34 are applied to comparator 35, and the comparator compares these two integrated signals to produce comparison signal S35 according to this comparison. The comparison signal S35 is supplied to the pulse width modulator 36, and the pulse width modulator generates a pulse width modulation signal S30 for driving the switch 31 based on the comparison signal S35.

An operation method of the current regulator shown in FIGS. 1 and 2, in particular, an operation method of the driving circuit 30 for generating the pulse width modulated signal S30 will be described below with reference to FIG. FIG. 3 shows exemplary time profiles of the current measurement signal S20, the reference current signal ST, the pulse width modulation drive signal S30 and the first and second integrated signals S33 and S34.

For the purpose of explanation, it is assumed that the reference current signal ST is a constant signal which does not change the desired power consumption at the load, that is, the power consumption of the desired value during the consideration period of FIG. 3. In addition, due to parasitic effects such as, for example, the line resistance or non-reactive resistance component of the inductive load, the time profile of the load current (I10) as in the case of an ideal inductive load operating below the saturation region, thus in this example It is assumed that the time profile of the current measurement signal S20 is not triangular. In the embodiment shown in FIG. 3, the current through the load 10 rises exponentially in some intervals when the switch is closed, ie during the switching on period Ton, and when the switch is opened, ie the switching off period Toff. D) to exponential functions in some intervals. Disregarding the parasitic effect, the saturation effect that occurs when the switching on period is long enough that the inductive load 10 becomes saturated may also affect the illustrated time profile. For illustration, in the time profile shown in FIG. 3, it is assumed that the switch 31 is turned on when the drive signal S30 is at the high level and the switch 31 is turned off when the drive signal S30 is at the low level. do.

Integrators 33 and 34 of the drive circuit 32 shown in FIG. 2 integrate the current measurement signal S20 from the start current measurement signal S20 of the drive cycle and start from the same initial value, for example zero. It is designed to integrate the reference current signal ST. For illustrative purposes, assume that a new drive cycle starts at the beginning of the switching on period of the switch 31. In this case, the integrators 33 and 34 are reset to their initial values at the start of the drive cycle, respectively, for example by the drive signal S30. This reset is completed, for example, by the rising edge of the pulse width modulation drive signal S30.

The second integration signal S34, which represents the time integration of the reference current signal ST, rises linearly with respect to time from the start of the drive cycle, while the first integration signal that represents the time integration of the current measurement signal S20. The rising rate of S33 is variable. In the time profile of the current measurement signal S20 or the load current shown in FIG. 3, the first integrated signal S33 is initially smaller than the second integrated signal S34 but rapidly after the start of the drive cycle. The integral signal S34 is exceeded.

In the drive circuit 32 shown in FIG. 2, the comparison signal S35 performs the function of a switch on signal which predefines the start of the switching on period of the switch 31. The switching on period Ton, ie the duration of the switching on period, is constant for all drive cycles in the illustrated example. On the other hand, the duration of the switching off period Toff or the switching off period and the total duration T of the drive cycles can be varied to adjust the power consumption. When the first integrated signal S33 falls below the value of the second integrated signal S34 after the switch 31 is opened, i.e., during the switching off period, the end of the drive cycle and the start of a new drive cycle meet. . In the case of the drive circuit 32 shown in Fig. 2, there is a switch on signal S35 at the rising edge of the comparison signal or at such a point in time.

4 generates a switch-on level of the pulse width modulation signal S30 according to the switch-on signal S35 to switch on the switch 31, and after the predetermined switching-on period Ton elapses, the driving signal ( One embodiment of a pulse width modulator 36 is shown which generates the switch off level of S30 and switches off the switch 31. The illustrated pulse width modulator 36 has an RS flip-flop 361 having a setting input S, a reset input R and a non-inverting output Q for obtaining a pulse width modulation drive signal S30. . The switch on signal S35 is applied to the setting input unit S. The flip-flop 361 shown is set at a predefined edge, for example a rising edge, of the switch on signal S35, so that the pulse width modulated signal S30 is at a predefined signal level, in this example a high level. Take The pulse width modulator 36 also has a delay element 362 that is supplied with a switch on signal S35. The output signal S362 from this delay element is supplied to the reset input R of the flip flop 361. Delay element 362 transfers switch on signal S35 to reset input R of flip-flop 361 with a predefined delay time corresponding to switching on period Ton, as a result of which switching on period After this elapses, the set flip-flop 361 is reset again, and after the switching-on period elapses, the drive signal S30 takes a switch off level, in this example a low level.

5 illustrates another exemplary embodiment of a pulse width modulator 36. This pulse width modulator includes an OR gate 363, which is different from that shown in FIG. 4, which is connected upstream of the reset input R of the flip-flop 361, and the inputs thereof. One is supplied with the delay signal S362 obtained at the output of the delay element 362, and the other is supplied with the overcurrent switch off signal S364. The overcurrent switch off signal S364 is obtained at the output of the comparator 364, one of the inputs of the comparator receives the current measurement signal S20, and the other input supplies the maximum current signal Smax. Receive. In this case, the maximum signal Smax represents the maximum allowable load current. In this pulse width modulator 36, the flip-flop 361 is configured when the delay signal S362 takes a high level or the overcurrent switch off signal S364 takes a high level, i.e., when the switching on period has elapsed or under load. Reset when current I10 exceeds the maximum allowable current before the switching on period elapses. Thus, the pulse width modulator 36 shown in FIG. 5 allows the current regulator to be protected against overcurrent.

6 illustrates another exemplary embodiment of a pulse width modulator. Unlike the pulse width modulator shown in FIG. 5, this pulse width modulator does not have a delay element to set a constant switching on period. In the case of this pulse width modulator, the flip-flop 361 is reset only based on the comparison between the current measurement signal S20 and the maximum current signal Smax. For this purpose, the reset input R of the flip-flop 361 receives only the output signal S364 from the comparator 364. When this pulse width modulator is used, the load current generally rises to the current value determined by the maximum current value Smax during the switching-on period, so that the switching-on period Ton is applied to different loads and different input voltage Vin. Can be varied.

In order to generate the integrated signals S33 and S34, the current regulator shown in FIG. 2 includes integrators 33 and 34 that continuously integrate the current measurement signal S20 and the reference current signal ST over time. . These integrators 33 and 34 include, for example, a voltage controlled current source and a capacitance connected downstream of the current source in a manner not shown. In this case, the current source generates a current that depends on the current measurement signal S20 and the reference current signal ST, and charges the capacitance starting from the initial value. In this case, the voltage across the capacitance corresponds to the integrated signals S33 and S34.

With reference to FIG. 7, instead of successive integrators 33 and 34 generating integrated signals S33 and S34, the sample values S372 and S382 of the current measurement signal S20 and the reference current signal ST are added. Discrete-time integrators 37 and 38 may also be used. These discrete integrators 37 and 38 sample, for example, the current measurement signal S20 and the reference current signal ST according to the clock signal CLK at regular time intervals predefined by the clock signal CLK. Sampling elements 372 and 382 to generate sample values S372 and S382. In this case, adders 371 and 381 which respectively add sample values S372 and S382 starting from an initial value such as 0 are connected downstream of the sampling element 372. These addition elements 371 and 381 are respectively reset to their original values at the start of the drive cycle, for example using a pulse width modulated signal S30. The signals S37 and S38 which are obtained at the output of the addition elements 371 and 381 and perform the functions of the continuous signals S33 and S34 described with reference to FIG. 2 are the current measurement signal S20 and the reference current signal ST. Discrete time integration signal of These discrete time signals S37, S38 are provided to a comparator 35, and at its output it is possible to obtain a switch on signal S35, which is a comparison of these discrete time integrated signals S37, S38. Depends on

For the sake of understanding, FIG. 3 shows the discrete time integration signals S37 and S38 as a result of one of the drive cycles as well as the sample values S372 and S382 of the current measurement signal S20 and the reference current signal ST. Doing. In this case, Tclk represents the duration of the sampling period in which the current measurement signal S20 and the reference current signal ST are each sampled once. This applies to the sampling frequency, ie fclk = 1 / Tclk. The two signals S20 and ST are each sampled at the same time point. As in the case of continuous time, the switch-on signal S35 is a signal of the second integrated signal S38 in which the first integrated signal S37 that depends on the current measurement signal S20 depends on the reference current signal ST. Takes the signal level to start a new switching-on period when below the value.

In the present invention, the "integration signal" is a continuous-time integration signal formed by the continuous time integration of the current measurement signal S20 or the reference current signal ST, and the current measurement signal ( S20) or the discrete time integrated signal formed by adding the sample value of the reference current signal ST.

8 shows another exemplary embodiment of a drive circuit 30 for generating a pulse width modulated drive signal S30. The driving circuit 30 includes a subtractor 39 supplied with the current measuring signal S20 and the reference current signal ST, and at its output between the current measuring signal S20 and the reference current signal ST. A difference signal Sdiff indicating the difference can be obtained. This difference signal Sdiff is provided to the integrator, and the integrator integrates the difference signal Sdiff to generate an integrated signal S40. In contrast to the exemplary embodiment described above, this integrator 40 need not be reset at the start of the drive cycle. Integral signal S40 is provided to comparator 35, the comparator detects the zero point of integral signal S40 and compares this with integrated signal S40 and reference potential GND or, for example, zero potential. .

FIG. 9 shows the integration S40 of the difference signal Sdiff based on the time profile for the current measurement signal S20 and the reference current signal ST shown in FIG. 3. 9 also shows that the comparison signal S35 takes a high level when the integral S40 of the difference signal Sdiff is less than zero and takes a low level when the integration S40 of the difference signal Sdiff is greater than zero. Assuming that the comparator 35 is implemented, the comparison signal S35 due to this integrated difference signal is shown. In the drive circuit 30 shown in Fig. 8, the drive cycle, i.e., the start of the switching on cycle starts with the rising edge of the output signal S35 from the comparator 35, i.e. the rising edge of the switch on signal. The duration Ton of the switching on period is determined by the pulse width modulator 36 in the manner described above. 9 also shows the time profile of the drive signal S30 based on the switch on signal S35 for understanding.

In the case of the current regulator with the drive circuit 30 shown in FIG. 8, the ratio between the switching on period Ton and the switching off period Toff is between the current measurement signal S20 and the reference current signal ST. Depends on the integration of the difference Sdiff and therefore on the difference between the integration of the current measurement signal S20 and the integration of the reference current signal ST.

In the case of the drive circuit 30 shown in FIG. 8, the continuous time integrator 40 can be replaced with a sampling element and an adder, which is connected downstream of the sampling element in accordance with the description with respect to FIG. 7. No further details are given.

The above-described current regulator and the current regulation method using this current regulator function regardless of the type of load, especially whether or not the inductive load 10 becomes saturated during the switching on period. In addition, the current regulator and the current regulation method can react quickly to the change of the reference current value ST, so that the average value of the current I10 flowing through the load 10 is adjusted to a new reference value, so that only one driving cycle Only takes In addition, the current regulator and the current regulation method are robust to changes in the input voltage Vin.

1 is a circuit diagram of an exemplary embodiment of the current regulator of the present invention having a load connection terminal, a current measuring device and a switching device for applying a pulse width modulated supply voltage to the connection terminal.

FIG. 2 is a circuit diagram of the current regulator shown in FIG. 1 showing the current measuring device and the switching device in more detail. FIG.

3 illustrates a method of operating the current regulator shown in FIGS. 1 and 2 using the time profile of the signal occurring in the current regulator.

4 is a circuit diagram of a first embodiment of a pulse width modulator present in the switching device shown in FIG.

5 is a circuit diagram of a second embodiment of a pulse width modulator.

6 is a circuit diagram of a third embodiment of a pulse width modulator.

7 is a circuit diagram of another embodiment of the current regulator of the present invention.

8 is a circuit diagram of another embodiment of a drive circuit for generating a pulse width modulated signal for a switch of a switching device in series with a load.

9 illustrates a method of operating the drive circuit shown in FIG. 8 using a time profile of a signal occurring in the drive circuit.

Claims (22)

Current regulator that regulates the current flowing through the load, A current measurement circuit configured to measure an amount of current flowing through the load to generate a current measurement signal according to the amount of current; A switching circuit configured to cycle between a first state and a second state and to receive a reference current signal and apply a supply voltage across the load, The supply voltage has a first voltage level during the first state and a second voltage level during the second state, Wherein the switching circuit comprises: Integrating the difference between the current measurement signal and the reference current signal during each drive cycle to obtain a difference integration signal, Is further configured to start a new drive cycle in response to the difference integration signal reaching a predetermined threshold after the end of the duration of the first state, The duration of the first state is constant for all drive cycles Current regulator. delete delete delete delete Current regulator that regulates the current flowing through the load, A current measurement circuit configured to measure an amount of current flowing through the load to generate a current measurement signal according to the amount of current; A switching circuit configured to cycle between a first state and a second state, to receive a reference current signal and to apply a supply voltage across the load, The supply voltage has a first voltage level during the first state and a second voltage level during the second state, Wherein the switching circuit comprises: Integrating both the current measurement signal and the reference current signal over time to obtain a time integration of the current measurement signal and a time integration of the reference current signal during each drive cycle, Is further configured to start a new drive cycle in response to the integration of the current measurement signal being smaller than the integration of the reference current signal after the end of the duration of the first state, The duration of the first state is constant for all drive cycles Current regulator. delete delete delete The method of claim 6, The switching circuit is configured to integrate the current measurement signal and the reference current signal in a continuous-time manner to obtain a time integration of the current measurement signal and a time integration of the reference current signal. Current regulator. The method of claim 6, The switching circuit is configured to add a sample value of the current measurement signal and a sample value of the reference current signal to obtain a time integration of the current measurement signal and a time integration of the reference current signal. Current regulator. delete delete In the method of controlling the current flowing through the load, Applying a supply voltage to the load that circulates between a first voltage level during a first period and a second voltage level during a second period; Generating a current measurement signal according to the amount of current flowing through the load; Integrating the difference between the current measurement signal and a reference current signal during each drive cycle to obtain a difference integration signal; Starting a new drive cycle in response to the difference integration signal reaching a predetermined threshold after the end of the duration of the first period, The duration of the first cycle is constant for all drive cycles Current regulation method. delete delete In the method of controlling the current flowing through the load, Applying a supply voltage to the load that circulates between a first voltage level during a first period and a second voltage level during a second period; Generating a current measurement signal according to the amount of current flowing through the load; Integrating both the current measurement signal and the reference current signal over time to obtain a time integration of the current measurement signal and a time integration of the reference current signal during each drive cycle; Starting a new drive cycle in response to the integration of the current measurement signal being smaller than the integration of the reference current signal after the end of the duration of the first period, The duration of the first cycle is constant for all drive cycles Current regulation method. 18. The method of claim 17, Integrating the current measurement signal and the reference current signal in a continuous-time manner to obtain a time integration of the current measurement signal and a time integration of the reference current signal; Current regulation method. 18. The method of claim 17, Summing a sample value of the current measurement signal and a sample value of the reference current signal to obtain a time integration of the current measurement signal and a time integration of the reference current signal; Current regulation method. delete delete delete

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