KR101330405B1 - OLED display apparatus and drive method thereof - Google Patents

Abstract

The present invention provides an organic light emitting diode display device that can reduce stress of a driving transistor of a pixel by refreshing the pixel before the actual data voltage implemented in gray scale is supplied to the pixel, wherein m data lines and n gates are provided. A display panel in which pixels including organic light emitting diodes are formed so that the lines cross each other and corresponding to the crossing areas one by one, and n control lines are formed; A cell control voltage generator for generating a cell control voltage for controlling initialization, refresh, and data implementation of each pixel and selectively supplying the n control lines to the n control lines; A data driver converting input digital data to supply analog data voltages to the m data lines; And a gate driver sequentially supplying scan pulses to the n gate lines.

Organic light emitting diode, display, refresh, data voltage

Description

Organic light emitting diode display and driving method thereof

1 is an equivalent circuit diagram of pixels constituting a general organic light emitting diode display.

2 is a block diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

3 and 4 are signal characteristic diagrams of an organic light emitting diode display according to an exemplary embodiment of the present invention.

Fig. 5 is an equivalent circuit diagram of each pixel of the organic light emitting diode display according to the first embodiment of the present invention.

6 is an equivalent circuit diagram of each pixel of an organic light emitting diode display according to a second exemplary embodiment of the present invention.

7 is an equivalent circuit diagram of each pixel of an organic light emitting diode display according to a third exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: organic light emitting diode display device 110: display panel

120: cell control voltage generator 130: timing controller

140: data driver 150: gate driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode display and a method of driving the same, which can reduce the stress of a driving transistor of a pixel by refreshing the pixel before the actual data voltage implemented in gray scale is supplied to the pixel. It is about.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such flat panel displays include liquid crystal displays, field emission displays, plasma display panels, and electro-luminescence (hereinafter, referred to as "EL"). Display).

Among them, the EL display device is a self-luminous element which emits a phosphor by recombination of electrons and holes, and is roughly divided into an inorganic EL using an inorganic compound as an phosphor and an organic EL using an organic compound. The EL display device is expected to be the next generation display device because it has many advantages such as low voltage driving, self-luminous, thin film type, wide viewing angle, fast response speed and high contrast.

An organic EL display device usually consists of an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer stacked between a cathode and an anode. In such an organic EL display device, when a predetermined voltage is applied between the anode and the cathode, electrons generated from the cathode move to the light emitting layer through the electron injection layer and the electron transport layer, and holes generated from the anode are transferred to the hole injection layer and the hole transport layer. It moves to the light emitting layer through. Accordingly, the light emitting layer emits light by recombination of electrons and holes supplied from the electron transporting layer and the hole transporting layer.

A circuit configuration of each pixel formed in the general organic light emitting diode display using the organic EL will be described with reference to FIG. 1.

1 is an equivalent circuit diagram of pixels constituting a general organic light emitting diode display.

Referring to FIG. 1, each pixel of a typical organic light emitting diode display device is turned on by a scan pulse supplied through a gate line GL to switch a data voltage supplied through a data line DL. Organic light turned on by the driving current supplied from the power terminal to which S_TR1, the data voltage supplied through the switch transistor S_TR1, and the storage capacitor Cst and the high potential power voltage VDD are applied. The light emitting diode OLED and a driving transistor D_TR1 for turning on by the data voltage supplied through the switch transistor S_TR1 or the charging voltage of the storage capacitor Cst to drive the organic light emitting diode OLED are provided.

The switch transistor S_TR1 is an NMOS transistor having a gate connected to the gate line GL, a drain connected to the data line DL, and a source connected in common to the storage capacitor Cst and the gate of the driving transistor D_TR1. . The switch transistor S_TR1 is turned on by a scan pulse supplied through the gate line GL to supply a data voltage supplied through the data line DL to the gate of the storage capacitor Cst and the driving transistor D_TR1. .

One side of the storage capacitor Cst is commonly connected to the gates of the switch transistor S_TR1 and the driving transistor D_TR1, and the other side thereof is connected to ground to charge the data voltage supplied through the switch transistor S_TR1. The storage capacitor Cst has its own charging voltage when the data voltage being supplied through the switch transistor S_TR1 is not applied to the gate of the driving transistor D_TR1, that is, when the gate voltage of the driving transistor D_TR1 is lowered. Is discharged to hold the gate voltage of the driving transistor D_TR1. Accordingly, the driving transistor D_TR1 is turned on by the charging voltage of the storage capacitor Cst during the holding period by the storage capacitor Cst even when the supply of the data voltage supplied through the switch transistor S_TR1 is stopped. do.

The organic light emitting diode OLED has an anode connected to a power supply terminal to which a high potential power supply voltage VDD is applied, and a cathode connected to a drain of the driving transistor D_TR1.

The driving transistor D_TR1 is an NMOS transistor having a source connected to the source of the switch transistor S_TR1 and the storage capacitor Cst, a drain connected to the cathode of the organic light emitting diode OLED, and a source connected to ground. . The driving transistor D_TR1 is turned on by the data voltage supplied to the gate through the switch transistor S_TR1 or the charging voltage of the switch transistor S_TR1 supplied to the gate, so that the driving current flowing through the organic light emitting diode OLED is grounded. By switching, the organic light emitting diode OLED is allowed to emit light by the driving current generated by the high potential power voltage VDD.

In the conventional organic light emitting diode display having pixels having the equivalent circuit, the gate charging voltage is maintained even when the driving transistor D_TR1 is turned from the turned-on state by the DC voltage applied to the gate. Therefore, the driving transistor D_TR1 is deteriorated. In particular, the conventional organic light emitting diode display has a problem in that an afterimage occurs on the screen because the voltage charged in the gate of the driving transistor D_TR1 in the previous frame is maintained until the current frame.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the stress of a driving transistor of a pixel by refreshing the pixel before the actual data voltage implemented in gray scale is supplied to the pixel. A light emitting diode display and a driving method thereof are provided.

Another object of the present invention is to provide an organic light emitting diode display and a method of driving the same, which can prevent deterioration of the driving transistor by reducing stress of the driving transistor of the pixel.

In the organic light emitting diode display of the present invention for achieving the above object, m data lines and n gate lines cross each other and pixels including the organic light emitting diodes are formed to correspond to the crossing regions one by one. a display panel on which n control lines are formed; A cell control voltage generator for generating a cell control voltage for controlling initialization, refresh, and data implementation of each pixel and selectively supplying the n control lines to the n control lines; A data driver converting input digital data to supply analog data voltages to the m data lines; And a gate driver sequentially supplying scan pulses to the n gate lines.

The cell control voltage generation unit may include a positive cell control voltage, a negative cell control voltage, and a positive cell control voltage to pixels connected to one control line during a horizontal period in which scan pulses are supplied to one horizontal line including one gate line. The cell control voltage of the ground voltage level is sequentially supplied.

The cell control voltage generation unit sequentially sequentially the cell control voltage of the positive cell control voltage, the negative cell control voltage, and the ground voltage level during the reset period, the refresh period, and the actual data implementation period, which are sequentially performed within one horizontal period. It is characterized by supplying to each pixel.

The data driver may sequentially supply a reset voltage, a data voltage of 0V, and an actual data voltage during the reset period, the refresh period, and the actual data implementation period, respectively.

The cell control voltage generator may sequentially supply the negative cell control voltages in units of i horizontal lines of the n control lines to refresh pixels formed in the i horizontal lines.

The cell control voltage generator is the first of the i horizontal lines to be refreshed every time the scan pulse is sequentially supplied to the n gate lines and then sequentially supplied from the first gate line to the last gate line Rather than supplying the negative cell control voltage to a horizontal line, the negative cell control voltage is sequentially supplied from a second horizontal line to a horizontal line located next to the last horizontal line.

Each pixel may include: a switch transistor turned on by a scan pulse supplied through a gate line to switch a data voltage supplied through the data line; A storage capacitor charging a data voltage supplied through the switch transistor; An organic light emitting diode which is turned on by a driving current supplied from a power source and emits light; And a driving transistor turned on by the charging voltage of the storage capacitor to drive the organic light emitting diode.

The storage capacitor is characterized in that one side is commonly connected to the source of the switch transistor and the gate of the driving transistor and the other side is connected to the control line.

The storage capacitor may be initialized by the positive cell control voltage supplied through the switch transistor and the reset voltage supplied through a control line during the reset period.

The storage capacitor charges the actual data voltage supplied through the switch transistor by the cell control voltage of the ground voltage level supplied to the control line during the actual data implementation period.

The driving transistor has a drain connected to the drain of the source transistor and the storage capacitor, a drain connected to the cathode of the organic light emitting diode, and a source connected to the gate line.

The voltage across the gate of the driving transistor may be removed during the refresh period when the negative cell control voltage is supplied to the control line.

The driving transistor is turned on by the charging voltage of the storage capacitor while driving the organic light emitting diode while the scan pulse is supplied to the horizontal line next to the current horizontal line including the current horizontal line. It is characterized by.

According to an embodiment of the present invention, an organic light emitting diode including an organic light emitting diode is formed such that m data lines and n gate lines cross each other and correspond to the crossing regions one by one, and n control lines are formed. A method of driving a display device, the method comprising: generating a cell control voltage for controlling initialization, refresh, and data implementation of each pixel and selectively supplying the control voltage to the n control lines; Converting input digital data to supply an analog data voltage to the m data lines; And sequentially supplying scan pulses to the n gate lines.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, in the organic light emitting diode display 100 of the present invention, a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn cross each other to correspond to intersection regions thereof. Pixels including organic light emitting diodes (OLEDs) are formed so as to correspond one by one, and a display panel 110 having a plurality of control lines CL1 through CLn and a cell control voltage Vpc controlling driving of each pixel are generated. From the timing controller 130 and the timing controller 130 which control the driving timing of the video data inputted from the system, the timing of supplying the cell control voltage Vpc, A data driver 140 for converting the digital data input through the timing controller 130 according to the data driving control signal DDC to supply the analog data voltage and the reset voltage to the pixels of the display panel 110. The gate driver 150 sequentially supplies scan pulses to the gate lines GL1 to GLn according to a gate driving control signal from the dimming controller 130.

The display panel 110 is formed by crossing a plurality of data lines DL1 through DLm and gate lines GL1 through GLn at right angles, and a pixel including an organic light emitting diode OLED is formed at the intersection. In addition, a plurality of control lines CL1 to CLn are provided on the display panel 110 to receive the cell control voltage Vpc from the cell control voltage generator 120, and the control lines CL1 to CLn are formed in the display panel 110. The pixels are connected to the pixels connected to the gate lines GL1 to GLn, respectively. That is, the first control line CL1 is commonly connected to the pixels connected to the first gate line GL1, and the last control line CLn is commonly connected to the pixels connected to the last gate line GLn.

In response to the cell control signal PDC from the timing controller 130, the cell control voltage generator 120 generates a positive cell control voltage Vpc_rs for reset and a negative polarity for refreshing, as shown in FIG. 3. The cell control voltage Vpc_rf and the cell control voltage Vpc_gn of the ground voltage level 0V for real data are sequentially supplied in units of one horizontal line. That is, the cell control voltage generation unit 120 includes the cell control voltage Vpc_gn of the positive cell control voltage Vpc_rs, the negative cell control voltage Vpc_rf, and the ground voltage level 0V at each pixel positioned on the same horizontal line. Supply sequentially. More specifically, the cell control voltage generator 120 supplies a negative cell control voltage Vpc_rs to one pixel during the reset period RST to reset the pixels, and then, during the refresh period (RFT) to refresh the pixels. The polarity cell control voltage Vpc_rf is supplied, and then the cell control voltage Vpc_gn of the ground voltage level 0V is supplied during the actual data implementation period RDT, which implements the gray scale by supplying the actual data voltage.

In particular, the cell control voltage generator 120 supplies the negative cell control voltage Vpc_rf in units of i horizontal lines among the n horizontal lines to refresh the pixels formed in the i horizontal lines. In this case, the cell control voltage generator 120 supplies the negative cell control voltage Vpc_rf in order from the horizontal line disposed at the top of the i horizontal lines to be refreshed to the lowest horizontal line. The cell control voltage Vpc_rf is supplied during the refresh period (RFT) of the pixels formed on the horizontal line.

For example, in FIG. 4, the negative cell control voltage Vpc_rf is sequentially supplied in units of i horizontal lines among n horizontal lines to refresh pixels formed in the i horizontal lines. That is, when scan pulses are sequentially supplied to the n gate lines GL1 to GLn disposed corresponding to the n horizontal lines, respectively, in the initial state, the cell control voltage generation unit 120 performs the tenth gate line ( The negative cell control voltage Vpc_rf is sequentially supplied from GL10 to the 52nd gate line GL52 to refresh the pixels connected to the 32 gate lines GL10 to GL52 during the refresh period (RFT) of the corresponding horizontal line. Let's do it.

When the 32 horizontal lines having the gate lines GL10 to GL52 arranged in the initial state are refreshed, and the scan pulses are sequentially supplied to the gate lines GL1 to GLn, the cell control voltage generator 120 Instead of supplying the negative cell control voltage Vpc_rf to the 10th gate line GL10, the negative cell control voltage Vpc_rf is sequentially supplied from the 11th gate line GL11 to the 53rd gate line GL53. The pixels connected to the 32 gate lines GL11 to GL53 are refreshed during the refresh period (RFT) of the corresponding horizontal line.

As described above, whenever the scan pulse is sequentially supplied to the gate lines GL1 to GLn, and then sequentially supplied from the first gate line GL1 to the last gate line GLn, the cell control voltage generator 120 changes the horizontal line supplied with the negative cell control voltage Vpc_rf in response to the cell control signal PDC from the timing controller 130. That is, each time the scan pulse is supplied to the gate lines GL1 to GLn again, the cell control voltage generator 120 does not supply the negative cell control voltage Vpc_rf to the first horizontal line of the i horizontal lines. Instead, the negative cell control voltage Vpc_rf is sequentially supplied from the second horizontal line to the horizontal line next to the last horizontal line, so that the horizontal lines to be refreshed are pushed back one by one.

The timing controller 130 receives the video data from the system and supplies the digital data to the data driver 140 and controls the gray level implementation of the data.

The timing controller 130 generates the data drive control signal DDC and the gate drive control signal GDC using the horizontal / vertical synchronization signals H and V from the system according to the clock signal CLK from the system. . The data driving control signal DDC generated as described above is supplied to the data driver 140, and the gate driving control signal GDC is supplied to the gate driver 150. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a source output enable signal SOE, and the gate driving control signal GDC. ) And gate output enable (GOE).

The timing controller 130 generates a cell control signal PDC for controlling the supply of the cell control voltage Vpc and supplies the generated cell control signal PDC to the cell control voltage generator 120. That is, as shown in FIG. 3, the timing controller 130 controls the positive cell control voltage Vpc and the negative cell control during the reset period RST, the refresh period RFT, and the actual data implementation period RDT, respectively. The cell control signal PDC instructing to supply the cell control voltage Vpc of the voltage Vpc and the ground voltage level 0V is supplied to the cell control voltage generator 120.

The data driver 140 converts digital data from the timing controller 130 into an analog data voltage in response to a data driving control signal DDC supplied from the timing controller 130 to supply the pixels to the pixels of the display panel 110. do. Here, the data driver 140 samples and latches digital data supplied through the timing controller 130, and then emits light from the display panel 110 based on the gamma reference voltage supplied from a gamma reference voltage generator (not shown). The diode OLED is converted into an analog data voltage capable of expressing gray scale and supplied to the data lines DL1 through DLm.

In particular, as shown in FIG. 4, the data driver 140 resets the reset data voltage for resetting during one horizontal period 1H when scan pulses are supplied to one horizontal line including one gate line GL. D_rs), a data voltage D_rf of 0V for refreshing, and an actual data voltage D_re implemented in gray scale are sequentially supplied. That is, the data driver 140 resets the reset data voltage D_rs during the reset period RST, which is a supply period of the positive cell control voltage Vpc_rs, in response to the data drive control signal DDC from the timing controller 130. After supplying, the data voltage D_rf of 0 V is supplied during the refresh period RFT, which is the supply period of the negative cell control voltage Vpc_rf, and then the supply period of the cell control voltage Vpc_gn of the ground voltage level 0V. The actual data voltage D_re is supplied during the actual data implementation period RDT.

The gate driver 150 sequentially supplies scan pulses to the gate lines GL1 to GLn in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 130.

5 is an equivalent circuit diagram of each pixel of the organic light emitting diode display according to the first exemplary embodiment of the present invention.

Referring to FIG. 5, each pixel of the organic light emitting diode display according to the first exemplary embodiment of the present invention is turned on by a scan pulse supplied through the gate line GL and supplied through the data line DL. Drive current supplied from a switch transistor S_TR2 for switching a voltage, a storage capacitor Cst2 for charging a data voltage supplied through the switch transistor S_TR2, and a power supply for supplying a high potential power voltage VDD. The organic light emitting diode OLED2 is turned on and emits light, and the driving transistor D_TR2 is turned on by the charging voltage of the storage capacitor Cst2 to drive the organic light emitting diode OLED2.

The switch transistor S_TR2 is an NMOS transistor having a gate connected to the gate line GL, a drain connected to the data line DL, and a source commonly connected to the gate of the storage capacitor Cst2 and the driving transistor D_TR2. . As shown in FIG. 4, the switch transistor S_TR2 is turned on by a scan pulse supplied through the gate line GL during one horizontal period 1H, and stores the data voltage supplied through the data line DL. It is supplied to the gate of the Cst2 and the driving transistor D_TR2.

One side of the storage capacitor Cst2 is connected to the source of the switch transistor S_TR2 and the gate of the driving transistor D_TR2, and the other side thereof is connected to the control line CL to charge the data voltage supplied through the switch transistor S_TR2. do. As shown in FIG. 4, the storage capacitor Cst2 is supplied through the data line DL during the actual data implementation period RDT during one horizontal period 1H in which scan pulses are supplied to the gate line GL. The data voltage D_re is charged.

The organic light emitting diode OLED2 has an anode connected to a power supply for supplying a high potential power voltage VDD and a cathode connected to a drain of the driving transistor D_TR2. The driving transistor D_TR2 is turned on to pass a current to ground. When is formed is driven by the drive current supplied from the power source to emit light.

The driving transistor D_TR2 has a gate connected to the source of the switch transistor S_TR2 and the storage capacitor Cst2, a drain connected to the cathode of the organic light emitting diode OLED2, and a source connected to the gate line GL. It is a MOS transistor. As shown in FIG. 4, the driving transistor D_TR2 is turned off in the actual data implementation period RDT to which the actual data voltage D_re is supplied through the data line DL, and the actual data implementation period RDT has passed. The gate line GL is turned on by the charging voltage to the storage capacitor Cst2 while the scan pulse is not supplied.

The operation of each pixel having such an equivalent circuit will be described in detail with reference to FIG.

During the reset period RST, the positive cell control voltage is preferentially within one horizontal period 1H when the scan pulse is supplied to the gate of the switch transistor S_TR2 and the source of the driving transistor D_TR2 through the gate line GL. Vpc_rs is supplied to the storage capacitor Cst2 through the control line CL, and at the same time, the storage capacitor Cst2 through the switch transistor S_TR2 whose reset voltage D_rs is turned on by the data line DL and the scan pulse. And the gate of the driving transistor D_TR2, the same positive cell control voltage Vpc_rs and the reset voltage D_rs are applied to both ends of the storage capacitor Cst2 during the reset period RST so that the storage capacitor Cst2 is applied. Initialization is performed in which all remaining voltages of N are removed. During the reset period RST, the driving transistor D_TR2 is turned on by the reset voltage D_rs, but since the scan pulse is supplied to the source of the driving transistor D_TR2, the high potential power supplied to the drain of the driving transistor D_TR2. Since the voltage VDD is not switched to the source of the driving transistor D_TR2, the driving transistor D_TR2 is substantially turned off.

As described above, the present invention initializes the storage capacitor Cst2 before supplying the actual data voltage D_re to each pixel, so that any residual image caused by the previous data is removed in the current data implementation, and thus the desired gray scale is implemented. .

During the refresh period (RFT) within one horizontal period (1H) after the reset period (RST), the negative cell control voltage (Vpc_rf) is supplied to the storage capacitor (Cst2) through the control line (CL) and at the same time 0V data. When the voltage D_rf is supplied to the gates of the storage capacitor Cst2 and the driving transistor D_TR2 through the switch transistor S_TR2 turned on by the data line DL and the scan pulse, the control line during the refresh period RFT. Since the negative cell control voltage Vpc_rf supplied to CL is smaller than the voltage of 0 V applied to the gate of the driving transistor D_TR2, the voltage applied to the gate of the driving transistor D_TR2 is applied in the direction to the control line CL and driven. Transistor D_TR2 is turned off.

Thus, the present invention reduces the stress of the driving transistor D_TR2 by performing a refresh to turn off the driving transistor D_TR2 before the actual data supply for one horizontal period 1H, thereby reducing the deterioration of the driving transistor D_TR2. Prevent it.

During the actual data implementation period RDT within one horizontal period 1H after the reset period RST, the cell control voltage Vpc_gn of the ground voltage level is supplied to the storage capacitor Cst2 through the control line CL. At the same time, when the actual data voltage D_re is supplied to the gate of the storage capacitor Cst2 and the driving transistor D_TR2 through the switch transistor S_TR2 turned on by the data line DL and the scan pulse, the actual data implementation period RDT Potential difference occurs across the storage capacitor Cst2 because the cell control voltage Vpc_gn of the ground voltage level supplied to the control line CL is smaller than the actual data voltage D_re supplied through the switch transistor S_TR2. The actual data voltage D_re is charged in the storage capacitor Cst2 and maintained for one frame period.

During the actual data implementation period RDT, the driving transistor D_TR2 is turned on by the actual data voltage D_re, but since the scan pulse is supplied to the source of the driving transistor D_TR2, the high potential supplied to the drain of the driving transistor D_TR2. Since the power supply voltage VDD is not switched to the source of the driving transistor D_TR2, the driving transistor D_TR2 substantially maintains a turn-off state to allow the organic light emitting diode OLED2 to maintain a turn-off state.

In this state in which the actual data voltage D_re is charged to the storage capacitor Cst2, the scan pulse supply is interrupted to the current horizontal line including the driving transistor D_TR2 and is scanned to the horizontal line next to the current horizontal line. When the pulse is supplied, the driving transistor D_TR2 is turned on by the data voltage charged in the storage capacitor Cst2 to form a current path, whereby the organic light emitting diode OLED2 is driven in proportion to the high potential power voltage VDD. It emits light by

 6 is an equivalent circuit diagram of each pixel of the organic light emitting diode display according to the second exemplary embodiment of the present invention.

Referring to FIG. 6, each pixel of the organic light emitting diode display according to the second exemplary embodiment of the present invention is the switch transistor S_TR2, the storage capacitor Cst2, and the organic light emitting diode, similarly to the pixel illustrated in FIG. 5. Although OLED2 and a driving transistor D_TR2 are provided, unlike the pixel shown in FIG. 5, an organic light emitting diode OLED2 is connected between the source of the driving transistor D_TR2 and the data line DL.

That is, in FIG. 6, the organic light emitting diode OLED2 has an anode connected to the source of the driving transistor D_TR2 and a cathode connected to the data line DL.

7 is an equivalent circuit diagram of each pixel of the organic light emitting diode display according to the third exemplary embodiment of the present invention.

Referring to FIG. 7, each pixel of the organic light emitting diode display according to the third exemplary embodiment of the present invention is turned on by a low-level scan pulse supplied through the gate line GL, and then through the data line DL. A power supply for supplying a switch transistor S_TR3 for switching the supplied data voltage, a storage capacitor Cst3 for charging the data voltage supplied through the switch transistor S_TR3, and a high potential power voltage VDD. The organic light emitting diode OLED3 which is turned on by the driving current supplied from the organic light emitting diode OLED and is turned off while being turned off by the charging voltage of the storage capacitor Cst3 and turned on while the data voltage is not supplied to the storage capacitor Cst3. A driving transistor D_TR3 for driving the OLED3 is provided.

The switch transistor S_TR3 is a PMOS transistor having a gate connected to the gate line GL, a source connected to the data line DL, and a drain connected in common to the gate of the storage capacitor Cst3 and the driving transistor D_TR3. .

One side of the storage capacitor Cst3 is connected to the drain of the switch transistor S_TR3 and the gate of the driving transistor D_TR3, and the other side thereof is connected to the control line CL to charge the data voltage supplied through the switch transistor S_TR3. do.

The organic light emitting diode OLED3 has an anode connected to the drain of the driving transistor D_TR2 and a cathode connected to the gate line GL.

The driving transistor D_TR3 is connected to a gate connected to the drain of the switch transistor S_TR3 and the storage capacitor Cst3, a source connected to a power supply for supplying a high potential power voltage VDD, and an anode of the light emitting diode OLED3. It is a P-MOS transistor having a drain.

Meanwhile, in the pixel illustrated in FIG. 7, the organic light emitting diode OLED3 is connected to the driving transistor D_TR3 without connecting the organic light emitting diode OLED3 between the drain of the driving transistor D_TR3 and the gate line GL. It can also be connected between the source and the power supply.

As described above, according to the present invention, the pixel is refreshed before the actual data voltage implemented in gray scale is supplied to the pixel, thereby reducing the stress of the driving transistor of the pixel, thereby preventing deterioration of the driving transistor.

It is to be noted that the technical idea of the present invention has been specifically described in accordance with the above preferred embodiment, but the above-mentioned embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (19)

a display panel in which m data lines and n gate lines cross each other and a pixel including an organic light emitting diode is formed to correspond to the crossing regions one by one, and n control lines are formed; A cell control voltage generator for generating a cell control voltage for controlling initialization, refresh, and data implementation of each pixel and selectively supplying the n control lines to the n control lines; A data driver converting input digital data to supply analog data voltages to the m data lines; And A gate driver sequentially supplying scan pulses to the n gate lines ; During one horizontal period in which scan pulses are supplied to one horizontal line including one gate line, the cell control voltage generator is configured to supply a positive cell control voltage, a negative cell control voltage, and a negative cell control voltage to pixels connected to one control line. An organic light emitting diode display device comprising supplying a cell control voltage of a ground voltage level sequentially. delete The method of claim 1, The cell control voltage generation unit sequentially sequentially the cell control voltage of the positive cell control voltage, the negative cell control voltage, and the ground voltage level during the reset period, the refresh period, and the actual data implementation period, which are sequentially performed within one horizontal period. The organic light emitting diode display device, characterized in that the supply to each pixel. The method of claim 3, wherein And the data driver sequentially supplies a reset voltage, a data voltage of 0V, and an actual data voltage during the reset period, the refresh period, and the actual data implementation period, respectively. 5. The method of claim 4, The cell control voltage generator sequentially supplies the negative cell control voltages in units of i horizontal lines of the n control lines to refresh pixels formed in the i horizontal lines. Device. 6. The method of claim 5, Each time a scan pulse is sequentially supplied to the n gate lines and then sequentially supplied from the first gate line to the last gate line, the cell control voltage generator is the first of i horizontal lines to be refreshed. An organic light emitting diode display, wherein the negative cell control voltage is sequentially supplied from a second horizontal line to a horizontal line located next to the last horizontal line without supplying the negative cell control voltage to a horizontal line. Device. 5. The method of claim 4, Each pixel is A switch transistor turned on by a scan pulse supplied through the gate line to switch the data voltage supplied through the data line; A storage capacitor charging a data voltage supplied through the switch transistor; An organic light emitting diode which is turned on by a driving current supplied from a power source and emits light; And A driving transistor turned on by the charging voltage of the storage capacitor to drive the organic light emitting diode An organic light emitting diode display device comprising a. The method of claim 7, wherein And one side of the storage capacitor is commonly connected to a source of the switch transistor and a gate of the driving transistor, and the other side of the storage capacitor is connected to a control line. 9. The method of claim 8, And the storage capacitor is initialized by the positive cell control voltage supplied through the switch transistor and the reset voltage supplied through a control line during the reset period. 9. The method of claim 8, And the storage capacitor charges the actual data voltage supplied through the switch transistor by the cell control voltage of the ground voltage level supplied to the control line during the actual data implementation period. The method of claim 7, wherein And the driving transistor has a drain connected to the drain of the switch transistor and the storage capacitor, a drain connected to the cathode of the organic light emitting diode, and a source connected to the gate line. The method of claim 11, And the voltage applied to the gate of the driving transistor is removed during the refresh period when the negative cell control voltage is supplied to the control line. The method of claim 11, The driving transistor is turned on by the charging voltage of the storage capacitor while driving the organic light emitting diode while the scan pulse is supplied to the horizontal line next to the current horizontal line including the current horizontal line. An organic light emitting diode display device. An organic light emitting diode display having an organic light emitting diode including m data lines and n gate lines corresponding to each other and corresponding to each of the crossing regions is formed, and n control lines are formed. In the driving method, Generating a cell control voltage for controlling initialization, refresh, and data implementation of each pixel and selectively supplying the n control lines; Converting input digital data to supply an analog data voltage to the m data lines; And Sequentially supplying scan pulses to the n gate lines; In the cell control voltage supply step, During one horizontal period in which scan pulses are supplied to one horizontal line including one gate line, cell control of the positive cell control voltage, the negative cell control voltage, and the ground voltage level is applied to the pixels connected to one control line. A method of driving an organic light emitting diode display, characterized in that the supply of a voltage sequentially. delete 15. The method of claim 14, In the cell control voltage supply step, Sequentially supplying the positive cell control voltage, the negative cell control voltage, and the cell control voltage of the ground voltage level to the pixels during the reset period, the refresh period, and the actual data implementation period, which are sequentially performed within one horizontal period. A method of driving an organic light emitting diode display device. 17. The method of claim 16, In the data voltage supply step, And a reset voltage, a data voltage of 0V, and an actual data voltage are sequentially supplied during the reset period, the refresh period, and the actual data implementation period, respectively. 18. The method of claim 17, In the cell control voltage supply step, And sequentially supplying the negative cell control voltages in units of i horizontal lines of the n control lines to refresh the pixels formed in the i horizontal lines. The method of claim 18, In the cell control voltage supply step, Each time a scan pulse is sequentially supplied to the n gate lines and then sequentially supplied from the first gate line to the last gate line, the negative polarity is applied to the first horizontal line of the i horizontal lines to be refreshed. And supplying the negative cell control voltage sequentially from a second horizontal line to a horizontal line located next to the last horizontal line without supplying a cell control voltage.

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