KR101313885B1 - Electronic device array - Google Patents

Abstract

As a method of manufacturing an array of electronic devices,

Forming at least one first conductive element of the first electronic device on the substrate and at least one second conductive element of the second electronic device on the substrate;

The first and second conductivity to provide a first channel for the movement of charge carriers between the conductive elements of the first electronic device and a second channel for the movement of charge carriers between the conductive elements of the second electronic device. Forming a channel material layer on the devices and the substrate;

Using irradiative techniques to reduce the conductivity of at least one selected portion of the channel material layer in at least one regions between the first and second conductive elements by one step. An electronic device array manufacturing method.

Description

Electronic device array {ELECTRONIC DEVICE ARRAY}

TECHNICAL FIELD The present invention relates to a technique for manufacturing an array of electronic devices, in particular a method of patterning a semiconductor layer in the manufacture of an array of electronic devices, such as semiconducting polymer thin-film transistors (TFTs). , But is not limited to such.

Semiconducting conjugated polymer TFTs are inexpensive logic circuits integrated on plastic substrates (C. Drury, et al., APL 73, 108 (1998)) and pixel transistor switches and optoelectronic integrated devices in high resolution active matrix displays. (H. Sirringhaus, et al., Science 280, 1741 (1998), A. Dodabalapur, et al. Appl. Phys. Lett. 73, 142 (1998)). In test devices composed of polymer semiconductors, inorganic metal electrodes and gate dielectric layers, high performance TFTs have been used. The charge carrier mobility is 0.1 cm ² / Vs and the on / off current ratio is 10 ⁶ -10 ⁸ , which is similar to the performance of amorphous silicon (H. Sirringhaus, et al., Advances in Solid State Physics 39, 101 (1.999)).

Thin device-quality films of conjugated polymer semiconductors can be formed by coating the polymer solution on an organic solvent onto a substrate. The technique is therefore ideally suited for low cost, wide range of solution processes compatible with flexible plastic substrates.

Organic TFT applications are prone to leakage of current between elements in the device, such as charged pixels and logic gate elements. For many TFT applications the active semiconducting layer needs to be isolated between the devices as a result. This is essential to reduce electrical crosstalk and to eliminate parasitic leakage currents between adjacent devices. Even if the semiconducting material is not doped, the leakage current through the semiconducting layer can be significant, especially for circuits consisting of high packing density transistors, such as high resolution active matrix displays. .

In an active matrix display, metal interconnects for pixel addressing are deposited so that they are located across the display. If a semiconducting material is present under such interconnect lines, parasitic TFT channels can form in the layers below the interconnect lines, generating a negligible leakage current between the pixels. This leakage can degrade device performance. As a result, if a blanket unpatterned layer of semiconductor is coated over the entire panel, patterning of the layer is required.

The semiconductor can be deposited in this form by spin-coating a solution processable semiconductor such as F8T2, or by evaporative deposition of other semiconductors such as pentacene. However, even in the undoped semiconducting layers in both of the cases mentioned above, the semiconductor material between the elements in the device and the regions under the gate interconnects will be electrically activated when the gate is activated.

Ideally, the patterning method for the semiconductor should be digitized, for example for distortion correction over a wide area panel in making large flexible displays. As a result, processes such as shadow masking and pentacene for the application of semiconductors are inadequate for wide-area semiconductor patterning because no distortion correction is possible for a given mask.

One method of patterning solution processable semiconductors is to do it only where needed, for example by inkjet printing the semiconductor directly into the channel region of the transistor. This is an example of a digital process and adds to the benefits of effective use of semiconductor materials. The final resolution achievable with such a process can be limited due to the spreading of drops of deposited semiconductor on the substrate surface. Another problem with such a process is that the droplet diffusion is determined by the surface on which it is printed, so that the substrate material cannot be easily changed without considering the effect on the semiconductor patterning step. This reduces the selection of available substrates. Direct-write printing techniques for patterning semiconductive layers from solution, such as offset or screen printing, are similar issues.

Photolithography can also be used to pattern the active semiconductor layer (Gerwin. H. Gelinck et. Al., Nature Materials 3, 106-110 (2004)). However, photolithography requires several processing steps and can cause degradation of the organic semiconductor material due to the chemical interaction between the semiconductor and the resist chemicals / solvents, and high registration with predeposited patterns. registration is difficult to perform on flexible substrates that are unstable in size when accuracy is required over a wide substrate area. For example, US patent US6803267 describes a method of making an organic memory device associated with a multi-step technique for patterning organic semiconductor materials. The multi-step technique deposits silicon-based resist on the organic semiconductor, irradiating portions of the silicon-based resist, patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist, and Patterning the exposed organic semiconductor and stripping the non-spun silicon-based resist.

It is an object of the present invention to provide an alternative method of patterning the panel material that at least partially solves the above mentioned problems in the manufacture of an array of electronic devices.

According to a first aspect of the invention, a method is provided for manufacturing an array of electronic devices, the method comprising forming one or more first conductive elements of a first electronic device on a substrate, as well as a second on the substrate. Forming one or more second conductive elements of the electronic device; And to provide a first channel for the movement of charge carriers between the conductive elements of the first electronic device in use and to provide a second channel for the movement of charge carriers between the conductive elements of the second electronic device in use. Forming a layer of channel material made of a channel material over the substrate and the first conductive elements and the second conductive elements, the method further comprising: between the first conductive elements and the second conductive elements (A) using an irradiative technique to reduce the conductivity of one or more selected portions of the layer of channel material in one or more regions of a single step.

In one embodiment, step (a) comprises using an irradiation technique to reduce the conductivity of the one or more selected portions by removing the one or more selected portions of the channel material layer in a single step, in which case the step (a) is performed without irradiating any portions of the layer of channel material overlying the first conductive element and the second conductive element.

In one embodiment, the channel material is a semiconductor material.

In one embodiment, the step (a) comprises the one or more selected portions of the channel material layer between the first conductive elements and the second conductive elements, and / or the one of the channel material layer. Using the irradiation technique to generate heat locally at each portion of the substrate underlying the selected portions above, wherein the heat is photothermal and / or photochemical of the channel material. (photochemical) induces a denaturing process and also reduces the conductivity of the one or more selected portions of the channel material layer.

In one embodiment, step (a) comprises etching the portions of the channel material using ultraviolet laser radiation.

In one embodiment, the one or more selected portions in step (a) comprise one or more lines extending substantially perpendicular to a direction between the first conductive elements and the second conductive elements.

In one embodiment, forming a pair of first conductive elements and a pair of second conductive elements on the substrate, wherein the channel material layer is formed between the pair of first conductive elements. In addition to providing one channel, the second channel is provided between the pair of second conductive elements.

In one embodiment, the selected portions of the channel material layer are spaced apart from the first channel and the second channel by at least 10 micrometers, in particular by at least 50 micrometers.

In one embodiment, the selected portions of the channel material layer are spaced apart from the first conductive elements and the second conductive elements by at least 10 micrometers, in particular by at least 50 micrometers.

In one embodiment, the first pair of conductive elements form a source electrode and a drain electrode of a first field effect transistor device, and the second pair of conductive elements are a source of a second field effect transistor device An electrode and a drain electrode are formed.

In one embodiment, the one or more selected portions in step (a) comprise a series of at least two lines extending continuously below the gate line.

In one embodiment, the method comprises the steps of (b) forming a dielectric layer over the substrate, the first conductive elements, the second conductive elements, and the channel material layer; And (c) forming a gate line extending over each of the first channel and the second channel.

In one embodiment, the field effect transistors are normally-off field effect transistor devices, and the one or more selected portions of step (a) comprise portions below the gate line.

In one embodiment, the one or more selected portions in step (a) comprise a series of at least two lines extending continuously below the gate line.

In one embodiment, the gate line has a width, and the one or more selected portions of step (a) include one or more lines extending at least the width of the gate line.

In one embodiment, the first electronic device and the second electronic device are normally-on field effect transistor devices, and the one or more selected portions of step (a) are below the gate line. Portions i) and portions ii not below the gate line.

In one embodiment, the one or more first conductive elements comprise a pixel electrode having a plurality of sides, and the one or more selected portions in step (a) are each of the surfaces of the pixel electrode. One or more lines extending along.

In one embodiment, the step (a) includes directing one or more laser beams to respective portions of the substrate located at or below the one or more selected portions of the channel material layer. Focusing at one or more points in position.

In one embodiment, the selected portions of the channel material layer do not form a closed path around the first electronic device and / or the second electronic device.

In one embodiment, etching the channel material also etches a portion of the material of the substrate.

According to another aspect of the invention, an array of electronic devices is provided, the array of electronic devices comprising at least one first electronic device and a second electronic device on a substrate, the first electronic device and Each of the second electronic devices includes a patterned channel material layer, the patterned channel material layer also defining one or more conduction paths between the first electronic device and the second electronic device when in use. Wherein the pattern of the channel material layer has a factor of at least 50% of the shortest conducting path between the first electronic device and the second electronic device than the shortest physical distance between the first electronic device and the second electronic device. As long as it is formed.

According to another aspect of the invention, an array of electronic devices is provided, the array of electronic devices comprising at least one first electronic device and at least one second electronic device on a substrate, wherein the first Each of the electronic device and the second electronic device includes a patterned channel material layer, the channel material layer consisting of channel material, and the first electronic device over at least a portion of the patterned channel material layer. Wherein the patterned channel material layer defines one or more conducting paths between the first electronic device and the second electronic device in use, wherein the patterned channel material layer also includes a gate electrode extending over a portion of the second electronic device. At least a portion of each of the one or more conducting paths is located before the gate Passes through the channel region of the patterned material layer is not already present.

In one embodiment, the pattern of channel material is defined by laser etching of the channel material, and the step of laser etching is a conductive element of the first electronic device and the second electronic device predefined on the substrate. Any portion of the layer of channel material overlying the field is performed without etching.

According to another aspect of the invention, there is provided a display or memory device comprising an array of electronic devices as described above.

The electronic device array may include two devices and on the other hand may include a custom array of hundreds or thousands of devices.

In one embodiment, laser etching is used to form trenches in the semiconductor layer and even in the substrate surface on which the semiconductor layer is formed.

In many cases the substrate on which the semiconducting layer is deposited already comprises a pattern of metal electrodes, for example an electrode or an array of interconnects. The semiconductor material laser patterning process with direct contact with the conductive material layer can be difficult. This is because the process window is defined by the etching threshold difference between the conductive material and the semiconductor material. The etching threshold for the conductive material may be similar to the threshold of the semiconductor material at a given laser wavelength (UV). As a result, situations can occur where there are few or no process windows. This is an important issue, especially in flexible substrates. The substrate may also be etched, and the adhesion of the conductive material to the substrate may not be very strong. In such a case, the conductive layer is removed from the substrate together with the semiconducting layer during the etching step which causes rupture in the conductive lines. In one embodiment of the invention, the semiconductor is etched only where the semiconductor is in direct contact with an insulating substrate material as opposed to those areas where the semiconductor is in contact with the conductive layer. The critical gap of the unpatterned semiconductor remains in the periphery of the underlying conductive layer. Electrically, the partial insulation scheme does not have to cause any insulation problems because the areas where the semiconductor material is in direct contact with the conductive layer are electrically shorted along the lines of the conductive material.

Embodiments of the present invention relate to techniques and designs in which highly effective suppression of leakage currents can be achieved in spite of only partial insulation of semiconducting active layer islands, around the conductive electrodes Leakage current flowing through the unpatterned region of the semiconductor can be minimized.

In an embodiment of the present invention, laser induced degradation of the electrical properties of the device using the semiconductive material remaining on the substrate after etching as the active layer can be avoided.

Embodiments of the present invention provide a high resolution, high yield digital process, while providing excellent suppression of leakage current between the elements within the devices. In addition, distortion correction techniques allow large areas to be processed. This enables direct write patterning of the semiconductor layer without requiring additional processing steps.

Embodiments of the present invention relate to the patterning of semiconductor devices through a laser etching process, which eliminates parasitic leakage currents and electrical crosstalk between adjacent devices and insulates the device.

One embodiment of the invention involves laser etching the semiconductor layer material to insulate adjacent devices.

One embodiment of the invention etches the semiconductor material and also the substrate material as needed but maintains a minimum distance from any underlying conductive layers.

Another embodiment of the present invention also etches the semiconductor material and, if necessary, the substrate material but maintains a minimum distance from any active device region.

Yet another embodiment of the present invention then involves etching the semiconductor material only in the substrate regions located under the electrode to be deposited.

One embodiment relates to patterning organic semiconducting materials. The semiconductor layer may be patterned by selecting a substrate that absorbs a desired laser wavelength to etch the semiconductor material. Upon exposure to the laser beam, the substrate material is etched in the exposed area. This will remove the irradiated substrate material and the semiconductive material in the area immediately above it in the upper layer. In this case, there is no limitation on the type of semiconductive material that can be selected.

BRIEF DESCRIPTION OF DRAWINGS To help understand the present invention, specific embodiments thereof will now be described by way of example only with reference to the accompanying drawings.

1 illustrates a method of isolating a device by patterning a semiconductor material using a laser ablation method in accordance with an embodiment of the present invention.

2 shows the location of unwanted leakage paths that may exist under the gate region in a normally-off device when the gate is activated.

3 illustrates an embodiment of the invention patterning a semiconductive material around a pixel structure when the semiconductor device is of positive threshold p-type (or negative threshold n-type). The schematic method is shown.

4 shows an optical micrograph of the surface view of a device measured with an Atomic Force Microscope (AFM) immediately after the semiconductor etching process step in accordance with an embodiment of the present invention.

FIG. 5 shows a tapping-mode AFM height image taken over the etched trench region of the device shown in FIG. 4.

FIG. 6 shows an optical photograph immediately after gate electrode lines are deposited following an etch patterning step of the lying semiconductor layer in accordance with an embodiment of the present invention.

7 shows typical TFT characteristics for a patterned semiconductor device in comparison with those of unpatterned semiconductor devices in accordance with an embodiment of the present invention.

8 illustrates examples of patterning a semiconductor layer in accordance with an embodiment of the invention. The minimum lateral separation between the semiconductor trench and the source or drain electrodes shown in FIG. 8B is no more than half the minimum of the lateral separation shown in FIG. 8A.

9 shows three transfer curves for patterned devices using two different designs (FIGS. 9A and 9B) with a sample without semiconductor patterning 9c. The comparison is shown.

Referring to the drawings, a first embodiment of the present invention is shown in FIG. 1 in connection with an array of top gate TFTs for applications such as active matrix displays. In order to fabricate an electronic device with optimal display front-of-screen performance using organic semiconducting material for the TFT, patterning the material of the semiconducting layer and insulating adjacent devices It is essential. This is done by a laser patterning process. This process is only used where there is no conductive source-drain layer, to remove the substrate material if necessary. In this way, parasitic TFTs can be removed by insulating the devices.

The substrate 1 is coated with a thin conductive layer 2. The substrate may be a rigid substrate such as glass or a flexible substrate such as, but not limited to, a plastic film comprising polyethylene terephtalate (PET). The first conductive layer 2 is preferably deposited with an inorganic metal layer such as gold or silver. Alternatively, organic conductive polymers such as polyethylenedioxythiophene doped with polystyrene sulfonic acid (PEDOT / PSS) can be used. The conductive layer may be a solution processing technique such as spin, dip, blade, bar, slot-die, or spray coating, inkjet ), By gravure, offset or screen printing, or by vacuum deposition, such as evaporation or preferably sputtering techniques. The preferred conductive layer is patterned to form source and drain electrodes 2 by processes such as, but not limited to, photolithography or laser etching. The conductive layer can also be patterned by direct write printing techniques such as inkjet printing. For display applications the metal layer is patterned to form a periodic array of TFT source drain electrodes, and data is interconnected with a pitch in two directions determined by the display resolution.

Once the metal layer is patterned to form source / drain electrodes, a semiconductive material layer 3 can be deposited on the substrate. The semiconducting material is polyarylamine, polyfluorene, or poly-dioctyllfluorene-co-bithiophene (F8T2) or (poly (9, 9'-dioctylfluorene-co) polythiophene derivatives such as -bis-N, N '-(4-butylphenyl) diphenylamine) (TFB)). Inkjet printing, soft lithographic printing (JA Rogers et al., Appl. Phys. Lett. 75, 1010 (1999); S. Brittain et al., Physics World May 1998, p. 31), screen printing (Z. Bao, et al., Chem. Mat. 9, 12999 (1997)), offset printing, blade coating Or a wide variety of deposition techniques such as dip coating, curtain coating, meniscus coating, spray coating, or extrusion coating to deposit the semiconducting material. It can be used to The semiconductor is preferably spin coated onto the substrate for coating to a thickness of ˜50 nm after solvent evaporation. In addition, an evaporation process can also be used. Another preferred technique of the invention is an inkjet printing technique. If the layer is inkjet printed, a minimum amount of semiconductor material may be used. This has an environmental and economic advantage.

The active semiconducting layer is then patterned such that the devices are isolated from each other. This is essential to eliminate parasitic leakage currents between adjacent devices and to reduce electrical crosstalk. The semiconductor layer is patterned using a pulsed laser beam 4, the wavelength of the pulsed laser beam 4 being the wavelength absorbed by the semiconducting material layer and, if subsequent etching is needed, also by the substrate. It is the wavelength that can be absorbed. The semiconductive material is exposed to the laser beam only in the region where the metal layer is not present. This is due to the fact that any exposure of the area containing the metal to the laser beam can cause etching of the metal material.

The etching allows the 248 nm KrF excimer laser (Lumonics PM800) to focus on a substrate through a mask pattern in a step and repeat process to provide the necessary semiconductor pattern. In deliberate overdosing, a two-shot process is used, with each shot irradiated with a fluence of 650 mJ / cm ² . In addition, depending on the absorption characteristics of the semiconductive material, a 308 nm laser beam or other suitable wavelength may be used. Etching into the semiconductor material 3 takes place through hermal and stress confinement effects from the localized photon flux. The areas of the substrate 1 can be etched during this process if necessary. The source and drain electrodes are now electrically insulated with respect to adjacent source / drain electrodes. This process proceeds to produce a limited amount of debris.

The semiconductor need not be patterned in the entire perimeter of the pixel for two different reasons.

Patterning the semiconductor material over its entire periphery will allow the semiconductor to be patterned on thin gold wires connecting the pixel to the integrated TFT region below it. However, this is unnecessary because all of the semiconductor material on the gold material will be shorted by the gold. In addition, attempts to pattern the semiconductor over underlying gold materials may remove the gold while destroying the connectivity.

Minimizing the patterning will minimize the fragments, which is particularly significant near the integrated TFT area.

Thereafter, the gate dielectric layer 5 and the gate electrode and interconnects 6 are deposited. Single or multiple dielectric materials 5 are deposited on the patterned semiconducting layer onto the substrate. Materials such as polyisobutylene or polyvinylphenol can be used for the dielectric layer, but preferably polymethylmethacrylate (PMMA) and polystyrene are used. The dielectric material may be deposited in the form of a continuous layer by techniques such as but not limited to spray or blade coding. However, preferably spray coating techniques are used.

Deposition of the gate electrode 6 and interconnect lines takes place after the deposition of the dielectric material layer. The gate electrode may be a conductive polymer such as PEDOT / PSS or printable inorganic nanoparticles of gold or silver. The gate electrode may be deposited using techniques such as sputtering or evaporation techniques or solution processing techniques such as spin, dip, blade, bar, slot die, gravure, offset or screen printing. Preferably, the gate electrode is deposited by ink jet printing.

If the semiconductor device is not doped or normally off (negative turn-on voltage in the case of a p-type TFT), i.e., does not conduct electricity in any non-gate region of the structure, removal of the semiconductor is primarily the gate. And under the gate interconnect. This is because when the gate is activated, all semiconductors under the gate interconnection region become conductive and create unwanted parasitic leakage paths between the filled pixel and other source or drain regions associated with other pixels.

2 shows the location of unwanted leakage paths that exist under the gate area when the gate is activated. The noticeable leakage between the drain electrode 8 of one TFT and the pixel electrode 9 of adjacent pixels will be below the gate interconnect 10. It is the semiconductor at these locations where trench patterning 11 is most effective to prevent inter-pixel leakage. Patterning the remainder of the semiconductor material provides little benefit over normally off semiconductors since the normally off semiconductors are never activated.

For normally on (positive turn-on voltage in the case of p-type TFT) semiconductor devices, it is better to pattern as much of the surroundings as possible without damaging the interconnect between the pixel and the TFT. Care should be taken not to damage the interconnection between the pixel and the TFT so that some leakage paths appear from the pixel electrode to the other adjacent TFTs, but the leakage path length can be increased significantly, resulting in reduced conductivity of the path. To reduce pixel crosstalk.

3 schematically illustrates a possible method of patterning a pixel structure when the semiconductor device is normally on, even when current leakage occurs even in the non-gate region of the pixel. The metal source / drain pixel electrode structure 12 is shown along the region 13 from which the other entire semiconductor layer has been removed. If no semiconductor patterning has been performed, there will be a large amount of interpixel leakage. However, by only patterning the semiconductor material as shown, only one leakage path 14 remains that allows charge to be transferred from one pixel 23 to another pixel electrode or source line 22. However, the aspect ratio of this leakage path is in the range of 10 to 20 times lower than in the case of unpatterned semiconductor material. Some current will be lost from the pixel electrode to the source line (although less than before) but this will not contribute to pixel crosstalk.

The semiconductor material defines a conduction path such that charge escapes the pixel electrode 23 to adjacent pixel electrodes or adjacent source lines 22. By patterning the semiconductive material in the manner shown in FIG. 3, there is no complete isolation of the active semiconducting material in the channel of a particular transistor from the surrounding devices (the semiconducting material from the closed loop region surrounding any device). As achieved by removal). That is, there is still a conduction path between adjacent devices. This requires the minimum distance of the laser etched area to any underlying electrode structure to be maintained in order to avoid degradation of the underlying metal pattern during the step of laser etching. Full insulation of the semiconductive active layer is possible with the photolithographic patterning method, but for laser etching, it will cause serious damage to the predefined metal layers and interconnects in the underlying layers. However, the length of such conduction paths between any two transistors is considerably longer than the linear distance between these transistors. Preferably, the step of semiconductor patterning increases the conduction path by at least 50%.

Preferably the patterning of the semiconducting layer is such that any such conduction paths do not pass through the gate electrode or gate level interconnects, i. Pass the substrate region that is not formed in such regions.

In the first embodiment the semiconductor layer and the laser wavelength are selected such that a semiconductive material strongly absorbs the laser radiation. Preferably, the laser is an ultraviolet laser, such as an excimer laser, absorbed by individual functional groups of organic semiconducting material. Alternatively, visible or infrared lasers can be used to be absorbed by a particular oscillation mode or π-π band gap transition of the organic semiconductor.

Alternatively, in the second embodiment the semiconductor material layer can be patterned by selecting a substrate that absorbs at the laser wavelength used to etch the semiconductor. Upon exposure to the laser beam, the substrate material is etched in the exposed areas, and the material in the semiconducting layer above these areas is also removed. In this case, there is no limit to the type of semiconducting material that can be selected.

According to the second embodiment, the substrate 1 is coated with a thin conductive layer 2. The substrate is selected such that the laser beam used to etch the layer of semiconductor material is absorbed by the substrate. In particular, plastic substrates can be used to absorb the wavelengths used during etching. The substrate may also be coated with an insulating dielectric overlayer that is deposited to absorb the laser radiation. Such overlayers may also include a dye selected to provide strong absorption at the wavelength of the laser. Preferably a first conductive layer 2 is deposited on which an inorganic metal layer, such as gold or silver, is deposited. Alternatively, organic conductive polymers such as PEDOT / PSS can be used. The conductive layer is deposited by evaporation or preferably by vacuum deposition such as sputtering techniques or using solution processing techniques such as spin, dip, blade, bar, slot die or spray coating, inkjet, gravure, offset or screen printing. . Preferred conductive layers are patterned to form source / drain electrodes 2 by processes such as, but not limited to, photolithography or laser etching. The conductive layer can also be patterned by direct write printing techniques such as inkjet printing. For display applications the metal layer is patterned to form a data array with a periodic array of TFT source / drain electrodes and a pitch in two directions defined by the display resolution.

Once the metal layer is patterned to form source / drain electrodes, a semiconducting material layer 3 is deposited on the substrate as described above. However, since the etching method depends on the substrate used rather than the current semiconductor material, there is no limit to the type of semiconductor that can be deposited. As mentioned above, a wide range of printing techniques that can be used to deposit selected semiconducting materials include, but are not limited to, ink jet printing, soft lithographic printing (JA Rogers et al., Appl. Phys. Lett. 75, 1010 (1999); S. Brittain et al., Physics World May 1998, p. 31), screen printing (Z. Bao, et al., Chem. Mat. 9, 12999 (1997)), offset printing, blates Coating or dip coating, curtain coating, meniscus coating, spray coating, extrusion coating, etc. Preferably, spin coating on the substrate for coating to a thickness of -50 nm after solvent evaporation. Another preferred technique for the present invention is an ink jet printing technique, if the layer is ink jet printed, a minimum amount of semiconductor material can be used, which is environmentally and economically beneficial. .

The semiconductor layer is then patterned using a laser pulse 4 at a wavelength absorbed by the substrate material layer. The substrate material is exposed to the laser beam only in areas where the first layer of conductive material is not present. This is due to the fact that any exposure to the laser beam in the area containing the underlying conductive material can result in metal etching.

The etching takes place in a step and repeat process by focusing a 248 nm KrF (Lumonics PM800) or 308 nm XeCl excimer laser onto the substrate through a mask pattern to provide the required pattern. Compared to semiconductor materials, the range of lasers that can be used is larger because larger ranges of wavelengths can be used to etch substrate materials. In a deliberate overdosing scheme, a two-shot process was used for each shot of 650 mJ / cm ² fluence. The laser beam may be focused on the substrate surface. The method etches the semiconductor material above the same step as the substrate material. The source / drain regions are now insulated with respect to adjacent source / drain electrodes. This process has the advantage that the semiconductor material can be easily changed from others without having to adjust the etching process parameters.

Subsequently, the gate dielectric layer 5 and the gate electrode and interconnect 6 are deposited. Single or multiple dielectric materials 5 are deposited on the substrate covered with a patterned semiconducting layer. Materials such as polysobutylene or polyvinylphenol can be used as the dielectric layer, but preferably polymethylmethacrylate (PMMA) and polystyrene are used. The dielectric material may be deposited in the form of a continuous layer by techniques such as but not limited to spray or blade coating. However, preferably spray coating techniques are used.

 Deposition of the dielectric material layer is followed by deposition of the gate electrode 6 and interconnect lines. The gate electrode may be a conductive polymer such as PEDOT / PSS or printable inorganic nanoparticles of silver or gold. The gate electrode is deposited using solution processing techniques such as spin, dip, blade, bar, slot die, gravure, offset or screen printing or techniques such as evaporation or sputtering. Preferably, the gate electrode is deposited by ink jet printing.

Figure 4 shows an optical picture of the surface state of the device measured by AFM immediately after the semiconductor etching process. The optical photograph shows a laser etch trench 15 fabricated around the device pixel. Semiconductor etching is particularly effective in the region where the gate lines pass. Etching the substrate region beyond which the gate lines pass is less effective, and not doing so may reduce the formation of debris.

A tapping-mode AFM height photograph is shown in FIG. 5. This picture is taken of the trench region 15 etched in FIG. 4. The photo shows that in this experiment, the 20 μm side trench has a depth of about 300 nm. This value is larger than the thickness of the semiconductor layer, which in this case was 50 nm. This overdosing scheme ensures isolation of the semiconductor. However, the process can be used at significantly lower fluences, which can result in shallower trenches, fewer fragments and higher process yields. This is due to the fact that the laser beam area can be significantly expanded. Experiments suggest that a fluence of 100 mJ / cm ² will be sufficient to etch only the semiconductor layer.

6 shows an optical photograph measured by AFM immediately after deposition of the gate electrode. The optical photograph shows a laser etched trench 16 made around a device pixel on which slightly different semiconductor patterns are made. The optical photograph shows the positions of the two parasitic TFTs 18 removed by patterning the gate electrode 17 and the semiconductor.

The TFT characteristics are measured and viewed so that they are not damaged by the semiconductor patterning step. However, even with the high fluence used in these experiments, the 'debris-affected zone' (DAZ) and the heat-affected zone (HAZ) are less than 50 μm, forming limited debris. Has The above mentioned areas are quite small, and if lower fluence is used for the optimal process, it is expected to be 10 μm area.

FIG. 7 shows typical TFT characteristics for the semiconductor patterning step shown in FIG. 4. No reduction is observed compared to the unpatterned semiconductor device in TFT performance.

8 shows different examples of how the semiconductor can be patterned. In Fig. 8A, the semiconductor is patterned very close to the TFT. The minimum lateral spacing of the source / drain of the semiconductor trench and the TFT is 20 um (part shown by the dotted circle). The total area of semiconductor patterning is about 37000 (um) ² . In a second example of a patterning scheme (FIG. 8B), the minimum lateral spacing between the semiconductor trench and the source / drain is 60 μm, and the total area of material removed is 17000 (um) ² . This is less than half of that in FIG. 8A. Both designs were fabricated and the semiconductor was patterned with the same overdose as before (650 mJ / cm ² ). The on-current of the semiconductor for the design of FIG. 8A shows a 10-fold degradation when compared to the design in FIG. 8B. The design in FIG. 8B shows no degradation compared to the unpatterned semiconductor sample.

FIG. 9 shows three transfer curves for devices patterned using two different designs (FIGS. 9A and 9B) compared to a sample with non-semiconductor patterning (FIG. 9C). The 'on' current of the TFT with the most accurate patterning is lowered by 10 times and the transconductance is correspondingly lowered.

This shows that, in this particular (high) fluence case, a degradation region exists around the patterned semiconductor, and its radius is greater than 20 um and less than 60 um. The degradation zone is believed to be due to debris and thermal damage occurring around the etched portion. If proper spacing between the TFT and semiconductor trenches is maintained, there will be no device degradation even at high fluences of 650 mJ / cm ² . The size of the degradation region will be much smaller at low fluences without compromising the device isolation level.

The processes and devices described herein are not limited to devices made of solution processing polymers. For example, some of the conductive electrodes and / or interconnections (see below) of a TFT in a circuit or display device may be, for example, electroplated onto a pre-patterned substrate or in a colloidal suspension. It may also be formed from inorganic conductors that can be deposited by a print of < RTI ID = 0.0 > In devices where not all layers are deposited from solution, at least one PEDOT / PSS portions of the device may be replaced with an insoluble conductive material such as a vacuum deposited conductor.

Examples of possible materials that can be used in the semiconducting layer include any solution treatable conjugated poly that exhibits suitable field effect mobility above 10 ⁻³ cm ² / Vs and preferably above 10 ⁻² cm ² / Vs. It includes polymeric or oligomeric materials. Materials that may be suitable are described, for example, in HE Katz, J. Mater. Chem. 7, 369 (1997), or Z. Bao, Advanced Materials 12, 227 (2000). Other possibilities include small conjugated molecules with solubilising side chains (JG Laquindanum, et al., J. Am. Chem. Soc. 120, 664 (1998)), self-assembled semiconducting organic-inorganic from solution Solutions such as hybrid materials (CR. Kagan, et al., Science 286, 946 (1999)) or CdSe nanoparticles (BA Ridley, et al., Science 286, 746 (1999)) or inorganic semiconductor nanowires Deposited inorganic semiconductors.

The electrodes can be patterned by any technique, including but not limited to photolithography, laser etching or direct write printing. Suitable techniques include soft lithographic printing (J.A. Rogers et al., Appl. Phys. Lett. 75, 1010 (1999); S. Brittain et al., Physics World May 1998, p. 31), screen printing ( Z. Bao, et al., Chem. Mat. 9, 12999 (1997)), and photolithographic patterning (see WO99 / 10939), outlet printing, flexographic printing or other graphic art printing Technology, embossing or imprinting techniques.

Although preferably all layers and components of the device and circuit are deposited and patterned by solution process and printing techniques, at least one component is patterned by photolithography processes or subjected to vacuum deposition techniques. Is deposited by.

Devices such as TFTs manufactured as described above may be part of more complex circuits or devices in which at least one such devices may be integrated with each other and / or with other devices. Examples of applications are active matrix circuitry and logic circuitry or user defined gate array circuitry for display or memory devices.

 As described above, patterning processes may be used to pattern other circuit components such as, but not limited to, interconnects, registers, capacitors.

The invention is not limited to the examples described above. Aspects of the invention include all novel and progressive aspects of the concepts described herein and combinations thereof.

The Applicant hereby expresses, from the point of view of the person skilled in the art, each individual feature and combination of two or more such features described herein, without limitation of the claims, and without limitation of the claims set forth herein. On the basis of the present invention, the disclosure extends to features and combinations that can be implemented entirely. The Applicant can make up aspects of the invention to any such individual feature or combination of features. In view of the above description, it will be apparent to those skilled in the art that various changes may be made within the scope of the present invention.

Claims (37)

A method of manufacturing an array of electronic devices, Forming one or more first conductive elements of the first electronic device on the substrate as well as forming one or more second conductive elements of the second electronic device on the substrate; And The substrate to provide a first channel for the movement of charge carriers between the conductive elements of the first electronic device in use and to provide a second channel for the movement of charge carriers between the conductive elements of the second electronic device in use. And forming a channel material layer of channel material on the first conductive elements and the second conductive elements. The method also includes irradiation techniques for reducing the conductivity of one or more selected portions of the channel material layer in one or more regions between the first conductive elements and the second conductive elements in a single step. (a) using an irradiative technique, The first electronic device is a first field effect transistor device, the second electronic device is a second field effect transistor device, the channel material is an organic semiconductor channel material, and the first conductive elements are the first field effect transistor. Forming a source electrode and a drain electrode of the device, wherein the second conductive elements form a source electrode and a drain electrode of the second field effect transistor device, and step (a) etches the selected portions of the channel material layer. Wherein the method also comprises: (B) forming a dielectric layer over the substrate, the first conductive elements, the second conductive elements, and the channel material layer; And (C) forming a gate line extending over each of the first channel and the second channel. delete The method of claim 1, And said step (a) is performed without irradiating any portions of said layer of channel material overlying said first conductive element and said second conductive element. delete delete delete The method of claim 1, Etching the portions of the channel material uses ultraviolet laser radiation. The method of claim 1, Wherein said one or more selected portions in step (a) comprise one or more lines extending substantially perpendicular to a direction between said first conductive elements and said second conductive elements. How to manufacture. delete The method of claim 1, And wherein the region with the selected portions of the channel material layer is spaced at least 10 micrometers from the first channel and the second channel. The method of claim 1, And said selected portions of said channel material layer are spaced at least 50 micrometers from said first channel and said second channel. The method of claim 1, And said selected portions of said layer of channel material are at least 10 micrometers from said first conductive elements and said second conductive elements. The method of claim 1, And wherein a region in which the selected portions of the channel material are located is spaced at least 50 micrometers from the first conductive elements and the second conductive elements. delete The method of claim 1, Wherein said one or more selected portions in said step (a) comprise a series of at least two lines extending continuously below a gate line. delete The method of claim 1, The first field effect transistor device and the second field effect transistor device are normally-off field effect transistor devices, wherein the one or more selected portions of step (a) are below the gate line. And manufacturing an array of electronic devices. The method of claim 1, Said gate line has a width, and said one or more selected portions of said step (a) comprise one or more lines extending at least said width of said gate line. The method of claim 1, The first field effect transistor device and the second field effect transistor device are normally-on field effect transistor devices, wherein the one or more selected portions of step (a) are below the gate line. And parts (i) and parts (ii) not under the gate line. 20. The method of claim 19, The one or more first conductive elements comprise a pixel electrode having a plurality of sides, and the one or more selected portions in step (a), one or more extending along each of the sides of the pixel electrode. A method of manufacturing an array of electronic devices, characterized in that it comprises lines. The method of claim 1, The step (a) may comprise one or more laser beams positioned at respective ones of the substrate located at or below the one or more selected portions of the channel material layer. and focusing to the points. The method of claim 1, Wherein the area of the substrate to which the channel material is irradiated does not form a closed path around the first electronic device and the second electronic device. The method of claim 1, Etching the channel material also etches a portion of the material of the substrate. delete delete delete delete delete delete delete The method of claim 1, Wherein said one or more selected portions of said channel material layer comprise one or more portions below a conductive line. The method of claim 1, The first conductive elements comprise a conductive element having a plurality of sides, and the one or more selected portions in step (a) extend along at least two sides of the conductive element having the plurality of sides. And one or more lines. delete The method of claim 1, And said step (a) comprises etching said selected portions of said channel material layer using ultraviolet laser radiation. A method of manufacturing an array of electronic devices, Forming one or more first conductive elements of the first electronic device on the substrate as well as forming one or more second conductive elements of the second electronic device on the substrate; And The substrate to provide a first channel for the movement of charge carriers between the conductive elements of the first electronic device in use and to provide a second channel for the movement of charge carriers between the conductive elements of the second electronic device in use. And forming a channel material layer of channel material on the first conductive elements and the second conductive elements. The method also includes irradiation techniques for reducing the conductivity of one or more selected portions of the channel material layer in one or more regions between the first conductive elements and the second conductive elements in a single step. (a) using an irradiative technique, Wherein the area of the substrate to which the channel material is irradiated does not form a closed path around the first electronic device and the second electronic device. A method of manufacturing an array of electronic devices, Forming one or more first conductive elements of the first electronic device on the substrate as well as forming one or more second conductive elements of the second electronic device on the substrate; And The substrate to provide a first channel for the movement of charge carriers between the conductive elements of the first electronic device in use and to provide a second channel for the movement of charge carriers between the conductive elements of the second electronic device in use. And forming a channel material layer of channel material on the first conductive elements and the second conductive elements. The method also includes irradiation techniques for reducing the conductivity of one or more selected portions of the channel material layer in one or more regions between the first conductive elements and the second conductive elements in a single step. (a) using an irradiative technique, Wherein said one or more selected portions of said channel material layer comprise one or more portions below a conductive line. A method of manufacturing an array of electronic devices, Forming one or more first conductive elements of the first electronic device on the substrate as well as forming one or more second conductive elements of the second electronic device on the substrate; And The substrate to provide a first channel for the movement of charge carriers between the conductive elements of the first electronic device in use and to provide a second channel for the movement of charge carriers between the conductive elements of the second electronic device in use. And forming a channel material layer of channel material on the first conductive elements and the second conductive elements. The method also includes irradiation techniques for reducing the conductivity of one or more selected portions of the channel material layer in one or more regions between the first conductive elements and the second conductive elements in a single step. (a) using an irradiative technique, The one or more first conductive elements comprise a conductive element having a plurality of sides, and the one or more selected portions in step (a) are along at least two sides of the conductive element having the plurality of sides. A method for manufacturing an array of electronic devices comprising one or more lines extending.

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