KR101319252B1 - Method for forming a through silicon via - Google Patents

Abstract

 A method of forming a through silicon via of a semiconductor substrate capable of overcoming the limitation of dry etching, in which the aspect ratio cannot be increased when forming a through hole for through silicon via, is disclosed. To this end, the present invention comprises the steps of preparing a semiconductor substrate, forming a first via hole by anisotropic etching so as not to penetrate the semiconductor substrate from the front surface of the semiconductor substrate, and the first surface of the semiconductor substrate at the bottom surface of the semiconductor substrate And forming a second via hole by wet etching so as to be connected with the via hole. Thus, a semiconductor substrate having through silicon vias suitable for a stacked semiconductor package can be realized.

Description

Method for forming a through silicon via

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a through silicon via (TSV) of a semiconductor substrate using wet etching and dry etching at the same time.

In the past, semiconductor chips were generally electrically connected to a printed circuit board (PCB) for a semiconductor package, which is a basic frame of the semiconductor package, through a wire or a bump. Recently, however, development of high-performance semiconductor packages such as stacked packages, multichip packages (MCPs), and system in packages (SIPs) has been actively developed. Accordingly, the development of three-dimension (3D) packaging technology for mounting more semiconductor chips in a single semiconductor package in a vertical direction has been actively developed. At this time, the semiconductor chips mounted in the vertical direction are mounted on the semiconductor package substrate while being electrically connected to each other through a TSV instead of a conventional wire or bump.

The vertical connection of the semiconductor chip through the TSV can shorten the signal connection path to improve the electrical characteristics of the semiconductor package, reduce the size of the semiconductor package, and ultimately reduce the bandwidth of the semiconductor device. There is an advantage that can be increased. Therefore, to develop 3D packaging technology, a stable TSV formation method is urgently needed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a through silicon via of a semiconductor substrate capable of overcoming the limitation of dry etching in which the aspect ratio cannot be increased when forming a via hole for a through silicon via (TSV). There is.

In the method of forming a through silicon via of a semiconductor substrate according to an aspect of the inventive concept, the method may include preparing a semiconductor substrate, etching the semiconductor substrate from the front surface of the semiconductor substrate so as not to penetrate the semiconductor substrate, and forming a first via hole by dry etching. And forming a second via hole by wet etching so as to be connected to the first via hole of the semiconductor substrate at a bottom surface of the semiconductor substrate.

According to an experimental embodiment of the present invention, it is preferable that the semiconductor substrate has a silicon crystal plane direction of (100).

In addition, according to an experimental embodiment of the present invention, after the step of forming the first via hole by the dry etching, it is suitable to further proceed to fill the first via hole with a conductive material.

In addition, after the forming of the second via hole by the wet etching, the step of filling the second via hole with a conductive material may be further performed.

In this case, after the filling of the conductive material, the step of forming a redistribution layer (RDL) connected to the conductive material may be further proceeded.

Therefore, according to the technical spirit of the present invention described above, first, in the dry etching, it is difficult to dig deeply TSV via hole, while at the same time overcome the difficulty of digging the via hole narrowly during wet etching, mixing them in a stable manner A via hole for TSV can be formed. Second, since the aperture sizes of the via holes formed on the upper and lower portions of the semiconductor substrate can be adjusted, TSV via holes of an ideal shape can be realized in a semiconductor chip used in a stacked semiconductor package.

1 is a flowchart for explaining a method of forming a through silicon via of a semiconductor substrate according to an exemplary embodiment of the present invention.
2 to 7 are cross-sectional views illustrating a method of forming a through silicon via of a semiconductor substrate in accordance with an embodiment of the present invention.
8 is a cross-sectional view for describing a field of application of a semiconductor substrate on which a through silicon via is formed according to an embodiment of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the constituent elements are shown enlarged for the sake of convenience of explanation, and the proportions of the constituent elements may be exaggerated or reduced.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a flowchart for explaining a method of forming a through silicon via (TSV) of a semiconductor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 1, first, a semiconductor substrate S100 is prepared. The semiconductor substrate may have a direction of the silicon crystal plane (100). Subsequently, a first via hole by dry etching is formed on a top side of the semiconductor substrate (S200). Thereafter, the inside of the first via hole formed on the front surface of the semiconductor substrate is filled with a conductive material (S300).

A second via hole is formed on the bottom surface of the semiconductor substrate filled with the conductive material by wet etching again (S400). In this case, the first via hole and the second via hole may be formed to be connected to each other. Subsequently, a conductive material is filled in the second via hole (S500) to form a TSV filled with a conductive material penetrating the semiconductor substrate. Therefore, according to the present invention, the via hole for TSV is formed by a method of mixing dry etching and wet etching.

A redistribution layer (RDL) is formed on the entire surface of the semiconductor substrate filled with the conductive material (S600), and a redistribution layer (RDL) is formed on the bottom surface of the semiconductor substrate (S700). The through-silicon via forming process of the semiconductor substrate according to the embodiment is completed.

Hereinafter, a method of forming a through silicon via of a semiconductor substrate according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2 to 7 are cross-sectional views illustrating a method of forming a through silicon via of a semiconductor substrate in accordance with an embodiment of the present invention.

Referring to FIG. 2, first, a semiconductor substrate 100 is prepared. The semiconductor substrate 100 may have a structure in which a predetermined circuit pattern that performs a predetermined function is formed on a top side and a final passivation layer is covered. In addition, the semiconductor substrate 100 may be a semiconductor substrate used as an interposer inserted in the middle of the upper and lower semiconductor chips and used as a connection path between the upper and lower sides. In addition, the semiconductor substrate 100 may be a semiconductor substrate 100 having a thickness thinned through a back-grinding process.

At this time, it is preferable that the semiconductor substrate 100 uses a semiconductor wafer having a silicon crystal surface structure of (100). Generally, semiconductor wafers are classified into (100), (110), and (111) semiconductor wafers according to the structure of the crystal plane of the silicon single crystal. For example, assuming that a silicon single crystal has a cube exactly, a square shape cut and processed corresponds to a (100) semiconductor wafer, and a crystal face cut straight down from both diagonal vertices of a square corresponds to a (110) semiconductor. Corresponding to the wafer, and having a crystal plane in the direction of drawing a triangle diagonally downward from one vertex corresponds to a (111) semiconductor wafer. At this time, the (100) semiconductor wafer has a chemically relatively stable property, and the (111) semiconductor wafer has a chemically active reaction. And (110) semiconductor wafers are known to have intermediate properties.

The reason for using the semiconductor wafer having the crystal plane structure of single crystal silicon (100) as the semiconductor substrate 100 in the present invention is that the semiconductor wafer having the crystal plane structure of the single crystal silicon (100) is constant with respect to the horizontal plane during wet etching. This is because it is etched at an angle to have an angle.

Referring to FIG. 3, a dry etching process is performed on the semiconductor substrate 100 to form a first via hole 102 having a predetermined depth. In this case, the dry etching may be performed using a gas such as Cl 2, Ar, He, CF 4, SiF 4, etc. through a reactive ion etching (RIE) method, and as an etching mask, a single layer such as an oxide film, a nitride film, or a photoresist may be used. Membrane or composite membrane may be used. The dry visual process may be modified in various ways at the level of those skilled in the art within the scope of dry etching.

Referring to FIG. 4, in the semiconductor substrate 100 on which the first via hole 102 is formed, the inside of the first via hole 102 is filled with a conductive material 104. Specifically, first, an insulating film 106 made of a single film or a composite film of an oxide film and a nitride film is formed on the entire surface of the semiconductor substrate 100 on which the first via hole is formed. Subsequently, a seed layer (not shown) layer is laminated to a thin thickness, and then the conductive material 104 is filled in the first via hole 102 by using electroplating. The conductive material may be a metal such as copper (Cu). Thereafter, the conductive material 104 formed on the insulating film 106 is removed through a chemical mechanical polishing (CMP) process. In this case, the insulating layer 106 may be used as a polishing stopper 106.

Referring to FIG. 5, the conductive material 104 forms a second via hole 110 in a wet etching method on a bottom surface of the semiconductor substrate 100 filled in the first via hole 102. In this case, a single film of a nitride film, an oxide film, or a composite film thereof may be used as a mask pattern. In this case, as the etchant of the wet etching, a solution of 33 ± 5 wt% potassium hydroxide (hereinafter, referred to as 'KOH') mixed with water and isopropyl alcohol may be used. It is preferable that the temperature at which wet etching proceeds is performed in a temperature range of 80 ± 3 ° C.

In the above-described wet etching process, since the semiconductor wafer 100 has the crystal plane direction of the semiconductor wafer 100 according to the present invention, the through-via hole 110 has an inclination of 54.74 ° with respect to the horizontal plane of the semiconductor wafer (in the drawing). it is formed obliquely to have θ). Therefore, the upper first via hole 102 of the semiconductor substrate 100 may have a narrow aperture, and the lower second via hole 110 may form a TSV via hole having a shape having a wide aperture (112 in FIG. 6).

In this case, as the depth of the second via hole 110 is expanded, the deeper the etching depth of the semiconductor substrate 100 may be obtained by wet etching. Therefore, in the method of forming a through-silicon via of the semiconductor substrate according to the present invention, it is difficult to dig deeply through TSV via holes during dry etching, and at the same time, it is difficult to dig through holes narrowly during wet etching, and then, they are mixed and stabilized. Thus, TSV via holes (112 in FIG. 6) can be formed.

Referring to FIG. 6, the conductive material 104 is filled in the semiconductor substrate 100 on which the second via hole 110 is formed. Specifically, first, an insulating film 108 including a single film or a composite film of an oxide film and a nitride film is formed on the bottom surface of the semiconductor substrate 100 on which the second via hole 110 is formed. Subsequently, a seed layer (not shown) layer is laminated to a thin thickness, and then a conductive material is filled in the second via hole 110 by using electroplating. The conductive material may be a metal such as copper (Cu). Thereafter, the conductive material 104A formed under the insulating film 108 is removed through a chemical mechanical polishing (CMP) process. In the chemical mechanical polishing process, the insulating layer 108 may serve as a polishing blocking layer.

Referring to FIG. 7, redistribution layers 114 and 116 connected to the conductive materials 104 and 104A filling the TSV via hole 112 are formed on the front and bottom surfaces of the semiconductor substrate 100, respectively. The redistribution layers 114 and 116 are formed to freely move the positions where the TSVs are formed on the upper and lower surfaces of the semiconductor substrate 100, and thus, the spaces on the front and bottom surfaces of the semiconductor substrate 100 may be viewed due to the position movement of the TSVs. Make sure you use it efficiently. Subsequently, the external connection terminals 118 and 120, for example, solder balls or solder bumps are attached to pads to which the external connection terminals are connected in the redistribution layers 114 and 116 of the semiconductor substrate 1000 according to an exemplary embodiment of the present invention. Complete the through silicon via formation process.

8 is a cross-sectional view for describing a field of application of a semiconductor substrate on which a through silicon via is formed according to an embodiment of the present invention.

Referring to FIG. 8, the semiconductor substrate 1000 according to FIG. 7 including a TSV manufactured according to the present invention may include a lower semiconductor package 1200 in a system in package (SIP) having a package on package (POP) structure. ) And an embodiment used as an interposer 1000 connecting the upper semiconductor package 1100 with each other. At this time, the number of TSVs increased from 4 to 6 was applied. In general, in the package on package (POP), the external connection terminal 1202 used in the lower semiconductor package 1200, for example, a solder ball has a large size, and the external connection terminal 118 used in the upper semiconductor package 1100 has a large size. In a small case, the semiconductor substrate 1000 having the TSV according to the present invention can be inserted in the middle and used efficiently as a connection path.

The external connection terminal 118 connected to the conductive material for TSV (104 in Fig. 7) at the front side is narrow, the external connection terminal 120 is connected to the conductive material for TSV (104A in Fig. 7) at the bottom This is because the line width is large. In the drawings, reference numerals 1204, 1206, and 1208 denote underfills that protect external connection terminals from external damage or electrical contact. In addition, the lower semiconductor package 1200 shows a state mounted on the printed circuit board 200 through an external connection terminal 1202. The number and diameter of the TSVs of the semiconductor substrate 1000 are illustrated by way of example and may be modified in various forms to optimize by those skilled in the art.

At this time, the present application example was shown that the semiconductor substrate 1000 according to the present invention used as an interposer is used between the lower semiconductor package 1200 and the upper semiconductor package 1100. However, the semiconductor substrate 1000 according to the present invention may be applied in such a manner that the external connection terminal 120 of the semiconductor substrate 1000 is mounted on the printed circuit board 200 without mounting the lower semiconductor package 1200. It is possible.

Meanwhile, the semiconductor substrate 1000 having a TSV according to the present invention may be used as a semiconductor chip used in the middle of a stacked semiconductor package in which three or more semiconductor chips are stacked vertically. In addition, the present invention can be applied to various fields of miniaturization or expansion of semiconductor packages.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

100: semiconductor substrate, 102: first via hole,
104: conductive material, 106/108: insulating film,
110: second via hole, 112: TSV via hole,
114: upper redistribution layer, 116: lower redistribution layer,
118/120: External connection terminal.

Claims (5)

Preparing a semiconductor substrate;
Etching the front surface of the semiconductor substrate so as not to penetrate the semiconductor substrate, but forming a first via hole by dry etching; And
And etching the bottom surface of the semiconductor substrate so as to be connected to the first via hole of the semiconductor substrate, and forming a second via hole by wet etching.
The method of claim 1,
The semiconductor substrate has a silicon crystal plane direction of (100), wherein the through-silicon via formation method of the semiconductor substrate.
The method of claim 1,
After forming the first via hole by the dry etching,
And further filling the first via hole with a conductive material.
The method of claim 1,
After forming the second via hole by the wet etching,
And further filling the second via hole with a conductive material.
The method according to claim 3 or 4,
After filling the conductive material,
And further forming a redistribution layer (RDL) connected to the conductive material.

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