KR101319196B1 - Thin film transistor, method of manufacturing the same and organic light emitting diode display having the same - Google Patents

Abstract

A thin film transistor, a method of manufacturing the same, and an organic light emitting diode display device having the same are described. The thin film transistor includes a channel portion, a source portion and a drain portion connected to both sides of the channel portion, and a charge deceleration portion interposed between at least one of the source portion and the drain portion and the channel portion to reduce the mobility of the charge moving from the source portion to the drain portion. The semiconductor substrate may have a semiconductor pattern to ensure uniformity of the thin film transistor.

Polysilicon, Charge Mobility, Thin Film Transistor, Luminance, Organic Light Emitting Diode

Description

Thin film transistor, manufacturing method thereof, and organic light emitting diode display device having the same {THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND ORGANIC LIGHT EMITTING DIODE DISPLAY HAVING THE SAME}

1A is a plan view of a thin film transistor according to a first embodiment of the present invention.

1B is a cross-sectional view taken along the line I-I 'shown in FIG. 1A.

FIG. 1C is a plan view illustrating a semiconductor pattern of the thin film transistor illustrated in FIG. 1A.

2A to 2D are plan views illustrating various forms of a semiconductor pattern according to a first embodiment of the present invention.

3 is a cross-sectional view of a thin film transistor according to a second embodiment of the present invention.

4A to 4D are cross-sectional views illustrating a manufacturing process of a thin film transistor according to a third embodiment of the present invention.

5A to 5D are cross-sectional views illustrating a manufacturing process of a thin film transistor according to a fourth embodiment of the present invention.

6A is a plan view of an organic light emitting diode display according to a fifth exemplary embodiment of the present invention.

FIG. 6B is a cross-sectional view taken along the line II-II 'of FIG. 6A.

 DESCRIPTION OF THE REFERENCE NUMERALS (S)

 100, 200, 300: substrate 110, 210, 310a, 310b: semiconductor pattern

 111, 211, 311a, 311b: channel portion 112, 212, 312a, 312b: charge reduction portion

 113, 213, 313a, 313b: source portion 114, 214, 314a, 314b: drain portion

 120, 220, 320: gate insulating film 130, 230, 330: gate electrode

 140, 240, 340: interlayer insulating film 150, 250, 350: source electrode

 160, 260, 360: drain electrode 370: protective film

 380: first electrode 390: organic light emitting layer

 400: second electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a thin film transistor and an organic light emitting diode display device having the same, which can reduce variations in electrical characteristics.

Today, with the development of information and communication, display devices are increasing in demand for various functions including image quality. At this time, it was possible to realize by adopting a thin film transistor as the display device. The thin film transistor can reduce power consumption and improve lifespan as well as image quality of a display device. In particular, the thin film transistor played a huge role in realizing a large area of the display device.

Such thin film transistors generally include a semiconductor layer, a gate electrode, a source electrode and a drain electrode. Here, the semiconductor layer may be formed of amorphous silicon or polysilicon. In particular, polysilicon has a higher charge mobility than amorphous silicon.

In order to form the polysilicon, a process of scanning a laser beam in an amorphous silicon film is performed. At this time, a shot of the laser beam may be superimposed on a portion of the amorphous silicon film, and the polysilicon formed in the overlapping region of the laser beam has better crystallinity than other regions. Here, the crystallinity and the charge mobility become proportional.

Therefore, the first thin film transistor formed of the polysilicon of the overlapped region and the second thin film transistor formed of the polysilicon other than the overlapped region have different electrical characteristics. That is, the first thin film transistor has a greater charge mobility than the second thin film transistor, and thus, the first thin film transistor and the second thin film transistor have a characteristic deviation of voltage-current. Accordingly, when the display device is formed by using the first and second thin film transistors, the display device may have non-uniform brightness, resulting in a problem of deterioration of image quality such as unevenness of the screen.

An object of the present invention is to provide a thin film transistor which can reduce the variation of the electrical characteristics and improve the electrical characteristics.

Another object of the present invention is to provide an organic light emitting diode display device having the uniform brightness by including the thin film transistor.

In order to achieve the above technical problem, an aspect of the present invention provides a thin film transistor. The thin film transistor includes a channel part, a source part and a drain part connected to both sides of the channel part, at least one of the source part and the drain part and the channel part interposed between the channel part and the movement of the charge moving from the source part to the drain part. A semiconductor pattern having a charge decelerating portion to reduce the degree; A gate insulating film covering the semiconductor pattern; A gate electrode on the gate insulating layer corresponding to the channel portion; An interlayer insulating film covering the gate electrode and disposed on the gate insulating film; A source electrode provided on the interlayer insulating film and electrically connected to the source part; And a drain electrode provided on the interlayer insulating layer and electrically connected to the drain portion.

Another aspect of the present invention to achieve the above technical problem provides a method of manufacturing a thin film transistor. The manufacturing method includes forming a preliminary semiconductor pattern on a substrate; Forming a gate insulating layer on the substrate to cover the preliminary semiconductor pattern; Forming a gate electrode on the gate insulating layer corresponding to the preliminary semiconductor pattern; Impurities are implanted into the preliminary semiconductor pattern using the gate electrode as a mask, and a channel portion corresponding to the gate electrode, a source portion and a drain portion connected to both sides of the channel portion, and at least one of the source portion and the drain portion Forming a semiconductor pattern having a charge deceleration portion interposed between one and the channel portions to decelerate the mobility of charge moving from the source portion to the drain portion; Forming an interlayer insulating film covering the gate electrode on the gate insulating film; And forming a source electrode electrically connected to the source portion and a drain electrode electrically connected to the drain portion on the interlayer insulating layer.

Another aspect of the present invention to achieve the above technical problem provides a method of manufacturing a thin film transistor. In the manufacturing method, a channel region, a source region and a drain region respectively connected to both sides of the channel region are defined on a substrate, and a first charge reduction unit interposed between at least one of the source portion and the drain portion and the channel portion. Forming a preliminary semiconductor pattern; Forming a second charge reducer on the first charge reducer of the preliminary semiconductor pattern; Forming a gate insulating layer on the substrate, the gate insulating layer covering the preliminary semiconductor pattern on which the second charge reduction unit is formed; Forming a gate electrode on the gate insulating layer corresponding to the channel region; Implanting impurities into the preliminary semiconductor pattern using the gate electrode as a mask to form the source region, the drain region, and the channel region as source, drain, and channel portions to form a semiconductor pattern; Forming an interlayer insulating film on the gate insulating film covering the gate electrode; And forming a source electrode electrically connected to the source portion and a drain electrode electrically connected to the drain portion on the interlayer insulating film.

In order to achieve the above technical problem, another aspect of the present invention provides an organic light emitting diode display. The display device is disposed on a substrate and is interposed between a channel portion, a source portion and a drain portion connected to both sides of the channel portion, at least one of the source portion and the drain portion, and the channel portion, from the source portion to the drain portion. A semiconductor pattern having a charge decelerating portion that decelerates the mobility of moving charges; A gate insulating layer covering the semiconductor pattern and disposed on the substrate; A gate electrode on the gate insulating layer corresponding to the channel portion; An interlayer insulating film covering the gate electrode and disposed on the gate insulating film; A source electrode provided on the interlayer insulating film and electrically connected to the source part; A drain electrode provided on the interlayer insulating film and electrically connected to the drain part; A passivation layer covering the source electrode and the drain electrode and provided on the interlayer insulating layer; And an organic light emitting diode disposed on the passivation layer and electrically connected to the drain electrode.

Hereinafter, a thin film transistor and an organic light emitting diode display according to the present invention will be described in detail. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like numbers refer to like elements throughout.

Example  One

FIG. 1A is a plan view of a thin film transistor according to a first embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line II ′ of FIG. 1A, and FIG. 1C is a semiconductor of the thin film transistor of FIG. 1A. A plan view showing a pattern.

1A to 1C, a thin film transistor according to an exemplary embodiment of the present invention may include a semiconductor pattern 110, a gate insulating layer 120, a gate electrode 130, and an interlayer insulating layer 140 disposed on a substrate 100. And a source electrode 150 and a drain electrode 160.

The semiconductor pattern 110 includes a channel portion 111 and a source portion 113 and a drain portion 114 connected to both sides of the channel portion 111, respectively. Here, the source 113 and the drain 114 may be doped with impurities. The impurities may be P-type or N-type, but is not limited in the embodiment of the present invention. In this case, when the channel part 111 is turned on by the gate electrode 130, the charge is transferred from the source part 113 to the drain part 114. Here, the semiconductor pattern 110 may be formed of polysilicon having a greater charge mobility than amorphous silicon, thereby improving electrical characteristics of the completed thin film transistor. However, when polysilicon is formed on the substrate 100, it is difficult to form polysilicon having uniform characteristics in all regions of the substrate 100 due to process difficulties.

When a plurality of thin film transistors are formed using polysilicon having non-uniform characteristics as described above, the plurality of thin film transistors have non-uniform electrical characteristics, for example, voltage-current variation. In this case, when the display device is formed by using thin film transistors having non-uniform characteristics, the luminance of the display device may become uneven.

As a result, the semiconductor pattern 110 may drastically reduce the mobility of charges moving from the source portion 113 to the drain portion 114, thereby improving the nonuniformity of the electrical characteristics of the thin film transistor. For example, the first semiconductor pattern may have a charge mobility of 100 cm ² / V · S, and the second semiconductor pattern may be 70 cm ² / V · S. As a result, the variation in charge mobility between the first semiconductor pattern and the second semiconductor pattern has 30 cm ² / V · S. However, when the first semiconductor pattern decreases the charge mobility by 10 cm ² / V · S and the second semiconductor pattern decreases by 7 cm ² / V · S, the charge mobility between the first semiconductor pattern and the second semiconductor pattern is reduced. The deviation has 3 cm ² / V · S. That is, as the charge mobility of the semiconductor pattern 110 is smaller, the variation in charge mobility between the semiconductor patterns 110 may be reduced. As a result, the first and second thin film transistors each having the first and second semiconductor patterns may reduce variations in electrical characteristics, for example, variations in voltage-current characteristics.

Therefore, the charge mobility in the semiconductor pattern 110 is reduced through the charge deceleration unit 112 between at least one of the source portion 113 and the drain portion 114 and the channel portion 111. In this case, the charge reduction unit 112 may reduce the charge mobility in the semiconductor pattern 110 from about 70 to 100 cm ² / V · S to 7 to 10 cm ² / V · S.

The charge reduction unit 112 includes impurities having a lower content than the source unit 113 or the drain unit 114. As a result, the charge reduction unit 112 may serve as a resistor for reducing the charge mobility moving from the source unit 113 to the channel unit 111. Alternatively, the charge reduction unit 112 may serve as a resistor for reducing the charge mobility moving from the channel unit 111 to the drain unit 114. Therefore, the charge reduction unit 112 has a higher resistance than the source unit 113 or the drain unit 114.

In addition, the charge reduction unit 112 is formed to be equal to or larger than the length of the channel unit 111. Therefore, the path of the charge moving from the source portion 113 to the channel portion 111 or from the channel portion 111 to the drain portion 114 is increased, thereby rapidly increasing the charge mobility in the semiconductor pattern 110. Can be reduced. For example, when the length of the channel portion 111 is 4 μm, the length of the charge reduction unit 112 may be 4 to 5 μm. If the length of the charge deceleration unit 112 is too long compared with the channel portion 111, the charge mobility of the semiconductor pattern 110 may be excessively reduced to deteriorate the characteristics of the thin film transistor.

In this case, as the semiconductor pattern 110 includes the charge deceleration unit 112, the size of the semiconductor pattern 110 is increased, and as a result, the size of the thin film transistor is increased. Therefore, the aperture ratio of the display device can be lowered.

Thus, while reducing the size of the thin film transistor, it should be designed to increase the surface area of the semiconductor pattern (110). This is because the path of charge in the charge deceleration section 112 must be increased.

2A to 2D are plan views illustrating various types of semiconductor patterns according to the first embodiment of the present invention.

2A to 2D, the semiconductor pattern may have a 'U' shape when viewed in plan to increase the surface area.

In detail, as shown in FIGS. 2A and 2C, the semiconductor pattern may include curved curved portions A and B in the charge deceleration portion. At this time, as shown in Figure 2a, the bent portion (A) may be one. As shown in Figure 2b and 2c, there may be at least two bends (A, B).

In addition, as shown in FIGS. 2A and 2B, the bent portion A may have a predetermined angle and have a bent shape, or as shown in FIG. 2C, the bent portion B may have a gentle shape.

As shown in FIG. 2D, the charge reduction unit 112 may be bent at both sides of the channel unit 111.

Therefore, by reducing the area occupied by the semiconductor pattern 110 and increasing the surface area of the semiconductor pattern 110, in particular, the charge deceleration part 112, the movement path of the charge in the charge deceleration part 112 may be increased.

Referring back to FIGS. 1A and 1C, the gate insulating layer 120 covering the semiconductor pattern 110 is disposed. The gate insulating film 120 is made of an inorganic insulating film. For example, the inorganic insulating film may be a silicon nitride film, a silicon oxide film, a laminated film thereof, or the like.

The gate electrode 130 is disposed on the gate insulating layer 120 corresponding to the channel portion 111 of the semiconductor pattern 110. In this case, the channel 111 and the gate electrode 130 may have the same length. This is because the impurity implantation process of the semiconductor pattern 110 may be performed using the gate electrode 130 as a mask.

An interlayer insulating layer 140 covering the gate electrode 130 is disposed on the gate insulating layer 120. The interlayer insulating layer 140 is made of an inorganic insulating layer. The inorganic insulating film may be a silicon nitride film, a silicon oxide film, a laminated film thereof, or the like.

The interlayer insulating layer 140 and the gate insulating layer 120 include contact holes C exposing the source portion 113 and the drain portion 114, respectively.

A source electrode 150 electrically connected to the source unit 113 through the contact hole C is disposed on the interlayer insulating layer 140. In addition, a drain electrode 160 electrically connected to the drain portion 114 through the contact hole C is disposed on the interlayer insulating layer 140. In this case, the source electrode 150 and the drain electrode 160 have a predetermined interval.

Therefore, in the embodiment of the present invention, the semiconductor pattern 110 of the thin film transistor is formed of polysilicon having a greater charge mobility than amorphous silicon, thereby improving the electrical characteristics of the thin film transistor. In addition, the charge reduction unit 112 may be provided in the semiconductor pattern 110 to improve the electrical characteristics of the thin film transistor according to the position of the thin film transistor due to the non-uniformity of the polysilicon.

Example  2

3 is a plan view of a thin film transistor according to a second exemplary embodiment of the present invention. The second embodiment of the present invention has the same configuration as the thin film transistor of the first embodiment described above except for the charge reduction portion. Therefore, in the second embodiment, duplicate descriptions of the same components will be omitted.

Referring to FIG. 3, a thin film transistor according to an exemplary embodiment of the present invention may include a semiconductor pattern 210, a gate insulating layer 220, a gate electrode 230, an interlayer insulating layer 240, and a source electrode disposed on a substrate 200. 250 and the drain electrode 260.

The semiconductor pattern 210 may include at least one of a channel portion 211, a source portion 213 and a drain portion 214, a source portion 213, and a drain portion 214 connected to both sides of the channel portion 211, respectively. The charge deceleration unit 212 is interposed between the channel unit 211.

The source portion 213 and the drain portion 214 are made of polysilicon containing the first impurity. The first impurity may be a P-type ion or an N-type ion. However, it is not limited to the embodiment of the present invention.

The charge decelerating unit 212 may reduce charge mobility in the semiconductor pattern 210. The charge reducer 212 includes a stacked first charge reducer 212a and a second charge reducer 212b. The first charge reduction part 212a is integrally formed with the channel part 211, the source part 213, and the drain part 214. At this time, the first charge reduction unit 212a is made of polysilicon. The second charge reduction unit 212b is disposed on the first charge reduction unit 212a. In this case, the second charge reduction unit 212b is made of amorphous silicon containing the second impurity. When the first impurity is a P-type ion, the second impurity may be an N-type ion. Alternatively, when the first impurity is an N-type ion, the second impurity may be a P-type ion.

In this case, some of the charges provided by the source unit 213 may move to the channel unit 211 through the first charge reduction unit 212a. In addition, some of the charges provided by the source unit 213 may move to the channel unit 211 along the interface between the first charge reduction unit 212a and the second charge reduction unit 212b.

In addition, some of the charges provided by the channel unit 211 may move to the drain unit 214 through the first charge reduction unit 212a. In addition, some of the charges provided by the channel portion 211 may move to the drain portion 214 along the interface between the first charge reduction portion 212a and the second charge reduction portion 212b. In this case, the charges may be trapped in the second charge deceleration unit 212b and then moved to the drain unit 214. In addition, since the second charge reduction unit 212b is made of amorphous silicon having a lower charge mobility than polysilicon, the mobility of the charges is lowered. Accordingly, the charge reduction unit 212 serves as a resistor for reducing the charge mobility in the semiconductor pattern 210, thereby reducing the charge mobility in the semiconductor pattern 210. As a result, variations in charge mobility between the thin film transistors can be reduced, thereby providing a thin film transistor having uniform and excellent electrical characteristics.

Example  3

4A to 4D are cross-sectional views illustrating a manufacturing process of a thin film transistor according to a third embodiment of the present invention. The third embodiment is a method for manufacturing the thin film transistor according to the first embodiment described above.

Referring to FIG. 4A, to manufacture a thin film transistor, first, a substrate 100 is provided.

The preliminary semiconductor pattern 110a is formed on the substrate 100. The preliminary semiconductor pattern 110a includes the channel region 111a and the charge reduction regions 112a disposed at both sides of the channel region 111a, and the source region 113a disposed outside the charge reduction regions 112a, respectively. And drain region 114a is defined.

In order to form the preliminary semiconductor pattern 110a, an amorphous silicon film is first formed on the substrate 100, and then the amorphous silicon film is crystallized to form a polysilicon film. Thereafter, the polysilicon layer is etched to form a preliminary semiconductor pattern 110a on the substrate 100. The amorphous silicon film may be formed through chemical vapor deposition or sputtering. In addition, the crystallization method is an excimer laser annealing method (ELA method), a solid phase crystallization method (SPC method; Solid Phase Crystallization) in which amorphous silicon is crystallized using a furnace heating method in a furnace. ), Sequential lateral solidification (SLS) using energy of the complete melting region or selective deposition of a metal on an amorphous silicon film, followed by heat treatment to crystallize the metal as seed. Any one of metal induced crystallization (MIC) may be selected.

In addition, to increase the surface area of the semiconductor pattern to be described later, the preliminary semiconductor pattern 110a may be formed in a 'U' shape. In addition, the preliminary semiconductor pattern 110a may further increase the surface area by forming a bent portion at least in part. In this case, the curved portion may be formed in the charge deceleration region.

After forming the preliminary semiconductor pattern 110a, a gate insulating layer 120 covering the preliminary semiconductor pattern 110a is formed on the substrate 100. The gate insulating film 120 may be formed of a silicon oxide film, a silicon nitride film, or a stacked film thereof. Here, the gate insulating layer 120 may be formed by, for example, chemical vapor deposition.

A gate electrode 130 overlapping with at least a portion of the preliminary semiconductor pattern 110a is formed on the gate insulating layer 120. The gate electrode 130 may be formed by forming a first conductive layer on the gate insulating layer 120 and then patterning the first conductive layer. The first conductive layer may be a metal. In this case, the first conductive film may be formed through a sputtering method or a vacuum deposition method.

Referring to FIG. 4B, after the gate electrode 130 is formed, a photoresist pattern 135 having an area of at least twice the area of the gate electrode 130 is formed on the gate electrode 130. This is to form the charge deceleration part 112 that is equal to or longer than the length of the channel part 111 to be described later using the photoresist pattern 135. In addition, the photoresist pattern 135 corresponds to the channel region 111a and the charge deceleration regions 112a. That is, the source region 113a and the drain region 114a of the preliminary semiconductor pattern 110a are exposed by the photoresist pattern 135.

Thereafter, the impurity (X) is implanted into the preliminary semiconductor pattern 110a using the photoresist pattern 135 as a mask. At this time, impurities are injected into the source region 113a and the drain region 114a by the photoresist pattern 135 to form the source portion 113 and the drain portion 114.

Referring to FIG. 4C, after the source portion 113 and the drain portion 114 are formed, the photoresist pattern 135 is removed. Subsequently, additional impurities X ′ are implanted into the semiconductor pattern 110 in which the source portion 113 and the drain portion 114 are formed using the gate electrode 130 as a mask. In this case, additional impurities X ′ are injected into the charge reduction region 112a to form the channel portion 111 and the charge reduction portion 112 in the semiconductor pattern 110. In this case, the channel part 111 corresponds to the gate electrode 130. As a result, the channel part 111 is formed of polysilicon into which impurities X and additional impurities X 'are not injected.

Additional impurities X 'are further injected into the source portion 113 and the drain portion 114. In this case, the impurities X and the additional impurities X ′ may have the same characteristics. For example, the impurities X and the additional impurities X ′ may be P-type ions or N-type ions.

As a result, the charge reduction unit 112 includes impurities having a lower content than that of the source unit 113 and the drain unit 114, and as a result, the charge reduction unit 112 includes the source unit 113 and the drain unit 114. It has a higher resistance than. Accordingly, by forming the charge deceleration part 112 in the semiconductor pattern 110, the charge mobility of the semiconductor pattern 110 may be reduced. As a result, variations in charge mobility between the semiconductor patterns 110 may be reduced, thereby forming a thin film transistor having uniform electrical characteristics.

Referring to FIG. 4D, after forming the semiconductor pattern 110 including the charge reduction unit 112, an interlayer insulating layer 140 is formed on the gate insulating layer 120 including the semiconductor pattern 110. The interlayer insulating layer 140 may be formed of an inorganic insulating layer. For example, the inorganic insulating film may be a silicon oxide film, a silicon nitride film, or a laminated film thereof. In this case, the interlayer insulating layer 140 may be formed through chemical vapor deposition.

Thereafter, contact holes C exposing the source portion 113 and the drain portion 114 are formed in the interlayer insulating layer 140 and the gate insulating layer 120. In order to form the contact hole C, a photoresist pattern having an opening formed on the interlayer insulating film is formed. The interlayer insulating layer and the gate insulating layer 120 are etched using the photoresist pattern as an etching mask to form a contact hole C.

Thereafter, a source electrode and a drain electrode connected to the source portion 113 and the drain portion 114 are formed on the interlayer insulating layer through the contact hole C. Here, after forming a second conductive film on the interlayer insulating film to form a source electrode and a drain electrode, the second conductive film is etched. The second conductive film may be made of metal. At this time, the second conductive film can be formed by sputtering or vacuum deposition.

As a result, a thin film transistor including the semiconductor pattern 110 having the charge reduction unit 112, the gate electrode 130, the source electrode 150, and the drain electrode 160 may be formed on the substrate 100.

In addition, in the exemplary embodiment of the present invention, the charge reduction unit 112 is formed on both sides of the channel unit 111, but the present invention is not limited thereto. For example, the charge reduction unit 112 may be formed only on one side of the channel unit 111.

Example  4

5A to 5D are cross-sectional views illustrating a manufacturing process of a thin film transistor according to a fourth embodiment of the present invention. The fourth embodiment is a method for manufacturing the thin film transistor according to the second embodiment described above.

Referring to FIG. 5A, to form a thin film transistor, first, a substrate 200 is provided. The preliminary semiconductor pattern 210a is formed on the substrate 200. The preliminary semiconductor pattern 210a may include a channel region 211a, first charge deceleration units 212a connected to both sides of the channel region 211a, and source regions connected to the outside of the first charge reduction units 212a, respectively. 213a and drain region 214a.

In order to form the preliminary semiconductor pattern 210a, an amorphous silicon film is formed on the substrate 100, and then the amorphous silicon film is crystallized to form a polysilicon film. The preliminary semiconductor pattern 210a may be formed by etching the polysilicon layer.

Referring to FIG. 5B, after the preliminary semiconductor pattern 210a is formed, the second charge reducer 212b is formed on the first charge reducer 212a.

The second charge reduction unit 212b may form the amorphous silicon film containing the first impurity and then etch the amorphous silicon film. In this case, the amorphous silicon film may be formed through chemical vapor deposition. Here, the first impurity may be a P-type ion or an N-type ion.

Here, the semiconductor pattern 210 may be formed in a 'U' shape when viewed in a plan view to reduce the size of the thin film transistor and increase the surface area. In addition, the semiconductor pattern 210 may form a bent portion at a predetermined portion. In this case, the bent portion may be formed in the first and second charge reduction units 212a and 212b.

Referring to FIG. 5C, a gate insulating layer 220 covering the preliminary semiconductor pattern 210a on which the second charge reduction unit 212b is formed is formed on the substrate 200.

The gate electrode 230 is formed on the gate insulating layer 220 corresponding to the channel region 211a.

The second impurity X is injected into the preliminary semiconductor pattern 210a using the gate electrode 230 as a mask. When the first impurity is a P-type ion, the second impurity (X) may be an N-type ion. On the other hand, when the first impurity is an N-type ion, the second impurity (X) may be a P-type ion.

Here, the second impurity X is injected into the source region 213a and the drain region 214a to form the source portion 213 and the drain portion 214. In this case, the second impurity is not injected into the channel region 211a by the gate electrode 230, and a channel portion 211 is formed which is separated from the source portion 213 and the drain portion 214. As a result, a semiconductor pattern 210 including a source portion 213, a drain portion 214, a channel portion 211, and first and second charge deceleration portions 212a and 212b is formed on the substrate 200. .

Therefore, the first charge reduction unit 212a and the second charge reduction unit 212b serve to reduce the mobility of the charges moved in the semiconductor pattern 210. Accordingly, when a plurality of semiconductor patterns 210 are formed on the substrate 200, the variation in charge mobility between the semiconductor patterns 210 may be reduced.

Referring to FIG. 5D, an interlayer insulating layer 240 covering the semiconductor pattern 210 is formed on the gate insulating layer 220.

Thereafter, the thin film transistor is completed on the substrate 200 by forming the source electrode 250 and the drain electrode 260 electrically connected to the source portion 213 and the drain portion 214 on the interlayer insulating layer 240. do.

Example  5

6A is a plan view of an organic light emitting diode display according to a fifth exemplary embodiment of the present invention, and FIG. 6B is a cross - sectional view taken along the line II-II ′ of FIG. 6A. In the fifth embodiment of the present invention, the thin film transistor of the first or second embodiment described above may be provided. Therefore, in the fifth embodiment of the present invention, repeated description will be omitted.

6A and 6B, in the organic light emitting diode display, a plurality of gate lines 301 and data lines 302 intersecting each other are disposed on a substrate 300. In this case, a plurality of cells in a lattice form is formed on the substrate 300 by the plurality of gate lines 301 and the data lines 302. Here, one of the plurality of cells may be defined as one pixel P. Thus, the display device includes a plurality of pixels defined by the plurality of gate lines 301 and the data lines 302.

Each pixel is provided with a thin film transistor Tr.

The thin film transistor Tr may include a switching thin film transistor Tr1 and a driving thin film transistor Tr2 connected to each other.

The switching thin film transistor Tr1 and the driving thin film transistor Tr2 include semiconductor layer patterns 310a and 310b, gate electrodes 330a and 330b, source electrodes 350a and 350b, and drain electrodes 360a and 360b. In this case, the gate electrode 330a of the switching thin film transistor Tr1 is connected to the gate wiring 301, the source electrode 350a is connected to the data wiring 302, and the drain electrode 360a is a driving thin film transistor ( It is connected to the gate electrode 330b of Tr2. The source electrode 350b of the driving thin film transistor Tr2 is connected to the power supply wiring 303, and the drain electrode 360b is electrically connected to the first electrode 380 which will be described later.

Since the semiconductor patterns 310a and 310b are made of polysilicon, electrical characteristics of the thin film transistor Tr may be improved. However, when polysilicon is formed non-uniformly, semiconductor patterns included in a plurality of pixels may cause large variations in electrical characteristics. This is because polysilicon has a high charge mobility. As a result, the display device includes thin film transistors having different electrical characteristics in each pixel. As a result, the display device may have different luminance for each pixel, thereby degrading the image quality of the display device.

As a result, the semiconductor patterns 310a and 310b may include the charge reduction units 312a and 312b interposed between at least one of the source portions 313a and 313b and the drain portions 314a and 314b and the channel portions 311a and 311b. Equipped. Here, the charge deceleration parts 312a and 312b have a larger resistance than the source parts 313a and 313b and the drain parts 314a and 314b to reduce the charge mobility in the semiconductor chattens 310a and 310b. Therefore, when the plurality of thin film transistors are formed on the substrate 300 using polysilicon, the electrical deviation between the thin film transistors may be reduced.

The charge reduction parts 312a and 312b include impurities having a lower concentration than the source parts 313a and 313b and the drain parts 314a and 314b. Alternatively, the charge reduction units 312a and 312b may be formed by stacking polysilicon and amorphous silicon in order to increase resistance. In addition, the charge reduction parts 312a and 312b may have a length equal to or greater than the length of the channel parts 311a and 311b in order to increase resistance by increasing a charge path.

In this case, as the charge reduction parts 312a and 312b are provided in the semiconductor patterns 310a and 310b, the size of the thin film transistor may eventually increase. In this case, the semiconductor patterns 310a and 310b have at least one bent portion, thereby reducing the area occupied by the semiconductor patterns 310a and 310b in the pixel and increasing the surface area. That is, the semiconductor patterns 310a and 310b may have a 'U' shape.

In addition, a storage capacitor Cp is further disposed in each pixel P. FIG. Here, the storage capacitor Cp includes the first storage capacitor Cp1 and the second storage capacitor Cp2 overlapped with the interlayer insulating layer 340 therebetween. In this case, the first storage capacitor Cp1 may be formed of the same conductive material as the gate line 301.

In addition, the storage capacitor Cp may be a portion of the second storage capacitor Cp2 and the power line 303 and a protruding area of the power line 303 in the pixel area.

The passivation layer 370 is disposed on the substrate 300 covering the thin film transistor Tr. The passivation layer 370 may be formed of an inorganic insulating layer or an organic insulating layer. For example, the inorganic insulating film may be a silicon oxide film, a silicon nitride film and a stacked film thereof. The organic insulating film may be a polyamide resin, a polyimide resin, an acrylic resin, or the like.

The passivation layer 370 has a contact hole exposing a portion of the driving thin film transistor Tr2.

An organic light emitting diode E is disposed on the passivation layer 370 and electrically connected to the driving thin film transistor Tr2 through the contact hole.

In detail, the first electrode 380 electrically connected to the drain electrode 314b through the contact hole is disposed on the passivation layer 370. The first electrode 380 may be patterned for each pixel.

The organic light emitting layer 390 is disposed on the first electrode 380. The organic light emitting layer 390 generates light by recombining the first charge provided from the first electrode 380 and the second charge provided from the second electrode 400 to be described later. Thus, the light forms an image provided to the user.

The first electrode 380 may be formed of a transparent conductive film, a light reflective conductive film, or a double film thereof. For example, the light transmissive conductive layer may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or gallium (Ga) -based compound. The light reflecting conductive film may be Pt, Au, Ir, Cr, Mg, Ag, Ni, Al, or an alloy thereof.

The organic light emitting layer 390 is disposed on the first electrode 380. The organic light emitting layer 390 receives the first charge and the second charge from the first electrode 380 and the second electrode 400, which will be described later, to generate light.

The second electrode 400 is disposed on the organic light emitting layer 390. The second electrode 400 may be used in common for all the pixels. That is, the second electrode 400 may be integrally formed in all the pixels. The second electrode 400 may be made of one material selected from the group consisting of Mg, Ca, Al, Ag, and alloys thereof.

In addition, in the organic light emitting diode display, a pixel isolation pattern 385 defining a pixel may be further formed on the first electrode 380. The pixel isolation pattern 385 has a lattice opening that exposes the first electrode 380 when viewed in plan view. That is, the pixel isolation pattern 385 surrounds the edge portion of the first electrode 380 and is disposed on the substrate 300. As a result, the pixel isolation pattern 385 prevents the first electrode 380 and the second electrode 400 from shorting. This is because charges are concentrated at the edge portion of the first electrode 380, so that the organic light emitting layer 390 interposed between the edge portion of the first electrode 380 and the second electrode 400 may deteriorate.

In addition, an outer portion of the substrate 300 may further include a circuit thin film transistor (not shown) for controlling each pixel. For example, the circuit thin film transistor may serve to dissipate static electricity generated inside or outside the display area for displaying an image. Alternatively, the circuit thin film transistor may serve as a switch for supplying a signal to the thin film transistor in the pixel.

As a result, since the circuit thin film transistor requires fast charge mobility, the semiconductor pattern of the circuit thin film transistor is formed of polysilicon. In addition, unlike the thin film transistor provided in the pixel, the semiconductor pattern includes a channel portion, a source portion, and a drain portion except for the charge deceleration portion.

Accordingly, in the exemplary embodiment of the present invention, an organic light emitting diode display having uniform luminance may be provided by providing a thin film transistor having uniform electrical characteristics.

As described above, the thin film transistor according to the present invention forms a semiconductor pattern with polysilicon to improve the electrical characteristics of the thin film transistor, but has a charge deceleration portion that can lower the charge mobility inside the semiconductor pattern, so that the electrical conductivity between the thin film transistors is reduced. The characteristic deviation was reduced.

In addition, by providing thin film transistors having uniform characteristics in the organic light emitting diode display, the organic light emitting diode display can reduce the response speed and driving voltage, and provide an organic light emitting diode display having a uniform image quality. .

Although described above with reference to embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the invention described in the claims below. You will understand.

Claims (22)

A channel portion, a source portion and a drain portion respectively connected to both sides of the channel portion, interposed between at least one of the source portion and the drain portion and the channel portion to reduce the mobility of charges moving from the source portion to the drain portion; A semiconductor pattern having a charge reduction unit; A gate insulating film covering the semiconductor pattern; A gate electrode on the gate insulating layer corresponding to the channel portion; An interlayer insulating film covering the gate electrode and disposed on the gate insulating film; A source electrode provided on the interlayer insulating film and electrically connected to the source part; And And a drain electrode provided on the interlayer insulating layer and electrically connected to the drain portion. The method of claim 1, The source and drain portions have a first resistance, and the charge deceleration portion has a second resistance higher than the first resistor. The method of claim 1, And the channel portion has a first length and the charge deceleration portion has a second length greater than or equal to the first length. The method of claim 1, The semiconductor pattern is a thin film transistor, characterized in that having a 'U' shape when viewed in plan. The method of claim 1, The thin film transistor of claim 1, wherein the charge deceleration part of the semiconductor pattern includes at least part of a curved bent part when viewed in a plan view. The method of claim 1, The channel portion has a length equal to the length of the gate electrode. The method of claim 1, And the source portion includes impurities of a first content and the charge deceleration portion includes impurities of a second content smaller than the first content. The method of claim 1, The charge reducer includes a stacked first charge reducer and a second charge reducer characterized in that the thin film transistor. 9. The method of claim 8, And the first charge reduction part is made of polysilicon, and the second charge reduction part is made of amorphous silicon. The method of claim 9, The source and drain portions include a first impurity and the second charge deceleration portion further comprises a second impurity. Forming a preliminary semiconductor pattern on the substrate; Forming a gate insulating layer on the substrate to cover the preliminary semiconductor pattern; Forming a gate electrode on the gate insulating layer corresponding to the preliminary semiconductor pattern; Impurities are implanted into the preliminary semiconductor pattern using the gate electrode as a mask, and at least one of a channel portion corresponding to the gate electrode, a source portion and a drain portion connected to both sides of the channel portion, and the source portion and the drain portion, respectively. Forming a semiconductor pattern having a charge deceleration portion interposed between the channel portion and the channel portion to decelerate the mobility of the charge moving from the source portion to the drain portion; Forming an interlayer insulating film covering the gate electrode on the gate insulating film; And And forming a source electrode electrically connected to the source portion and a drain electrode electrically connected to the drain portion on the interlayer insulating layer. The method of claim 11, Forming the semiconductor pattern Forming a photoresist pattern on the gate electrode having at least twice the area of the gate electrode; Implanting impurities into the preliminary semiconductor pattern using the photoresist pattern as a mask to form the source and drain portions; Removing the photoresist pattern; And And forming the charge deceleration part and the channel part using the gate electrode as a mask. The method of claim 11, And the channel portion has a first length and the charge deceleration portion has a second length greater than or equal to the first length. The method of claim 11, And the source and drain portions have a first resistance, and the charge deceleration portion has a second resistance higher than the first resistance. The method of claim 11, Before forming the preliminary semiconductor pattern on the substrate Forming an amorphous silicon film on the substrate; Crystallizing the amorphous silicon film to form a polysilicon film; And And forming a preliminary semiconductor pattern by patterning the polysilicon layer. A preliminary semiconductor having a channel region, a source region and a drain region respectively connected to both sides of the channel region on a substrate, and having a first charge deceleration portion interposed between at least one of the source region and the drain region and the channel region; Forming a pattern; Forming a second charge reducer on the first charge reducer of the preliminary semiconductor pattern; Forming a gate insulating layer on the substrate, the gate insulating layer covering the preliminary semiconductor pattern on which the second charge reduction unit is formed; Forming a gate electrode on the gate insulating layer corresponding to the channel region; Implanting impurities into the preliminary semiconductor pattern using the gate electrode as a mask to form the source region, the drain region, and the channel region as source, drain, and channel portions to form a semiconductor pattern; Forming an interlayer insulating film on the gate insulating film covering the gate electrode; And And forming a source electrode electrically connected to the source portion and a drain electrode electrically connected to the drain portion on the interlayer insulating film. 17. The method of claim 16, Forming the preliminary semiconductor pattern Forming an amorphous silicon film on the substrate; Crystallizing the amorphous silicon film to form a polysilicon film; And And patterning the polysilicon film to form a preliminary semiconductor pattern. 17. The method of claim 16, Forming the second deceleration unit Forming amorphous silicon on the preliminary semiconductor pattern, the amorphous silicon having another impurity having different characteristics from that of the impurity; And And patterning the amorphous silicon to form the second charge reduction part. A charge disposed on a substrate and interposed between a channel portion, a source portion and a drain portion connected to both sides of the channel portion, and at least one of the source portion and the drain portion and the channel portion and moving from the source portion to the drain portion. A semiconductor pattern having a charge decelerating portion that reduces mobility; A gate insulating layer covering the semiconductor pattern and disposed on the substrate; A gate electrode on the gate insulating layer corresponding to the channel portion; An interlayer insulating film covering the gate electrode and disposed on the gate insulating film; A source electrode provided on the interlayer insulating film and electrically connected to the source part; A drain electrode provided on the interlayer insulating film and electrically connected to the drain part; A passivation layer covering the source electrode and the drain electrode and provided on the interlayer insulating layer; And And an organic light emitting diode disposed on the passivation layer and electrically connected to the drain electrode. 20. The method of claim 19, And the source and drain portions have a first resistance, and the charge deceleration portion has a second resistance higher than the first resistance. 20. The method of claim 19, And a circuit thin film transistor provided on the periphery of the substrate and including a circuit semiconductor pattern having a channel portion, a source portion, and a drain portion. 22. The method of claim 21, And the circuit semiconductor pattern is made of polysilicon.

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