KR101296635B1 - A liquid crystal display device and a method for aligning pads of the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of increasing the number of output pads of a gate integrated circuit and preventing malfunction due to misalignment between the output pads and input pads of the panel, wherein n (n is a natural number) gates A liquid crystal panel comprising lines; N input pads formed on one side of the n gate line and arranged in a zigzag shape; It has n + p output pads arranged in a zigzag form (p is a natural number), and n output pads are selected according to a selection signal from the outside, and scan pulses are applied to each of the input pads through the selected n output pads. And a first gate integrated circuit for supplying.

LCD, output pad, gate integrated circuit, COG, zigzag

Description

A liquid crystal display device and a method for aligning pads of the same}

1 illustrates a conventional gate integrated circuit.

2 is a view illustrating a liquid crystal display device according to a first embodiment of the present invention.

FIG. 3 is a diagram for explaining inconsistency between an arrangement of output pads and an arrangement of input pads. FIG.

4 is a view for explaining a contact failure between the output pad and the input pad caused by the mismatch between the arrangements described in FIG.

5 is a view illustrating a liquid crystal display device according to a second embodiment of the present invention

6 illustrates a case in which the arrangement of the output pads and the arrangement of the input pads are symmetrical;

7A and 7B illustrate a method for aligning an output pad and an input paddle in FIG. 6.

8 illustrates a detailed configuration diagram of the gate integrated circuit;

9 illustrates a liquid crystal display according to a third embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

201: gate integrated circuit OP: output pad

IP: Input Pad GL: Gate Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an increase in the number of output pads of a gate integrated circuit and to prevent malfunction due to misalignment between the output pads and input pads of the panel, and a method of arranging the pads thereof. It is about.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

The driving circuit includes a gate integrated circuit for driving gate lines and a data driver for driving data lines.

1 is a diagram illustrating a conventional gate integrated circuit.

The conventional gate integrated circuit 101 includes a plurality of output pads 120 arranged in one direction, as shown in FIG.

A plurality of gate lines GL is formed in the liquid crystal panel, and an input pad 130 is formed at one side of each gate line GL. Each input pad 130 is electrically connected to each output pad 120. The number of the input pad 130 and the output pad 120 is the same.

The gate integrated circuit 101 outputs scan pulses through the respective output pads 120. The output scan pulse is supplied to the gate line GL through the input pad 130. Thus, the gate line GL is driven.

As the liquid crystal display becomes larger, more gate lines GL are formed in the liquid crystal panel. In order to drive such a large number of gate lines GL, it is advantageous to form the maximum number of output pads 120 in the gate integrated circuit 101 to thin the liquid crystal display device.

However, since there is a limit in narrowing the distance between the output pads 120, it is difficult to form a large number of output pads 120 in the gate integrated circuit 101.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a liquid crystal display device and a method for arranging the pads thereof in which a large number of output pads can be formed in a gate integrated circuit by arranging the output pads in a zigzag form. There is this.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel including n gate lines (n is a natural number); N input pads formed on one side of the n gate line and arranged in a zigzag shape; It has n + p output pads arranged in a zigzag form (p is a natural number), and n output pads are selected according to a selection signal from the outside, and scan pulses are applied to each of the input pads through the selected n output pads. And a first gate integrated circuit for supplying.

In addition, the pad alignment method of the liquid crystal display device according to the present invention for achieving the above object, the liquid crystal panel comprising n (n is a natural number) gate lines; N input pads formed on one side of the n gate line and arranged in a zigzag shape; A pad alignment method of a liquid crystal display device, comprising: a first gate integrated circuit having n + 1 output pads arranged in a zigzag form and supplying scan pulses to the input pads through the n output pads; Comparing the arrangement of the pads with the arrangement of the output pads; When the arrangement of the input pads and the arrangement of the output pads match, the first to nth output pads are selected. When the arrangement of the input pads and the arrangement of the output pads do not match, the second to n + 1 Selecting output pads; And supplying a scan pulse to the selected output pads.

Hereinafter, a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view illustrating a liquid crystal display device according to a first embodiment of the present invention.

As shown in FIG. 2, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel (not shown) including a plurality of gate lines GL1 to GLn, and the gate lines GL1 to GLn. Gate integrated circuit 201 for driving the circuits in turn.

The liquid crystal panel further includes a plurality of data lines (not shown), which are arranged on the liquid crystal panel to intersect the gate lines GL1 to GLn.

The liquid crystal display according to the first exemplary embodiment of the present invention further includes a data driver (not shown) for driving the data lines.

A thin film transistor (not shown) is formed around the gate lines GL1 to GLn and the data lines intersect each other.

Pixel electrodes (not shown) are formed in each pixel area defined by the gate lines GL1 to GLn and the data lines.

The thin film transistor is connected to gate lines GL1 to GLn, a data line, and the pixel electrode. The thin film transistor is turned on in response to a scan pulse from the gate lines GL1 to GLn. Through the turned-on thin film transistor, a data signal from a data line is supplied to the pixel electrode.

The gate integrated circuit 201 includes a plurality of output pads OP1 to OPn. The output from the gate integrated circuit 201 is output through the output pads OP1 to OPn.

That is, the gate integrated circuit 201 outputs scan pulses through the respective output pads OP1 to OPn. The output scan pulses are supplied to the gate lines GL1 to GLn through the input pads IP1 to IPn of the liquid crystal panel. Therefore, each gate line GL1 to GLn is sequentially driven.

The output pads OP1 to OPn are arranged in a zigzag form.

That is, the output pads OP1 to OPn may be divided into first output pads OP1, OP3,..., And OPn-1 and second output pads OP2, OP4,..., And OPn. . The first output pads OP1, OP3,..., OPn-1 are arranged in one direction at regular intervals.

The second output pads OP2, OP4,..., And OPn are positioned at one side of the first output pads OP1, OP3,. The second output pads OP2, OP4,..., OPn are arranged in one direction at regular intervals.

In this case, the second output pads OP2, OP4,..., OPn are positioned between the first output pads OP1, OP3,..., OPn-1 that are adjacent to each other. OP3, ..., OPn-1) are formed on one side.

The input pads IP1 to IPn are also arranged in a zigzag form. The number of output pads OP1 to OPn and the number of input pads IP1 to IPn are the same.

The output pads OP1 to OPn are formed under the gate integrated circuit 201. 2 shows the gate integrated circuit 201 as viewed from above, and the output pads OP1 to OPn are not actually seen. However, for convenience of description, the output pads OP1 to OPn are shown to be visible.

FIG. 2 shows a situation before the output pads OP1 to OPn and the input pads IP1 to IPn contact each other, and each of the output pads OP1 to OPn contacts each of the input pads IP1 to IPn. As a result, the gate integrated circuit 201 and the gate lines GL1 to GLn are electrically connected to each other.

As such, the first output pads OP1, OP3,... And OPn-1 are positioned between the first output pads OP1, OP3,. By forming the second output pads OP1, OP3,... And OPn-1 so as to be located at one side of the output pads OP1, OP3,..., OPn-1, the gate integrated circuit 201 is formed in the present invention. It is possible to form a larger number of output pads (OP1 to OPn) as compared to the conventional while maintaining the length of.

The gate integrated circuit 201 is mounted on a liquid crystal panel by a gate on chip (COG) method.

On the other hand, if the arrangement of the input pads IP1 to IPn and the arrangement of the output pads are not the same, the following problems may occur.

FIG. 3 is a diagram for explaining inconsistency between the arrangement of the output pads and the arrangement of the input pads, and FIG. 4 is for explaining a contact failure between the output pad and the input pad caused by the inconsistency between the arrangements described in FIG. 3. Drawing.

As shown in FIG. 3, the arrangement of the output pads OP1 to OPn and the arrangement of the input pads IP1 to IPn are symmetrical to each other.

In this state, when the output pads OP1 to OPn and the input pads IP1 to IPn are stacked on each other, as shown in FIG. 4, the output pads OP1 to OPn and the input pads IP1 to IPn. Poor contact between them occurs.

That is, as shown in FIG. 4, each output pad OP1 to OPn comes into contact with two adjacent input pads IP1 to IPn. Accordingly, there is a problem that the scan pulse is not output correctly.

5 is a view illustrating a liquid crystal display device according to a second embodiment of the present invention.

As shown in FIG. 5, the liquid crystal display according to the second exemplary embodiment of the present invention includes a liquid crystal panel in which a plurality of gate lines GL1 to GLn are formed, and a gate for driving the gate lines GL1 to GLn. An integrated circuit 501 is included.

The gate integrated circuit 501 includes a plurality of output pads OP1 to OPn + 1 arranged in a zigzag form, and the number of the output pads OP1 to OPn + 1 is equal to that of the gate lines GL1 to GLn. More than numbers. For example, as shown in FIG. 5, the number of the output pads OP1 to OPn + 1 is one more than the number of the gate lines GL1 to GLn.

The gate integrated circuit 501 receives a gate start pulse GSP and shifts it to output the scan pulse.

Input pads IP1 to IPn are formed at one side of the gate lines GL1 to GLn, and the number of the input pads IP1 to IPn is equal to the number of the gate lines GL1 to GLn. The input pads IP1 to IPn and the gate lines GL1 to GLn are electrically connected to each other.

The input pads IP1 to IPn are also arranged in a zigzag form, and the output pads OP1 to OPn + 1 are also arranged in a zigzag form.

The number of the output pads OP1 to OPn + 1 is one more than the number of the input pads IP1 to IPn. The arrangement of the remaining output pads OP1 to OPn except for one output pad OPn + 1, that is, the output pad OPn + 1 located at the bottom of the output pads OP1 to OPn + 1, It is similar to the arrangement of the input pads IP1 to IPn. That is, the output pads OP1 to OPn and the input pads IP1 to IPn have a zigzag shape, but the arrangement of the output pads OP1 to OPn and the arrangement of the input pads IP1 to IPn. Are symmetrical to each other.

The gate integrated circuit 501 selects n output pads among the n + 1 output pads OP1 to OPn + 1 according to the selection signal SEL supplied to the gate integrated circuit 501. That is, n output pads are selected except for any one output pad.

The gate integrated circuit 201 operates as follows according to the logic state of the selection signal SEL.

That is, when the selection signal SEL is in a high logic state, the gate integrated circuit 201 may include first to nth output pads OP1 to OPn among n + 1 output pads OP1 to OPn + 1. Select them. The scan pulses are sequentially supplied to the selected first to nth output pads OP1 to OPn. The scan pulses supplied to the first through nth output pads OP1 through OPn are transmitted to the first through nth input pads IP1 through IPn, and the first through nth input pads IP1 through IPn. The scan pulses transmitted to the fields are sequentially supplied to the first to nth gate lines GL1 to GLn.

When the selection signal SEL is in a low logic state, the gate integrated circuit 201 may include second through n + 1 output pads OP2 through n + 1 output pads OP1 through OPn + 1. OPn + 1). The scan pulses are sequentially supplied to the selected second to n + 1th output pads OP2 to OPn + 1. The scan pulses supplied to the second to n + 1th output pads OP2 to OPn + 1 are transmitted to the first to nth input pads IP1 to IPn, and the first to nth input pads ( The scan pulses transmitted to the IP1 to IPn are sequentially supplied to the first to nth gate lines GL1 to GLn.

FIG. 5 illustrates a case in which the arrangement of the output pads OP1 to OPn and the arrangement of the input pads IP1 to IPn are the same. In this case, the first to nth output pads of the gate integrated circuit 201 are shown. OP1 to OPn correspond to the first to nth input pads IP1 to IPn, respectively.

Therefore, when the gate integrated circuit 501 is bonded to the liquid crystal panel, the first to nth output pads OP1 to OPn and the first to nth input pads IP1 to IPn of the gate integrated circuit 201 are bonded to each other. Are respectively bonded.

Here, the n + 1th output pad OPn + 1 does not contact any of the input pads IP1 to IPn.

When the gate integrated circuit 501 and the liquid crystal panel are bonded to each other, when the gate start pulse GSP and the high logic selection signal SEL_H are supplied to the gate integrated circuit 501, the first to nth output pads may be provided. Scan pulses are sequentially output from (OP1 to OPn), and no scan pulses are output from the n + 1th output pad OPn + 1.

FIG. 6 illustrates a case in which the arrangement of the output pads and the arrangement of the input pads are symmetrical.

7A and 7B are views for explaining a method for aligning an output pad and an input paddle in FIG. 6.

First, as shown in FIG. 7A, the gate integrated circuit 501 is moved toward the liquid crystal panel to bond the gate integrated circuit 501 to the liquid crystal panel. Then, the first to nth output pads OP1 to OPn and the first to nth input pads IP1 to IPn of the gate integrated circuit 501 may not be properly bonded. That is, each of the output pads OP1 to OPn cannot be joined to the corresponding input pads IP1 to IPn. In addition, each output pad OP1 to OPn is bonded to two adjacent input pads IP1 to IPn.

Thereafter, as illustrated in FIG. 7B, the gate integrated circuit 501 is pushed upward so that the n + 1th output pad OPn + 1 is aligned with the nth input pad IPn. Accordingly, as the first to nth output pads OP1 to OPn are all moved upward, the kth output pad (k is a natural number of two or more) and the k-1th input pad are aligned and contacted. In this case, the first output pad OP1 does not contact any of the input pads IP1 to IPn.

As such, when the gate integrated circuit 501 and the liquid crystal panel are bonded to each other, when the gate start pulse GSP and the selection logic SEL_L in the low logic state are supplied to the gate integrated circuit 201, the second to nth Scan pulses are sequentially output from the +1 output pads OP2 to OPn + 1, and no scan pulses are output from the first output pad OP1.

For such an operation, the gate integrated circuit 201 has a configuration as follows.

8 is a diagram illustrating a specific configuration of the gate integrated circuit.

As illustrated in FIG. 8, the gate integrated circuit 201 controls the shift register 816 for sequentially outputting the scan pulse and the output of the shift register 816 according to the selection signal SEL from the outside. It includes a control unit 815 for.

The shift register 816 includes a plurality of stages ST1 to STn + 1. Each stage ST1 to STn + 1 outputs scan pulses, and in this case, scan pulses are sequentially output from the uppermost stages ST1 to STn + 1 to the lower stages ST1 to STn + 1.

The number of stages ST1 to STn + 1 is equal to the number of output pads OP1 to OPn + 1, and each stage ST1 to STn + 1 is output through the output lines OL1 to OLn + 1. It is connected to the pads OP1 to OPn.

At least two clock pulses having different phases are supplied to each stage ST1 to STn + 1.

Each stage ST1 to STn + 1 is enabled by receiving scan pulses from the preceding stages ST1 to STn + 1, and the enabled stage ST1 to STn + 1 uses one clock pulse. Generate a scan pulse.

Each stage ST1 to STn + 1 disables itself using the other clock pulse.

The control unit 815 selects n stages to generate an output from among n + 1 stages ST1 to STn + 1 according to the logic state of the selection control signal. The gate start pulse GSP is supplied to the stage located at the top of the selected n stages.

That is, when the high logic selection signal SEL_H is supplied, the controller 815 selects the first to nth stages ST1 to STn. The gate start pulse GSP is supplied to the first stage ST1 located at the uppermost side among the selected stages ST1 to STn.

Then, the first stage ST1 is enabled by the gate start pulse GSP. That is, it becomes a state which can output a scan pulse. Thereafter, when a first clock pulse is supplied to the first stage ST1, the enabled first stage ST1 outputs a first clock pulse. The output first clock pulse is the first scan pulse. The first scan pulse is supplied to the first output pad OP1 and to the next stage, that is, the second stage ST2.

Then, when the second stage ST2 is enabled, and then a second clock pulse is supplied to the second stage ST2, the enabled second stage ST2 outputs a second clock pulse. . The output second clock pulse is the second scan pulse. The second scan pulse is supplied to the second output pad OP2 and to the next stage, that is, the third stage ST3.

Here, when the second stage ST2 outputs the second scan pulse, the second clock pulse is supplied to the front stage, that is, the first stage ST1, and the first stage ST1 is disabled. .

In this manner, the first to nth stages ST1 to STn sequentially output the first to nth scan pulses, and the first to nth scan pulses are output to the first to nth output pads OP1 to OPn. Supply.

The first to nth scan pulses supplied to the first to nth output pads OP1 to OPn are sequentially supplied to the first to nth gate lines GL1 to GLn.

When the selection signal SEL_L in the low logic state is supplied, the controller 815 selects second to n + 1 stages ST2 to STn + 1. The gate start pulse GSP is supplied to the second stage ST2 located at the uppermost side of the selected stages ST2 to STn + 1.

Then, the second stage ST2 is enabled by the gate start pulse GSP. That is, it becomes a state which can output a scan pulse. Thereafter, when a second clock pulse is supplied to the second stage ST2, the enabled second stage ST2 outputs a second clock pulse. The output second clock pulse is the first scan pulse. The first scan pulse is supplied to the second output pad OP2 and to the next stage, that is, the third stage ST3.

Then, when the third stage ST3 is enabled, and after the first clock pulse is supplied to the third stage ST3, the enabled third stage ST3 outputs the first clock pulse. . The output first clock pulse is the second scan pulse. The second scan pulse is supplied to the third output pad OP3 and to the next stage, that is, the fourth stage ST4.

Here, when the third stage ST3 outputs the second scan pulse, the first clock pulse is supplied to the front stage, that is, the second stage ST2, and the second stage ST2 is disabled. .

In this manner, the second to n + 1 stages ST2 to STn + 1 sequentially output the first to nth scan pulses, and output the first to nth scan pulses to the second to n + 1th output pads. It is supplied to (OP2 to OPn + 1).

The first to nth scan pulses supplied to the second to n + 1th output pads OP2 to OPn + 1 are sequentially supplied to the first to nth gate lines GL1 to GLn.

The controller 815 includes a first switching device SW1, a second switching device SW2, and a selector 855.

The first switching device SW1 supplies a gate start pulse GSP to the first stage ST1 in response to the high logic select signal SEL_H.

The second switching device SW2 supplies the scan pulse from the nth stage STn to the n + 1th stage STn + 1 in response to the low logic select signal SEL_L.

The selector 855 supplies a scan pulse from the first stage ST1 to the second stage ST2 in response to the high logic select signal SEL_H, and selects the low logic select signal SEL_L. In response to), the gate start pulse GSP is supplied to the second stage ST2.

The switching device may be a metal oxide semiconductor (MOS) transistor or a bipolar transistor.

The control unit 815 configured as described above operates as follows.

When the high logic selection signal SEL is supplied to the first and second switching devices SW1 and SW2, the first switching device SW1, which is an N-type metal oxide semiconductor (NMOS) switching device, is turned on. The second switching device SW2, which is a P-type metal oxide semiconductor (PMOS) switching device, is turned off.

The gate start pulse GSP is supplied to the first stage ST1 through the turned-on first switching device SW1. Accordingly, the first stage ST1 is enabled.

The enabled first stage ST1 then outputs a first scan pulse, which is supplied to the selector 855.

A high logic selection signal SEL_H is also supplied to the selector 855, where the selector 855 receives the first scan pulse in a second stage in response to the high logic selection signal SEL_H. It is supplied as it is to ST2. That is, when the selection signal SEL is in a high logic state, the selection unit 855 supplied with the selection signal SEL may input the scan pulse from the first stage ST1 to the second stage ST2. It serves to form a signal transmission path between the first stage ST1 and the second stage ST2.

On the other hand, since the second switching device SW2 is turned off, the scan pulse from the nth stage STn is blocked from being supplied to the n + 1th stage STn + 1.

Therefore, when the selection signal SEL is in a high logic state, the first to nth stages ST1 to STn sequentially output the first to nth scan pulses, and the n + 1th stage STn + 1 ) Does not output a scan pulse.

When the low logic selection signal SEL_L is supplied to the first and second switching devices SW1 and SW2, the first switching device SW1, which is an NMOS switching device, is turned off and the second switching device which is a PMOS switching device. SW2 is turned on.

Since the first switching device SW1 is turned off, input of the gate start pulse GSP to the first stage ST1 is blocked.

The scan pulse from the nth stage STn may be supplied to the n + 1th stage STn + 1 through the turned-on second switching device SW2.

A select logic SEL_L of a low logic state is also supplied to the selector 855, where the selector 855 generates a second gate start pulse GSP in response to the select signal SEL_L of the low logic state. Supply to the stage ST2 as it is. That is, when the selection signal SEL is in a low logic state, the selection unit 855 supplied with the selection signal SEL may input the gate start pulse GSP from the outside to the second stage ST2. A signal transfer path is formed between the input terminal to which the GSP is input and the second stage ST2.

The second stage ST2 enabled by the gate start pulse GSP then outputs a first scan pulse, and the first scan pulse is supplied to the third stage ST3.

Thereafter, the third to n + 1th stages ST3 to STn + 1 sequentially output scan pulses.

Therefore, when the selection signal SEL is in a high logic state, the second to n + 1th stages ST2 to STn + 1 sequentially output the first to nth scan pulses, and the first stage ST1. Does not output a scan pulse.

The gate integrated circuit 201 configured as described above is mounted on a liquid crystal panel using a gate on chip (COG) method.

9 illustrates a liquid crystal display according to a third exemplary embodiment of the present invention.

The liquid crystal display according to the third exemplary embodiment of the present invention has a plurality of gate integrated circuits 901a and 901b, as shown in FIG. For example, the liquid crystal display according to the third embodiment of the present invention has first and second gate integrated circuits 901a and 901b.

The first and second gate integrated circuits 901a and 901b divide and drive k gate lines GL1 to GLk formed in the liquid crystal panel, where k is a natural number and k = n + m.

Each gate integrated circuit 901a and 901b may drive the same number of gate lines, or may drive different numbers of gate lines.

Each gate integrated circuit 901a, 901b has a larger number of output pads than the number of gate lines assigned to it.

For example, the first gate integrated circuit 901a may have one more n + 1 output pads OP1 to OPn + 1 than the n gate lines GL1 to GLn assigned thereto. The two gate integrated circuit 901b may have one more m + 1 output pads OP1 to OPm + 1 than the m gate lines GLn + 1 to GLm assigned thereto.

The first gate integrated circuit 901a has the same configuration as the gate integrated circuit 501 according to the second embodiment of the present invention.

Of course, the second gate integrated circuit 901b also has the same configuration as the gate integrated circuit 501 according to the second embodiment of the present invention described above, and the second gate integrated circuit 901b has the first gate integrated circuit. The last scan pulse output from 901a is supplied as the gate start pulse GSP.

That is, when the first to nth stages ST1 to STn of the first gate integrated circuit 901a are driven, scan pulses from the nth stage STn are transferred to the second gate integrated circuit 901b. It is supplied as a gate start pulse GSP. When the second to n + 1th stages ST2 to STn + 1 of the first gate integrated circuit 901a are driven, the scan pulse from the n + 1th stage STn + 1 is driven to the first gate integrated circuit 901a. The two gate integrated circuit 901b is supplied as a gate start pulse GSP.

The second gate integrated circuit 901b is also supplied with the selection signal SEL, and selects the first to nth stages ST1 to STn or the second to nth according to the logic state of the selection signal SEL. Select the +1 stage ST2 to STn + 1.

The first and second gate integrated circuits 901a and 901b configured as described above are mounted on a liquid crystal panel using a gate on chip (COG) method.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display according to the present invention as described above has the following effects.

Using the liquid crystal display device according to the embodiment of the present invention, even if the arrangement of the output pads of the gate integrated circuit and the arrangement of the input pads of the liquid crystal panel are inconsistent, the output pads and the input pads can be properly aligned. Scan pulses from each output pad can be supplied precisely to the corresponding input pad.

Claims (9)

a liquid crystal panel comprising n gate lines (n is a natural number); N input pads formed on one side of the n gate line and arranged in a zigzag shape; It has n + p output pads arranged in a zigzag form (p is a natural number), n output pads are selected according to a selection signal from the outside, and scan pulses are applied to each input pad through the selected n output pads. A first gate integrated circuit for supplying; P is 1; The first gate integrated circuit selects first to nth output pads when the selection signal from the outside is in a high logic state, and supplies scan pulses to the selected first to nth output pads in sequence; And, The first gate integrated circuit selects second to n + 1 output pads when the selection signal from the outside is in a low logic state, and sequentially scans pulses to the selected second to n + 1 output pads. Liquid crystal display, characterized in that for supplying. delete delete The method of claim 1, The first gate integrated circuit, N + 1 stages for supplying a scan pulse to the n + 1 output pads; And According to the selection signal, n stages among the n + 1 stages are selected, a start pulse is supplied to a stage located at the first stage of the selected n stages, and a scan pulse is generated from one stage not selected. And a controller which controls the stages so that they are not output. 5. The method of claim 4, The control unit provided in the first gate integrated circuit, When the selection signal is in a high logic state, selects first to nth stages to supply a start pulse to the first stage, and controls the n + 1 stage not to output a scan pulse; And, When the selection signal is in a low logic state, selects second to n + 1 stages to supply a start pulse to the second stage, and controls the first stage not to output a scan pulse; . 6. The method of claim 5, The control unit provided in the first gate integrated circuit, A first switching device for supplying a start pulse to the first stage in response to a selection signal of a high logic state; A second switching device for supplying scan pulses from the nth stage to the n + 1th stage in response to the low logic selection signal; And And a stage selector configured to supply a scan pulse from the first stage to a second stage in response to the high logic selection signal and to supply the start pulse to a second stage in response to the low logic select signal. Liquid crystal display device characterized in that. The method of claim 1, The liquid crystal panel, m gate lines (m is a natural number); M input pads formed on one side of the m gate lines and arranged in a zigzag shape; And M + q output pads (q is a natural number) arranged in a zigzag form, m output pads are selected according to a selection signal from the outside, and scan pulses are applied to each of the input pads through the selected m output pads. Further comprising a second gate integrated circuit for supplying; And the second gate integrated circuit receives the last scan pulse output from the first gate integrated circuit as a start pulse. The method according to claim 1 or 7, And the first and second gate integrated circuits are mounted on the liquid crystal panel in a chip on gate (COG) manner. a liquid crystal panel comprising n gate lines (n is a natural number); N input pads formed on one side of the n gate line and arranged in a zigzag shape; A pad alignment method of a liquid crystal display device, comprising: a first gate integrated circuit having n + 1 output pads arranged in a zigzag shape and supplying scan pulses to the respective input pads through the n output pads; Comparing the arrangement of the input pads with the arrangement of the output pads; When the arrangement of the input pads and the arrangement of the output pads match, the first to nth output pads are selected. Selecting second to n + 1 output pads when the arrangement of the input pads and the arrangement of the output pads do not match; And And supplying scan pulses to the selected output pads.

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