KR101294094B1 - Memory Device and access method of the same - Google Patents

Abstract

A memory device and a method of access thereof are disclosed. According to an embodiment of the present invention, a memory device includes a PMOS transistor and an NMOS transistor connected between a power supply voltage and an inversion voltage of a global word line, and is configured by decoding a predetermined number of lower bits of a block address and a row address. A first inverter that inputs a group line and inverts a logic level of the local group line; And a local word line decoder including a second inverter for inverting an output of the first inverter and activating a local word line to be connected.

Description

Memory device and access method of the same

The present invention relates to a memory device and an access method thereof, and more particularly, to a memory device and an access method thereof, which can improve the operation speed and reduce power consumption while reducing the layout area.

As the degree of integration of the memory device increases, the layout area, the operating speed, and the power consumption of the memory device become an issue. In particular, increasing the density of memory devices increases the repetitive arrangement of local wordline decoders for accessing memory cells, and seeks to reduce the increase in layout area, lower operating speed, and increased power consumption by local wordline decoders. Should be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device and an access method thereof capable of improving the operation speed and reducing the power consumption while reducing the layout area despite the repetitive arrangement of the local wordline decoder.

According to an aspect of the present invention, a memory device includes a PMOS transistor and an NMOS transistor connected between a power supply voltage and an inversion voltage of a global word line, and includes a lower number of predetermined numbers of block addresses and row addresses. A first inverter configured to invert a logic level of the local group line by inputting a local group line set by decoding a bit; And a local word line decoder including a second inverter for inverting an output of the first inverter and activating a local word line to be connected.

The first inverter may be smaller in size than the second inverter.

The second inverter activates the connected local word line to logic high when the local group line is applied to logic high after the inversion voltage of the global word line is applied to the logic low. .

The memory device further includes a global inverter for inverting the voltage of the global word line, wherein the threshold voltage of the NMOS transistor of the global inverter is higher than the threshold voltage of the NMOS transistor of the first inverter.

The memory device may further include a global wordline decoder to decode the global wordline and a local groupline decoder to decode the local groupline, the power supply voltages of the global wordline decoder and the local groupline decoder, The power supply voltage of the local word line decoder may be applied separately.

The memory device may be a static random access memory (SRAM).

The memory device may include a plurality of blocks, and the local wordline driver may be shared by two of the plurality of blocks.

A method of accessing a memory device according to an embodiment of the present invention for solving the above technical problem, the method comprising: decoding a global word line by decoding bits excluding a predetermined number of lower bits of a row address; Decoding a predetermined number of lower bits and block addresses of a row address to activate a local group line; Inverting a logic level of the activated local group line in response to an inversion voltage of the global word line; And a second inverting step of activating a local word line corresponding to the row address by inverting a logic level according to the first inverting result.

The first inverting step may consume less current than the second inverting step.

According to the memory device and the access method thereof according to the embodiment of the present invention, by providing the local word line decoder as a multi-stage inverter having different driving capabilities, it is possible to realize a small area and achieve a high operating speed. This minimizes the load on the local group line, which reduces the power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a block diagram schematically illustrating a local wordline decoder according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a memory device according to an exemplary embodiment of the present invention.
3 is a view illustrating a portion of the memory device of FIG. 2 in more detail.
4 is a block diagram illustrating a memory card according to an exemplary embodiment of the present invention.
5 is a block diagram illustrating a computing system device according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an," and "the" include plural forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, regions and / or regions, it should be understood that these elements, components, regions, layers and / Do. These terms are not intended to be in any particular order, up or down, or top-down, and are used only to distinguish one member, region or region from another member, region or region. Thus, the first member, region or region described below may refer to a second member, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing.

1 is a block diagram schematically illustrating a local wordline decoder according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a local word line decoder LWDEC according to an embodiment of the present invention includes a first inverter IVT1 and a second inverter IVT2. The first inverter IVT1 is gated by the connected local group line BXL, and is connected between the power supply voltage VDD and the inversion voltage / GWL of the global word line. The second inverter IVT2 is gated by the output of the first inverter IVT1 and activates the corresponding local word line LWL.

When the global word line is activated, the inversion voltage / GWL of the global word line transitions to a logic low, is connected to the source of the NMOS transistor n1 of the first inverter IVT1, and the local group line BXL. ) Is connected to the gate of the first inverter (IVT1). At this time, the output of the first inverter IVT1 becomes the logic low by the local group line BXL of the logic high. Since the second inverter IVT2 having the output of the logic low of the first inverter IVT1 as the input outputs a logic high, the local word line LWL connected to the local wordline decoder LWDEC is activated. This will be described in more detail.

The local word line decoder LWDEC according to an embodiment of the present invention may be included in the memory device MDEV shown in FIG. 2. When the memory device MDEV according to the embodiment of the present invention is an SRAM, the local word line decoder LWDEC may be provided between two blocks each consisting of memory cells (not shown). For example, one local wordline decoder LWDEC is provided between the first block BLK1 and the second block BLK2, and the other local wordline decoder LWDEC is k-1 (k is an integer of 4 or more). ) May be provided between the block BLKk-1 and the k-th block BLKk. Referring to FIG. 2, a method of accessing a memory device MDEV according to an embodiment of the present invention will be described. By an address received from an external device (eg, a host or a memory controller), a specific memory cell of the memory device MDEV may be accessed. Since a memory cell of the memory device MDEV is connected to a word line and a bit line, the address may include a row address indicating a word line and a column address indicating a bit line to which the memory cell to be accessed is connected. In addition, the address may further include a block address for a block including a memory cell to be accessed.

2 shows an example in which the row address RAdr consists of x bits (x is an integer of 2 or more). The global word line decoder GWDEC of the memory device MDEV may include the bits RAdr [x: x−a + 1] except for the lower a (a is an integer greater than or equal to 1) bits among the row addresses RAdr. Activate a global word line corresponding to one of GWL1 to GWLn (n is an integer of 2 or more).

A plurality of local word lines may be connected to each of the global word lines. For example, four local word lines of each of the blocks BLK1 to BLKk may be connected to the first global word line GWL1. For example, if the memory device MDEV includes k blocks as shown in FIG. 2, the first global word line GWL1 includes the first blocks BLK1 to k-th blocks BLKk. Each of four local word lines LWL_1-1 to LWL1-4, ..., LWL_k-1 to LWLk-4 may be connected. For example, the local word lines of the first block BLK1, which are connected to the first global word line GWL1, are LWL1-1 to LWL1-4, and the local word lines of the second block BLK2 are LWL2-1. To LWL2-4.

Each of the local word lines of each block is connected to a corresponding local group line. For example, the local word lines LWL1-1 to LWLn-1 of the first block BLK1 are connected to the local group line BXL1-1, and the local word lines LWL1-2 to LWLn-2 of the first block BLK1 are connected. It can be connected to the local group line BXL1-2. Similarly, local word lines LWL1-3 to LWLn-3 of the first block BLK1 are connected to a local group line BXL1-3, and local word lines LWL1-4 to LWLn-4 of the first block BLK1 are a local group. Can be connected to line BXL1-4.

As such, the local group lines are provided for each block by the number of local word lines connected to one global word line in each block. For example, four local group lines BXL1-1 to BXL1-4 of the first block BLK1 are provided. Similarly, four local group lines BXL2-1 to BXL2-4 of the second block BLK2 are provided.

2, among the plurality of local word lines connected to one global word line, decoding is performed by the lower a bit RAdr [xa: 1] and the block address BAdr of the row address RAdr. Local wordline is activated. FIG. 2 illustrates an example in which some of the bits of the row address RAdr are separated and transmitted to the global wordline decoder GWDEC and the remaining bits of the row address RAdr are transmitted to the local group line decoder BXD. It is not limited to this.

In order to activate one local word line of a specific block among a plurality of local word lines connected to one global word line, the memory device MDEV according to an embodiment of the present invention may be a local group line decoder BXD, and the above-described method. Local word line decoder (LWDEC).

The local group line decoder BXD decodes the lower a bit RAdr [x-a: 1] and the block address BAdr of the row address RAdr to activate the corresponding local group line BXL. 2 shows an example in which four local group lines are provided for each block. However, the local group line decoder BXD may be provided between two blocks, like the local word line decoder LWDEC.

As described above, the local word line decoder LWDEC activates the corresponding local word line according to the voltage of the local group line and the global word line being activated. That is, the local word line decoder LWDEC applies a write voltage or a read voltage to a local word line to which a memory cell to be accessed is connected.

In other words, the global word line corresponding to the row address is activated by the global word line decoder, the block and the local group line corresponding to the row address are activated by the local group line decoder, and the same global word is activated by the local word line decoder. The activated block among the local word lines connected to the line and the local word line connected to the local group line are activated, thereby accessing the memory cell connected to the local word line corresponding to the row address. As the write voltage or the read voltage is applied to the local word line activated in this manner, data may be written to the memory cell or data stored in the memory cell may be read.

Hereinafter, the structure and operation of the local wordline decoder according to the embodiment of the present invention will be described in more detail.

3 is a view illustrating a portion of the memory device of FIG. 2 in more detail.

Referring to FIG. 3, the first inverter IVT1 of the local word line decoder LWDEC of the memory device MDEV according to the embodiment of the present invention is gated by a connected local group line, and the power supply voltage ( VMOS) and a PMOS transistor p1 and an NMOS transistor n1 connected between the inversion voltage / GWL of the global word line. For example, the first inverter IVT1 of the fourth local wordline decoder LWDEC4 of the i (i is an integer of 1 or more k) blocks BLKi is gated by the fourth local group line LWL4, It is connected between the power supply voltage VDD and the inversion voltage / GWLj of the jth global word line.

The second inverter IVT2 of the local word line decoder LWDEC is gated by the output of the first inverter IVT1, and the PMOS transistor p2 is connected between the power supply voltage VDD and the ground voltage VSS. And an NMOS transistor n2. The local word line corresponding to the output of the second inverter IVT2 is connected. For example, the output of the second inverter IVT2 of the fourth local wordline decoder LWDEC4 of the i-th block BLKi is connected to the fourth local wordline LWL4.

In this case, the first inverter IVT1 may be smaller than the second inverter IVT2. A large number of memory cells MC are connected to each of the local word lines LWL. Each memory cell MC includes, for example, a latch including a pair of inverters that are cross-coupled when the memory device MDEV according to an embodiment of the present invention is an SRAM. And a pair of NMOS pass transistors connecting the two latch rods and the bit line pay (BL / BLB).

The capacitive and resistive loads of the transistors of the memory cell MC and the local wordline itself are very large. Furthermore, as described above, the number of memory cells connected to each local word line is significant. Despite this load, in order to drive at high speed, the second inverter IVT2 can be designed with a large driving capability. On the other hand, since the first inverter IVT1 only needs to drive a gate load of the second inverter IVT2, the first inverter IVT1 may be designed to have a smaller size than the second inverter IVT2. The small size of the first inverter IVT1 reduces the load of the local group line BXL having the largest capacitive load in the memory device MDEV, for example, SRAM, and is implemented with only one inverter. While a large number of memory cells are connected to drive a large load local wordline, the current consumption can be significantly reduced compared to a local wordline decoder that must drive both a global wordline or a local groupline load.

In addition, the local word line decoder LWDEC according to an exemplary embodiment of the present invention includes a first inverter IVT1 having a small number of transistors, so that the local word line decoder LWDEC has a larger number of transistors than NAND. Speed can be improved. In particular, the NMOS transistor n1 of the first inverter IVT1 according to the embodiment of the present invention may further improve the operation speed by having a relatively low threshold voltage. On the other hand, the NMOS transistor n3 included in the global inverter GIVT that inverts the voltage of the global word line may have a relatively high threshold voltage in order to reduce off current. In this case, the threshold voltage of the NMOS transistor n1 of the first inverter IVT1 does not affect the off current. Alternatively, in order to reduce the off current, the gate length of the NMOS transistor n3 included in the global inverter GIVT according to the embodiment of the present invention is equal to the gate of the NMOS transistor n1 of the first inverter IVT1. It can be longer than long.

When the local group line BXL is activated but the global word line GWL is deactivated, since the source power of the NMOS transistor n1 of the first inverter IVT1 is not supplied, the local group line BXL is turned off. Since the output remains logic high, the output of the second inverter IVT2 becomes logic low. Therefore, the local word line LWL connected to the local word line decoder LWDEC remains in an off state.

In the local word line decoder LWDEC of this structure, the leakage current of the first inverter IVT1 is determined by the NMOS transistor n3 of the global inverter GIVT, which is activated before the local group line BXL. This is because the threshold voltage of the NMOS transistor n1 of the first inverter IVT1 can be optimized for the operation speed.

In addition, since the inversion voltage / GWL of the global word line is connected to the source of the NMOS transistor n1 of the first inverter IVT1 of the local word line decoder LWDEC, the local word line decoder The power supply voltage may be set differently from the power supply voltage of the global word line decoder. That is, the power supply voltage of the local word line decoder LWDEC may be supplied separately from the power supply voltages of the global word line decoder GWDEC and the local group line decoder BXD.

As described above, the local word line decoder according to the embodiment of the present invention may have various advantages, such as improving the operation speed and reducing the current consumption while reducing the layout area of the memory device. .

4 is a block diagram illustrating a memory card according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a memory card MCRD according to an embodiment of the present invention includes a memory controller Ctrl and a memory device MDEV. The memory device MDEV may be an SRAM. The memory controller Ctrl controls data writing to the memory device MDEV or data reading from the memory device MDEV in response to a request from an external host (not shown) received through the input / output means I / O. . The memory device MDEV of FIG. 4 may include the local wordline decoder of FIGS. 1 to 3. Therefore, according to the computing system CSYS according to the embodiment of the present invention, it is possible to reduce the layout area and to improve the operation speed and reduce the power consumption.

The memory card MCRD of FIG. 4 may be a compact flash card (CFC), a microdrive, a microdrive, a smart media card (SMC), a multimedia card (MMC), or a secure digital card (SDC). It may be implemented as a security digital card, a memory stick, or a USB flash memory driver.

5 is a block diagram illustrating a computing system device according to an exemplary embodiment of the present invention.

The computing system CSYS according to an embodiment of the present invention includes a processor (CPU), a user interface (UI), and a memory system (MSYS) electrically connected to a bus (BUS). The memory system MSYS includes a memory controller Ctrl and a memory device MDEV. The memory device MDEV of the memory system MSYS of FIG. 5 may include the local wordline decoder of FIGS. 1 to 3. Therefore, according to the computing system CSYS according to the embodiment of the present invention, it is possible to reduce the layout area and to improve the operation speed and reduce the power consumption.

The computing system CSYS according to an embodiment of the present invention may further include a power supply device PS. When the computing system CSYS according to the embodiment of the present invention is a mobile device, a modem such as a battery and a baseband chipset for supplying an operating voltage of the computing system may be additionally provided. In addition, it is common knowledge in the art that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system CSYS according to the embodiment of the present invention. This is obvious to those who have learned, so a detailed description is omitted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms are employed herein, they are used for purposes of describing the present invention only and are not used to limit the scope of the present invention.

For example, the above description has been given to an example in which the local word line decoder according to the embodiment of the present invention includes two inverters, but is not limited thereto. The local wordline decoder according to the embodiment of the present invention may have various advantages while having the advantages described above.

Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (9)

A local group line having a PMOS transistor and an NMOS transistor connected between a power supply voltage and an inverted voltage of a global word line, the local group line being set by decoding a predetermined number of lower bits of a block address and a row address, A first inverter for inverting the logic level of the first inverter; And
And a second inverter for inverting the output of the first inverter and activating a local word line to be connected. The method according to claim 1,
And the first inverter is smaller in size than the second inverter. The method of claim 1, wherein the second inverter,
And when the local group line is applied to the logic high after the inversion voltage of the global word line is applied to the logic low, the connected local word line is activated to the logic high. . The method according to claim 1,
The memory device further includes a global inverter for inverting the voltage of the global word line,
The threshold voltage of the NMOS transistor of the global inverter is higher than the threshold voltage of the NMOS transistor of the first inverter. The method according to claim 1,
The memory device further includes a global inverter for inverting the voltage of the global word line,
And a gate length of the NMOS transistor of the global inverter is longer than that of the NMOS transistor of the first inverter. The memory device of claim 1, wherein the memory device comprises:
A global wordline decoder for decoding the global wordline and a local groupline decoder for decoding the local groupline,
And a power supply voltage of the global word line decoder and the local group line decoder and a power supply voltage of the local word line decoder are separately applied. The memory device of claim 1, wherein the memory device comprises:
A memory device, characterized in that it is a static random access memory (SRAM). In the memory device access method,
Decoding the global word line by decoding the bits except the predetermined number of lower bits of the row address;
Decoding a predetermined number of lower bits and block addresses of a row address to activate a local group line;
Inverting a logic level of the activated local group line in response to an inversion voltage of the global word line; And
And a second inverting step of activating a local word line corresponding to the row address by inverting a logic level according to the first inverting result. The method of claim 8,
The first inverting step consumes less current than the second inverting step.

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