KR101284220B1 - An etching method for through silicon via of acute type semiconductor wafer - Google Patents

Abstract

PURPOSE: A method for etching a through silicon via using an acute type semiconductor wafer is provided to minimize the physical and chemical damage generated in the edge of a semiconductor wafer by using a nitride layer for protecting the edge of the acute type semiconductor wafer. CONSTITUTION: A back grinding process on an acute type semiconductor wafer is performed (S100). An oxidation process is performed on the front surface of an acute semiconductor wafer to form an oxide layer (S200). A nitridation process is performed on the oxide layer to form a nitride layer (S300). The nitride layer and the oxide layer are patterned to form an etch mask pattern (S400). A through via hole is formed in the acute semiconductor wafer by using the etch mask pattern (S500). [Reference numerals] (AA) Start; (BB) End; (S100) Wafer back grounding; (S200) Oxidation process (forming an oxide layer); (S300) Forming a nitride layer; (S400) Forming an etch mask pattern; (S500) Forming a through via hole by a wet etching process

Description

An etching method for through silicon via of acute type semiconductor wafer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, through-through for forming through silicon via (TSV) on a semiconductor wafer made of silicon material used as an interposer. A method of etching via holes. The semiconductor wafer used as the interposer may use a dummy wafer handled in a semiconductor device manufacturing process.

In the past, semiconductor chips were generally electrically connected to a printed circuit board (PCB) for a semiconductor package, which is a basic frame of the semiconductor package, through a wire or a bump. Recently, however, development of high-performance semiconductor packages such as stacked packages, multichip packages (MCPs), and system in packages (SIPs) has been actively developed. Accordingly, the development of three-dimension (3D) packaging technology for mounting more semiconductor chips in a single semiconductor package in a vertical direction has been actively developed. At this time, the semiconductor chips mounted in the vertical direction are mounted on the semiconductor package substrate while being electrically connected to each other through a TSV instead of a conventional wire or bump. In addition, the semiconductor chip may be mounted on a semiconductor package substrate by using an interposer including a separate TSV between the semiconductor chips disposed up and down. In this case, the interposer may be a silicon material, and may have a redistribution line (RDL) formed therein.

The vertical connection of the semiconductor chip through the TSV can shorten the signal connection path to improve the electrical characteristics of the semiconductor package, reduce the size of the semiconductor package, and ultimately reduce the bandwidth of the semiconductor device. There is an advantage that can be increased. Therefore, to develop 3D packaging technology, a stable TSV formation method is urgently needed.

SUMMARY OF THE INVENTION The technical problem of the present invention is to achieve a through silicon via an acute angle semiconductor wafer capable of suppressing physical / chemical damage occurring at the edge of a semiconductor wafer during a semiconductor wafer etching process for forming a through silicon via (TSV). To provide a via (TSV) etching method.

According to an aspect of the inventive concept, a through silicon via (TSV) etching method using an acute angle semiconductor wafer includes preparing an acute angle semiconductor wafer having an acute angle between a bottom surface and a side surface of an edge, Forming an oxide film by performing an oxidation process, forming a nitride film in contact with the oxide film on an entire surface of the acute semiconductor wafer on which the oxide film is formed, to protect an edge of the acute semiconductor wafer, and patterning the nitride film and the oxide film forming an etch mask pattern by patterning and forming a through via hole in the acute semiconductor wafer using the etch mask pattern.

According to an exemplary embodiment of the present invention, the acute semiconductor wafer may be a back grinding of the bottom surface by more than half of the original thickness.

According to an experimental embodiment of the present invention, the oxide film preferably has a thickness in the range of 1000 to 3000 GPa, and the nitride film preferably has a thickness in the range of 2000 to 4000 GPa.

In this case, the method of forming the nitride film is preferably formed by a low pressure chemical vapor deposition (LPCVD) method.

According to a preferred embodiment of the present invention, the method of forming the through via hole may be formed by wet etching using potassium hydroxide (KOH) etching solution.

Therefore, according to the technical idea of the present invention described above, in the etching process of forming the through via hole in the acute-angle semiconductor wafer to form the TSV, an oxide film formed by an oxidation process is first formed, and a nitride film used as a hard mask for the oxide film is formed. Form. Accordingly, in the etching process, the adhesion of the nitride layer may be strengthened at the edge of the acute semiconductor wafer, thereby improving the physical / chemical damage problem during the etching.

1 is a flowchart illustrating a through silicon via (TSV) etching method using an acute angle semiconductor wafer according to a preferred embodiment of the present invention.
2 to 7 are cross-sectional views illustrating a through silicon via (TSV) etching method using an acute angle semiconductor wafer according to a preferred embodiment of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the constituent elements are shown enlarged for the sake of convenience of explanation, and the proportions of the constituent elements may be exaggerated or reduced.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a flowchart illustrating a through silicon via (TSV) etching method using an acute angle semiconductor wafer according to a preferred embodiment of the present invention.

Referring to FIG. 1, a back grinding process for a semiconductor wafer is performed (S100). At this time, the semiconductor wafer is polished from the bottom, and thus the angle of the bottom surface and the side surface of the edge of the semiconductor wafer is an acute angle (an acute angle). Such acute semiconductor wafers generally have a relatively high probability of physical / chemical damage at the edge, and are effective in suppressing physical / chemical damage at the edge of the present invention. The acute semiconductor wafer is suitably used for an interposer, and may be used by recycling a dummy wafer handled in a semiconductor device manufacturing process. The dummy wafer may be a wafer that places the wafer on the top and bottom of the loading apparatus, such as a boat used in semiconductor wafer processing equipment.

Subsequently, an oxidation process is performed on the acute semiconductor wafer (S200). As a result, an oxide film is formed on the surface of the acute semiconductor wafer. Thereafter, a nitride film is formed on the oxide film by low pressure chemical vapor deposition (LPCVD) to form a nitride film (S300). That is, in order to protect the edges of the acute semiconductor wafer, a nitride film is formed on the entire surface of the acute semiconductor wafer on which the oxide film is formed in contact with the oxide film. Subsequently, a photoresist pattern is formed on the nitride layer to etch the nitride layer and the oxide layer below to form an etching mask pattern for etching through via holes in the acute semiconductor wafer (S400). Thereafter, the photoresist pattern is removed, and wet etching is performed using the etching mask pattern to form through via holes penetrating the acute semiconductor wafer (S500).

In this case, the oxide film makes the crystal structure of the nitride film more dense, thereby improving the function of the hard mask on the nitride film, and the etching mask formed of the composite film of the oxide film and the nitride film may improve the adhesion between the acute semiconductor wafer. Therefore, it plays a role of suppressing damage occurring in the wet etching process at the edge of the acute semiconductor wafer.

2 to 7 are cross-sectional views illustrating a through silicon via (TSV) etching method using an acute angle semiconductor wafer according to a preferred embodiment of the present invention.

2 and 3, first, an acute semiconductor wafer 100 is prepared. The acute semiconductor wafer 100 may be a silicon wafer for an interposer used to arrange semiconductor chips in a vertical direction in a manufacturing process of a semiconductor package. In addition, an integrated circuit may or may not be formed on the front surface T of the acute semiconductor wafer 100. In general, silicon wafers are rounded off by the manufacturer and delivered to the user.

Subsequently, a back grinding process is performed on the acute semiconductor wafer 100. In the drawing, reference numeral 102 denotes a portion where the bottom surface of the acute semiconductor wafer 100 is removed by a back grinding process. Here, if more than half of the thickness of the original silicon wafer is back-grinded, the bottom surface (X axis) and the side surface (Y axis) of the edge form an acute angle (θ of FIG. 3) as shown in part 104 of FIG. 3. Becomes

Referring to FIG. 4, an oxidation process is performed on the entire surface of the acute semiconductor wafer 100. The oxidation process may be a thermal oxidation process, or may be a high pressure oxidation process in which oxidation is performed at a pressure higher than atmospheric pressure in order to lower the process temperature. At this time, the thickness of the oxide film 106 grown on the entire surface of the acute semiconductor wafer 100 by the oxidation process is suitably in the range of 1000 to 3000 kPa. The oxide film 106 is acute semiconductor wafer when the temperature of the reaction chamber is set to about 1000 ° C., the acute semiconductor wafer 100 is introduced, and the oxidation process is performed for about 20 minutes while supplying water vapor and nitrogen (N 2) gas. An oxide film 106 having a thickness of about 2000 μs may be formed on the entire surface of the 100. The oxide film 106 prevents contaminants from contaminating the surface of the acute semiconductor wafer 100 from the outside, and creates a new surface state as the oxide film 106 grows downward with the silicon wafer in the oxidation process.

This surface state serves to suppress the occurrence of damage at the edge of the acute semiconductor wafer 100 by making the crystal structure of the nitride film made in the subsequent process more dense.

Referring to FIG. 4, a nitriding process is performed on an acute semiconductor wafer 100 on which the oxide film 106 is formed to form a nitride film 108 used as a hard mask on the oxide film 106.

The nitriding process may be a low pressure chemical vapor deposition (LPCVD) process. Specifically, while the pressure of the chamber (chamber) at a temperature of about 760 ℃ to maintain a pressure of about 100 mTorr, the xylene (DCS) gas and ammonia (NH 3) gas is flowed into the chamber for about 100 minutes. As a result, a nitride film 108 having a thickness of 3000 Å with excellent mechanical strength as a dielectric and suitable for use as a hard mask can be obtained.

In this case, when the nitride film 108 is formed directly on the acute semiconductor wafer 100 without forming an oxide film in advance, when the nitride film 108 grows more densely and is used as a hard mask in a subsequent process, Can effectively suppress contamination or damage.

On the other hand, the nitride film 108, in order to solve the problem that the nitride film 108 is not properly deposited on the edge in the low-pressure chemical vapor deposition process may be formed twice each with a thickness of 1500 kW. At this time, forming the acute-angle semiconductor wafer 100 while turning in the chamber is advantageous to solve the problem that the nitride film 108 is not properly deposited at the edge.

Referring to FIG. 6, a photoresist pattern 110 is formed on an acute semiconductor wafer 100 on which the nitride film 108 is formed. In this case, the photoresist pattern 110 may be formed on upper and lower surfaces of the acute semiconductor wafer 100 on which the nitride film 108 is formed. The photoresist pattern 110 may have a structure that exposes a tooth in which a through via hole is to be formed to the outside. Subsequently, the lower nitride layer 108 and the oxide layer 106 are etched using the photoresist pattern 110 as an etching mask. In this case, the nitride film 108 and the oxide film 106 may be collectively etched using a high performance plasma etching equipment such as an inductively coupled plasma (ICP) etcher. After the removal of the photoresist pattern 110 by an ashing process and the cleaning process, the hard mask 112 including the composite film of the oxide film 106 and the nitride film 108 is formed on the acute semiconductor wafer 100. Is formed.

Referring to FIG. 7, wet etching is performed on the acute semiconductor wafer 100 on which the hard mask 112 is formed to form a through via hole 114 penetrating through the acute semiconductor wafer 100. The wet etching, 33 ± 5 wt% of potassium hydroxide (hereinafter referred to as 'KOH') can be used as an etchant, a solution mixed with water and isopropyl alcohol (isopropyl alcohol), the wet etching is in progress Temperature can advance in the temperature range of 80 +/- 3 degreeC. The wet etching can reduce the manufacturing cost because the through via hole 114 can be formed through a relatively simple process without using expensive process equipment as compared with dry etching. In addition, the etched surface is smoother than dry etching, and it is an environmentally friendly manufacturing process because it does not use harmful chemicals.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

100: acute semiconductor wafer, 102: polished surface,
104: frame, 106: oxide film,
108: nitride film, 110: photoresist pattern,
112: hard mask, 114: through via hole.

Claims (6)

Preparing an acute semiconductor wafer having an acute angle between a bottom surface and a side surface of an edge;
Performing an oxidation process on an entire surface of the acute semiconductor wafer to form an oxide film;
Forming a nitride film in contact with the oxide film on an entire surface of the acute semiconductor wafer on which the oxide film is formed to protect the edges of the acute semiconductor wafer;
Patterning the nitride layer and the oxide layer to form an etch mask pattern; And
And forming a through via hole in the acute semiconductor wafer by using the etching mask pattern. delete The method of claim 1,
The oxide film,
A through-silicon via (TSV) etching method using an acute angle semiconductor wafer, characterized in that the thickness is in the range of 1000 ~ 3000Å. The method of claim 1,
The method of forming the nitride film,
A through silicon via (TSV) etching method using an acute angle semiconductor wafer, characterized in that formed by low pressure chemical vapor deposition (LPCVD). The method of claim 1,
The nitride film,
A through-silicon via (TSV) etching method using an acute-angle semiconductor wafer, characterized in that the thickness is in the range of 2000 ~ 4000Å. The method of claim 1,
The method of forming the through via hole,
A through silicon via (TSV) etching method using an acute angle semiconductor wafer, characterized in that the wet etching using a potassium hydroxide (KOH) etchant.

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