KR101275068B1 - Method of fabricating the array substrate for in-plane switching mode liquid crystal display device - Google Patents

Abstract

The present invention provides a semiconductor device comprising: a gate line and a common line of a double layer structure formed in a pixel area including a switching area and extending in one direction and spaced apart from each other; A double layer gate pad electrode connected to an end of the gate line on the substrate; A plurality of common electrodes having a plurality of single layer structures formed in the pixel area on the substrate by branching from the common wiring; A plurality of single-layered pixel electrodes formed alternately in parallel with common wirings of the plurality of single-layered structures in the pixel area on the substrate, and connected at both ends thereof; A double layer gate electrode formed in the switching region on the substrate and connected to the gate wiring; A first gate pad contact hole formed over the boundary of each pixel region, the switching region, and the gate pad electrode, and exposing the gate pad electrode on both sides of the gate pad electrode; A gate insulating film having a pixel contact hole exposing an end of one of the plurality of pixel electrodes; A double layer data line formed on the gate insulating layer to cross the gate line to define the pixel area; A data pad electrode formed on the gate insulating layer so as to be connected to one end of the data line, a central portion having a single layer structure, and both sides having a double layer structure; A gate auxiliary pad electrode contacting the gate pad electrode of the double layer structure over the gate insulating layer through the first gate pad contact hole, a central portion thereof having a single layer structure, and both ends thereof having a double layer structure; A semiconductor layer formed in the switching region over the gate insulating film; A double layer source electrode connected to the data line over the semiconductor layer, and a double layer drain electrode spaced apart from the source electrode on the semiconductor layer and contacting one of the plurality of pixel electrodes through the pixel contact hole. and; A central portion having a single layer structure covering the switching region and the data line and formed at a boundary between each pixel region and at the same time covering a double layer structure corresponding to the gate auxiliary pad electrode and the data pad electrode. Correspondingly, an array substrate for a transverse field type liquid crystal display device having a second gate pad contact hole and a data pad contact hole exposing them and including a protective layer formed thereon and a method of manufacturing the same are provided.

        4 mask, array board, liquid crystal, transverse electric field, bad pad

Description

Method for fabricating the array substrate for in-plane switching mode liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field type liquid crystal display device. In particular, a transverse electric field type liquid crystal display device through a four mask process capable of preventing contrast ratio reduction and defects in wavy noise through suppressing step generation, and further preventing contact failure of the pad part. It relates to a method for manufacturing an array substrate for use.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate having a common electrode, an array substrate having pixel electrodes, and a liquid crystal interposed between the two substrates. As a result, the liquid crystal is driven and is excellent in characteristics such as transmittance and aperture ratio.

However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9, .

The common electrode 17 and the pixel electrode 30 are formed on the lower substrate 10 on the same plane. In this case, the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30. It is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field type liquid crystal display device.

First, referring to FIG. 2A, which illustrates an arrangement of liquid crystals in an on state where a voltage is applied, a phase change of a liquid crystal 11a at a position corresponding to the common electrode 17 and the pixel electrode 30 is performed. Although the liquid crystal 11b positioned in the section between the common electrode 17 and the pixel electrode 30 is formed by a horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, It is arranged in the same direction as the horizontal electric field (L). That is, since the liquid crystal is moved by the horizontal electric field in the transverse electric field type liquid crystal display device, the viewing angle becomes wide.

Thus, as seen the lateral jeongyehyeong liquid crystal display device from the front, the up / down / left / right direction in the direction of about 80~85 ^o can be seen without reversal.

Next, referring to FIG. 2B, since no voltage is applied to the liquid crystal display, a horizontal electric field is not formed between the common electrode 17 and the pixel electrode 30 and the arrangement state of the liquid crystal layer 11 does not change. Do not.

3 is a cross-sectional view of one pixel area including a thin film transistor of a conventional array substrate for a transverse electric field type liquid crystal display device.

As illustrated, in the pixel region P, a plurality of common electrodes 44a and 44b are formed on the substrate 40 so as to be spaced apart from each other, and a gate insulating film 46 is formed on the entire surface thereof. Although not shown in the drawing, the gate wires (not shown) extending in one direction along with the common electrodes 44a and 44b are connected to the common electrodes 44a and 44b, and the common wires are not shown. It is being formed.

In addition, a data line 52 defining a pixel region P is formed on the gate insulating layer 46 to intersect the gate line (not shown), and a protective layer is formed on the entire surface of the data line 52. And a plurality of pixels 54 formed on the passivation layer 54 so as to alternate with the common electrodes 44a and 44b formed under the gate insulating layer 46 in each pixel area P. Electrodes 59a and 59b are formed.

In the switching region TrA, the semiconductor layer 47 including the gate electrode 42, the gate insulating film 46, and the ohmic contact layer 47b spaced apart from the active layer 47a on the substrate 40. And a thin film transistor Tr having a structure in which source and drain electrodes 49 and 50 spaced apart from each other are sequentially stacked.

Meanwhile, the method of manufacturing the array substrate 40 for a transverse electric field type liquid crystal display device having such a configuration will be briefly described. After depositing a first metal material on the substrate 40, the gate electrode is formed by a first mask process. 42, gate wirings (not shown), common wirings (not shown), and common electrodes 44a and 44b are formed, and then a first inorganic insulating material is deposited to form a gate insulating film 46, and subsequently Pure amorphous silicon (a-Si) and impurity amorphous silicon (n + a-Si) are successively deposited on the gate insulating layer 46 to form a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown). . Subsequently, the pure and impurity amorphous silicon layer (not shown) is patterned by a second mask process to form an active layer 47a and an impurity amorphous silicon pattern (not shown) at the position covering the gate electrode 42. .

Next, a second metal material is deposited on the impurity amorphous silicon pattern (not shown), and then spaced apart from each other on the data line 52 and the impurity amorphous silicon pattern (not shown) by a third mask process. Source and drain electrodes 49 and 50 are formed. In this step, the ohmic contact layers 47b are formed to be spaced apart from each other by removing the impurity amorphous silicon pattern (not shown) in the spaced intervals using the source and drain electrodes 49 and 50 as masks. The semiconductor layer 47 including the ohmic contact layer 47b and the active layer 47a is formed by exposing the active layer 47a to form a channel. The gate electrode 42, the gate insulating layer 46, the semiconductor layer 47, the source and drain electrodes 49 and 50 form a thin film transistor Tr, which is a switching element.

Next, after the deposition of the second insulating material, a protective layer 54 having a drain contact hole 56 exposing a portion of the drain electrode 50 is formed by a fourth mask process, and then the protective layer 54. The pixel electrodes 59a and 59b are formed by depositing a transparent conductive material over the layer) and patterning the same by a fifth mask process.

As described above, in the conventional manufacturing process of the array substrate for a transverse electric field type liquid crystal display device, a five mask process is usually performed.

However, in the mask process, equipment is required for each deposition, exposure, development, and etching process. As the physical and chemical processes are repeated, more mask processes require more processing time, thereby lowering productivity and increasing manufacturing costs.

Recently, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device by a four mask process has been proposed to solve the problem caused by the progress of the five mask process.

However, as shown in FIG. 4, which is a cross-sectional view of one pixel region, the array substrate manufactured by the four mask process includes the semiconductor layer 69 and the source and drain electrodes 74 and 76 in the manufacturing method thereof. It is characterized by reducing one mask process by manufacturing through one mask process, but simultaneously patterning the semiconductor layer 69, the source and drain electrodes 74, 76 and the data wiring 72 through one mask process. As a result, a semiconductor pattern 70 including a first pattern 70a of pure amorphous silicon and a second pattern 70b of impurity amorphous silicon is formed under the data line 72, and in particular, the first pattern 70a. ) Is formed to have a width wider than that of the data line 82, thereby causing a problem in which the wavy noise is generated.

In recent years, as the wiring becomes very long due to the large area, problems such as signal delay have occurred.

Therefore, in order to solve these problems, recently, a double layer structure is formed by using copper (Cu) or a copper alloy, which is a low-resistance metal material, and another metal material for improving bonding properties. And dualizing the drain electrode and the active layer to form an active layer and an impurity amorphous silicon pattern corresponding to the gate electrode, forming a metal layer thereon, and patterning the source and drain electrodes, the common electrode, and the pixel electrode. It has been proposed a manufacturing method characterized in that, and then to form a protective layer.

However, in the gate pad of the array substrate formed by the above method, the contact resistance is increased or a contact failure is caused.

FIG. 5 is a plan view of a gate pad portion of an array substrate manufactured by a four-mask process in which the active layer and the source and drain electrodes are dualized, and FIGS. 6A to 6G are cut along the cutting line VI-VI of FIG. 5. Some manufacturing step-by-step process cross sections for one part.

As shown, the planar structure of the gate pad in an array substrate manufactured by a four-mask manufacturing process in which the semiconductor layer and the source and drain electrodes are formed by dualization is described as copper (or copper alloy) / molybdenum or copper (or copper). A gate pad electrode having a double layer structure of an alloy) / molybdenum titanium layer, and a gate auxiliary pad electrode having source and drain electrodes formed through a plurality of first gate pad contact holes provided in the gate pad electrode and the gate insulating layer The gate auxiliary pad electrode is exposed through the second gate pad contact hole provided in the protective layer.

However, the gate pad having the above-described configuration forms a gate pad electrode having a double layer structure in its manufacturing process, forms a gate insulating film having a plurality of first gate pad contact holes thereon, and has a double layer structure thereon. After forming the gate auxiliary pad electrode, the upper layer made of copper or a copper alloy is wet-etched to form the gate auxiliary electrode having a single layer structure in the gate auxiliary pad electrode to correspond to the first gate pad contact hole. As the upper layer of the gate pad electrode corresponding to the portion is partially etched, the contact characteristic is degraded or the contact resistance is increased, thereby causing a signal delay phenomenon of the gate wiring to which a signal voltage is applied.

In order to solve the above problems, in the present invention, an array substrate for a liquid crystal display device including a gate pad part having a structure in which contact characteristics are not degraded or partial etching does not occur and signal delay due to an increase in contact resistance does not occur. It aims at providing the manufacturing method of this.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention for achieving the above object is a double-layered gate wiring and common wiring formed in a pixel area including a switching region extending in one direction and spaced apart from each other; ; A double layer gate pad electrode connected to an end of the gate line on the substrate; A plurality of common electrodes having a plurality of single layer structures formed in the pixel area on the substrate by branching from the common wiring; A plurality of single-layered pixel electrodes formed alternately in parallel with common wirings of the plurality of single-layered structures in the pixel area on the substrate, and connected at both ends thereof; A double layer gate electrode formed in the switching region on the substrate and connected to the gate wiring; A first gate pad contact hole formed over the boundary of each pixel region, the switching region, and the gate pad electrode, and exposing the gate pad electrode on both sides of the gate pad electrode; A gate insulating film having a pixel contact hole exposing an end of one of the plurality of pixel electrodes; A double layer data line formed on the gate insulating layer to cross the gate line to define the pixel area; A data pad electrode formed on the gate insulating layer so as to be connected to one end of the data line, a central portion having a single layer structure, and both sides having a double layer structure; A gate auxiliary pad electrode contacting the gate pad electrode of the double layer structure over the gate insulating layer through the first gate pad contact hole, a central portion thereof having a single layer structure, and both ends thereof having a double layer structure; A semiconductor layer formed in the switching region over the gate insulating film; A double layer source electrode connected to the data line over the semiconductor layer, and a double layer drain electrode spaced apart from the source electrode on the semiconductor layer and contacting one of the plurality of pixel electrodes through the pixel contact hole. and; A central portion having a single layer structure covering the switching region and the data line and formed at a boundary between each pixel region and at the same time covering a double layer structure corresponding to the gate auxiliary pad electrode and the data pad electrode. Correspondingly, it includes a protective layer formed with a second gate pad contact hole and a data pad contact hole exposing them, respectively.

The electrode and the wiring of the double layer structure are both made of molybdenum (Mo) or molybdenum (MoTi), and the upper layer is made of copper (Cu) or a copper alloy.

A plurality of pixel electrodes and the common electrode constituting the single layer structure, and a portion of the gate auxiliary pad electrode and the data pad electrode forming a single layer are formed of molybdenum (Mo) or molybdenum (MoTi).

The drain electrode is formed to overlap the common wiring, so that the overlapping portion forms a storage capacitor.

In the method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention, a double layer structure is formed on a substrate on which a pixel region including a switching region is defined, and a gate line electrode extending in one direction and a gate pad electrode at an end thereof are formed. And a gate electrode connected to the gate wiring in the switching region, common wiring extending in parallel with the gate wiring, a common electrode having a plurality of double layer structures branched from the common wiring in the pixel region, and the common wiring. Forming a plurality of double layer pixel electrodes alternate with the electrodes; Sequentially forming a gate insulating film and a pure and impurity amorphous silicon layer over the gate wiring; Patterning the impurity and the pure amorphous silicon layer and a gate insulating layer thereunder to expose the gate pad electrode to both sides of the pixel contact hole exposing one end of the pixel electrode and the center portion of the gate pad electrode, respectively; Forming a gate pad contact hole, and forming an active layer and an impurity amorphous silicon pattern over the gate insulating layer in the switching region; A double layer structure is formed over the gate insulating layer, a data line defining the pixel region is formed to cross the gate line, a data pad electrode is formed at an end thereof, and the impurity amorphous silicon pattern of the switching region is formed on the impurity amorphous silicon pattern. Forming a source electrode connected to a data line and a drain electrode spaced apart from the source electrode and in contact with the pixel electrode through the pixel contact hole; Forming an ohmic contact layer under the source and drain electrodes by removing the impurity amorphous silicon pattern exposed between the source and drain electrodes; Forming a protective layer over the data line and patterning the protective layer to expose the plurality of pixel electrodes and the common electrode, and exposing a central portion of the gate auxiliary pad electrode and a central portion of the data pad electrode; And forming a single layer structure by performing wet etching to remove the plurality of pixel electrodes, the common electrode, the gate auxiliary pad electrode, and the data pad electrode having the double layer structure exposed to the outside of the protective layer by wet etching. Corresponding to the central portion of the gate auxiliary pad electrode exposed to wet etching, the gate insulating layer is interposed therebetween to prevent the central portion of the gate pad electrode from being exposed to the etchant for the wet etching.

A pixel contact hole exposing one end of the pixel electrode and a first gate pad contact hole exposing the gate pad electrode on both sides of the center portion of the gate pad electrode, the gate insulating layer being formed in the switching region The forming of the active layer and the impurity amorphous silicon pattern may include forming a first photoresist pattern having a first thickness on the impurity amorphous silicon layer corresponding to the gate electrode, and forming a portion of the pixel contact hole and the gate. Exposing the impurity amorphous silicon layer to correspond to both sides of the pad electrode, and forming a second photoresist pattern of a second thickness thinner than the first thickness to correspond to other regions; The pixel contact hole and the gate pad electrode exposing one end of the pixel electrode by etching the impurity amorphous silicon layer exposed to the outside of the first and second photoresist patterns, the pure amorphous silicon layer below the gate insulating film, and the gate insulating film Forming a first gate pad contact hole to expose; Removing the second photoresist pattern; Forming the island-like active layer and the impurity amorphous silicon pattern in the switching region by removing the impurity amorphous silicon layer exposed by removing the second photoresist pattern and the pure amorphous silicon layer thereunder; Removing the first photoresist pattern.

The electrode and the wiring of the double layer structure are both made of molybdenum (Mo) or molybdenum (MoTi), and the upper layer is made of copper (Cu) or a copper alloy.

In the present invention, the process efficiency can be improved by manufacturing the array substrate for the liquid crystal display device by performing the mask process four times, and the manufacturing cost of the array substrate for the transverse electric field type liquid crystal display device can be reduced by simplifying the process.

In addition, the semiconductor layer has a structure in which the island is formed in the switching region, and since the semiconductor pattern of the material constituting the semiconductor layer is not formed under the data wiring, there is an effect of fundamentally preventing wave noise.

In addition, since the gate pad electrode is not exposed to the etchant during the etching process of the gate auxiliary pad electrode disposed thereon, the gate pad electrode is not partially etched, and thus, the gate pad contact defect is also prevented at the source. Therefore, there is an effect of suppressing signal delay and the like.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

First, the planar and vertical structures of the array substrate for a liquid crystal display device according to the present invention will be described.

7 is a plan view of one pixel area of the array substrate according to the present invention, FIG. 8 is a plan view of a portion of the gate pad portion in which the gate pad electrode of the array substrate is formed, and FIG. 9 is according to the present invention. A plan view of a portion of the data pad portion on which the data pad electrode of the array substrate is formed. 10 is a cross-sectional view of a portion taken along the cutting line VII-Ⅹ of FIG. 7, FIG. 11 is a cross-sectional view of a portion taken along the cutting line ′-? Of FIG. 8, and FIG. 12 is a view of FIG. 9. It is sectional drawing about the part cut along the cutting line?-?. In this case, for convenience of description, an area in which the thin film transistor Tr is formed in each pixel area P is defined as a switching area TrA and an area in which the storage capacitor StgC is formed as a storage area StgA.

First, referring to FIGS. 7 and 10, in the transverse electric field type liquid crystal display array substrate 101 according to the embodiment of the present invention, a plurality of gates and data lines 103 and 138 intersect with each other. The common line 105 is formed to define the region P and penetrate the pixel region P to be parallel to the gate line 103.

In addition, the switching region TrA located in the pixel region P is connected to the gate wiring 103 and the data wiring 138, and has a gate electrode 108, a gate insulating film 118, an active layer 126a, and an upper portion thereof. The semiconductor layer 126 including the ohmic contact layers 126b spaced apart from each other, and the thin film transistor Tr including the source and drain electrodes 140 and 143 spaced apart from each other are formed. In this case, the gate electrode 108 is connected to the gate line 103 and the source electrode 140 to the data line 138, respectively.

In this case, the structure and shape of the thin film transistor Tr may be variously modified. For example, as shown in the drawing, a source electrode branched from the data line 138 is configured to have a “U” shape, and the drain electrode 143 is configured to be inserted into an opening of the “U” type source electrode. In this case, the channel structure may be formed to have a “U” shape, or the source and drain electrodes 140 and 143 may have a bar shape, and thus the channel may have an “I” shape.

In addition, in the pixel region P, a plurality of pixel electrodes 114 and a common electrode 111 are alternately formed and spaced apart from each other, and the plurality of pixel electrodes 114 are formed with the drain electrode 143 and the gate. It is connected through the pixel contact hole 119 provided in the insulating film (not shown), and both ends thereof are connected to the pixel electrode connecting portion 115. In addition, the plurality of common electrodes 111 are formed by branching directly on the common wiring 105.

The drain electrode 143 is formed to overlap the common wiring 105 to form the storage capacitor StgC using the gate insulating layer 118 interposed therebetween as a dielectric layer.

One end of the gate line 103 and the data line 138 extends to a gate and a data pad unit (not shown), respectively, and is connected to a gate pad electrode (not shown) and a data pad electrode (not shown), respectively. have.

8 and 11, in the gate pad part GPA, a gate pad electrode 116 is formed to be connected to the gate line (not shown), and the gate pad electrode 116 is disposed thereon. A gate auxiliary pad electrode 148 having a single layer structure is formed at a central portion of the second gate pad contact through a gate insulating layer (not shown), and a second gate pad contact exposing the gate auxiliary pad electrode 148 corresponding to the central portion thereof. A protective layer 170 is formed having a hole 172 (the contact hole provided in the gate insulating layer 118 first formed during the manufacturing process is referred to as a first gate pad contact hole 121).

In addition, the first gate pad exposing the gate pad electrode 116 by removing the gate insulating layer 118 on both sides thereof in a direction in which a gate line (not shown) extends with respect to the center portion of the gate pad electrode 116. A contact hole 121 is formed, and the gate auxiliary contacting the gate pad electrode 116 through each of the first gate pad contact holes 121 and forming a double layer structure of the lower layer 148a and the upper layer 148b. The pad electrode 148 is formed. In this case, the gate auxiliary pad electrode 148 of the double layer structure is covered by the protective layer 118 corresponding to both sides of the central portion.

In this case, a central portion of the gate pad portion GPA connected to an external driving circuit board (not shown) may form a second gate pat contact hole 172 having a single layer gate auxiliary pad electrode 148a formed in the protective layer. The gate auxiliary pad electrodes 148 (148a and 148b) having a double layer structure contact the gate pad electrode 116 and the first gate pad contact hole 121 with respect to both sides of the central portion. As a result, the gate auxiliary pad electrode 148 and the gate pad electrode 116 are electrically connected to each other, and a double layer structure is formed to correspond to the central portion of the exposed gate pad electrode 116 after removing the protective layer (not shown). Even when etching is performed to form a layer structure, the portion is in a state in which the gate pad electrode 116 is covered by a gate insulating film (not shown), so the portion is not affected by the etching. Each such as this do not occur. Therefore, the partial contact of the gate pad electrode upper layer 116b made of copper or copper alloy in the gate pad part GPA prevents an increase in contact failure or contact resistance with the gate auxiliary pad electrode 148. Able to know.

9 and 12, in the data pad part DPA, the data line (not shown) is connected to the gate insulating layer 118 and has a double layer structure of a lower layer 145a and an upper layer 145b. The data pad electrode 145 is formed, and an exposed portion of the data pad electrode 145 corresponding to the data pad contact hole 174 provided in the protective layer (not shown) is removed from the upper layer 145b. Characterized by forming a single layer structure consisting of only the lower layer (145a).

Hereinafter, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to an embodiment of the present invention having such a structure will be described.

13A to 13L are step-by-step process cross-sectional views of a part taken along the cutting line VII-VII of FIG. 7, and FIGS. 14A to 14L are step-by-step manufacturing steps of a part taken along the cutting line VII-VII of FIG. 8. It is process sectional drawing, FIG. 15A-FIG. 15M are process sectional drawing of the manufacturing step about the part which cut | disconnected FIG. 9 along cutting line XII-XII. In this case, for convenience of description, an area where the thin film transistor Tr is formed in each pixel area P is defined as a switching area TrA and an area where the storage capacitor StgC is formed as a storage area StgA.

13A, 14A and 15A, a first metal material such as molybdenum (Mo) or molybdenum (MoTi) is deposited on a transparent insulating substrate 101, for example, a substrate 101 made of glass or plastic. As a result, a first metal layer (not shown) is formed, and a second metal layer (not shown) is continuously formed by depositing copper (Cu) or a copper alloy, which is a low resistance metal material, on the top thereof.

Subsequently, by collectively or continuously patterning the second and first metal layers (not shown), the gate wiring (not shown) having a double layer structure and extending in one direction and the common wiring 105 (150a and 105b) are parallel with each other. And gate electrodes 108 (108a and 108b) having a double layer structure, which are simultaneously branched from the gate wiring (not shown) to the switching region TrA in each pixel region P, and the gate wiring (not shown). A gate pad electrode 116 (116a, 116b) having a double layer structure connected to the gate line (not shown) is formed in the gate pad part GPA having one end.

In addition, a plurality of double layered common electrodes 110 (110a and 110b) are formed in each pixel area P by being separated from the common wiring 105 of the double layered structure and spaced apart at regular intervals. The plurality of double layer pixel electrodes 113 (113a and 113b) are formed to be alternately spaced apart from the common electrode 110. In this case, the plurality of double layer pixel electrodes 113 may be formed such that the ends thereof are all connected by the pixel electrode connecting unit 115.

13B, 14B, and 15B, the gate electrode 108, the gate wiring (not shown), the common wiring 106, the gate pad electrode 116, and the plurality of double layer common electrodes 110 and the pixels are illustrated. A gate insulating film 118 is formed by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the substrate 101 on which the electrode 113 is formed, and subsequently, pure amorphous silicon and impurity amorphous. By depositing silicon sequentially, the pure amorphous silicon layer 122 and the impurity amorphous silicon layer 123 are formed.

Next, a photoresist, which is a photosensitive organic material, is coated on the entire surface of the impurity amorphous silicon layer 123 to form a first photoresist layer (not shown), and the light blocking region and light are transmitted almost 100%. After placing a multi-tone exposure mask (not shown) composed of a transmissive region and a semi-transmissive region having a small amount of light transmitted relative to the transmissive region, exposure is performed.

Thereafter, the exposed first photoresist layer (not shown) is developed to form a first photoresist pattern 180a having a first thickness corresponding to the gate electrode 108 of the switching region TrA, and the gate At both ends of the pad portion GPA, the center portion of the gate pad electrode 116, and at one end of one of the plurality of double-layered pixel electrodes 113 formed adjacent to the common wiring 105. For example, the first photoresist layer (not shown) may be completely removed so that the impurity amorphous silicon layer 123 is exposed, and in other regions, a second photoresist pattern having a second thickness thinner than the first thickness ( 180b) is formed.

Subsequently, as shown in FIGS. 13C, 14C, and 15C, thereafter, dry etching is performed, and the impurity amorphous silicon layer 123 exposed to the outside of the first and second photoresist patterns 180a and 180b and the pure water thereunder. By removing the amorphous silicon layer 122 and the gate insulating layer 118, a pixel contact hole 119 is formed to correspond to one end of the pixel electrode 113 having one double layer structure in each pixel region P. At the same time, in the gate pad part GPA, first gate pad contact holes 122 are formed on both sides of the gate pad electrode 116 to expose the gate pad electrode 116.

13D, 14D and 15D, the ashing is performed to remove the second photoresist pattern (180b of FIGS. 13C, 14C and 15C) having the second thickness, thereby removing the second portion of the switching region TrA. The impurity amorphous silicon layer 123 is exposed to all regions except the region corresponding to the gate electrode 108. At this time, the thickness of the first photoresist pattern 180a is reduced, but still remains in the switching region TrA.

Next, as shown in FIGS. 13E, 14E, and 15E, dry etching is performed to expose the impurity amorphous silicon layer 123 of FIGS. 13D, 14D, and 15D and a portion thereof exposed to the outside of the first photoresist pattern 180a. The gate insulating layer 118 is exposed except for a portion corresponding to the gate electrode 108 of the switching region TrA by removing the pure amorphous silicon layer 122 of FIGS. 13D, 14D and 15D. At this time, in the switching region TrA, an impurity amorphous silicon pattern 124 having the same size as an island shape and an active layer 126a of pure amorphous silicon are formed under the first photoresist pattern 180a.

13F, 14F, and 15F, the first photoresist pattern (FIGS. 13E and 14E) is formed by stripping the substrate 101 on which the active layer 126a and the impurity amorphous silicon pattern 124 are formed. And the impurity amorphous silicon pattern 124 is exposed by removing 180a of 15e.

Subsequently, a third metal material, for example, molybdenum (Mo) or molybdenum titanium (MoTi) having a relatively strong corrosion resistance and excellent bonding strength with copper or a copper alloy is formed on the entire surface of the substrate 101 over the impurity amorphous silicon pattern 124. The third metal layer 133 and the fourth metal layer 134 that are sequentially stacked are formed by depositing a fourth metal material, for example, copper (Cu) or a copper alloy having low resistance characteristics.

Next, as shown in FIGS. 13G, 14G, and 15G, a photoresist is applied on the fourth metal layer 134 to form a second photoresist layer (not shown), and an exposure mask having a blocking region and a transmission region ( After the exposure is carried out using a light emitting device, the development is performed to develop a portion where the data line is to be formed, a portion where the source and drain electrodes to be separated from each other, a portion where the storage capacitor is to be formed, and a data pad electrode must be formed. The third photoresist pattern 184 is formed to correspond to the portion and the gate pad electrode 116.

Next, as shown in FIGS. 13H, 14H and 15H, wet etching of the fourth and third metal layers exposed to the outside of the third photoresist pattern 184 (134 and 133 of FIGS. 13G, 14G and 15G) is performed. By proceeding to remove it, in the switching region TrA, the source electrodes 140 (140a and 140b) and the drain electrode 143 (143a, which are in contact with both ends of the impurity amorphous silicon pattern 124, respectively, and are spaced apart from each other. 143b)). In this case, the drain electrode 143 of the double layer structure extends to the storage region StgA to form a storage capacitor StgC together with the common wiring 105 overlapping the plurality of drain electrodes 119 through the pixel contact hole 119. By contacting with any one of the pixel electrode 113 of the double layer structure it is electrically connected to the pixel electrode 113 of the plurality of double layer structure.

In addition, a data line 138 (138a, 138b) having a double layer structure is formed at the boundary of each pixel region P to cross the gate wiring (not shown) to define the pixel region P. Referring to FIG.

In the gate pad part GPA, a double layer gate auxiliary pad electrode 148 (148a and 148b) contacting the gate pad electrode 116 through the two first gate pad contact holes 121. To form.

In the data pad part DPA, the data pad electrodes 145 (145a and 145b) having the double layer structure connected to the data line 138 having the double layer structure are formed. In this case, the data line 138, the source and drain electrodes 140 and 143, the gate auxiliary pad electrode 148 and the data pad electrode 145 have a double layer structure at this stage.

Next, as shown in FIGS. 13I, 14I, and 15I, the impurity amorphous silicon pattern exposed between the source and drain electrodes 140 and 143 formed to be spaced apart from each other in the switching region TrA by performing dry etching (FIG. 13H). 124 is removed to expose the active layer 126a between the source and drain electrodes 140 and 143. At this time, the impurity amorphous silicon pattern 124 of FIG. 13H, which is not removed from the source and drain electrodes 140 and 143, forms an ohmic contact layer 126b, and is spaced apart from the active layer 126a and the upper portion thereof. The ohmic contact layer 126b forms the semiconductor layer 126. In this case, the gate electrode 108, the gate insulating layer 118, the semiconductor layer 126, and the source and drain electrodes 140 and 143 spaced apart from each other form a thin film transistor Tr.

Next, as shown in FIGS. 13J, 14J, and 15J, the third photoresist pattern (184 of FIGS. 13I, 14I, and 15I) remaining on the substrate 101 on which the ohmic contact layer 126b is formed is stripped. Proceed to remove.

Subsequently, an inorganic insulating material may be formed on the entire surface of the data line 138 and the source and drain electrodes 140 and 143, the gate auxiliary pad electrode 148, and the data pad electrode 145 having the double layer structure. For example, the protective layer 170 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx).

Thereafter, a photoresist is formed on the passivation layer 170 to form a photoresist layer (not shown), and then a mask process is performed on the protective layer 170 to pattern the fourth photoresist pattern corresponding to the boundary of the pixel region P. FIG. (186) is formed.

Next, the protective layer 170 exposed to the outside of the fourth photoresist pattern 186 and the gate insulating layer 118 thereunder are removed, so that the pixel electrode 113 having the double layer structure and the common layer in the pixel region P are removed. The electrode 110 is exposed.

Also, in the gate pad part GPA, a second gate pad contact hole 172 is formed corresponding to the center part of the gate pad electrode 116 to expose the gate auxiliary pad electrode 148 having a double layer structure corresponding to the center part. In the data pad unit DPA, the central portion of the double layer data pad electrode 145 or the entire data pad electrode 145 is exposed. In the figure, a portion of the central portion of the data pad electrode is exposed.

Next, as shown in FIGS. 13K, 14K and 15K, the plurality of pixel electrodes (113 in FIGS. 13J, 14J and 15J) and the common electrode (FIGS. 13J and 14J) having a double layer structure exposed by removing the protective layer 170 are removed. The upper layer (113b, 110b, 145b, and 148b of FIGS. 13j, 14j, and 15j) made of copper (Cu) or a copper alloy with respect to 110 of 15j, the center of the gate auxiliary pad electrode 148, and the data pad electrode 145 is formed. The wet etching is performed to remove the pixel electrode 114 and the common electrode 111 having the single layer structure, and the gate auxiliary pad electrode 148 and the data pad electrode 145 having the single layer structure.

In this case, in the gate pad part GPA, in the region corresponding to the second gate pad contact hole, the gate insulating layer 118 is between the gate auxiliary pad electrode 148 and the gate pad electrode 116 positioned below the gate pad part GPA. Since the substrate is not exposed to the etchant for removing the upper layer 148b of the gate auxiliary pad electrode 148, the partial etching of the upper layer 116b of the gate pad electrode 116 does not occur. In addition, since both sides of the gate pad electrode 116 are still covered by the protective layer 170, the upper layer 148b is not exposed to the etchant. Accordingly, the gate auxiliary pad electrodes 148 of the both sides still have a double layer structure, and the gate pad electrode 116 of the double layer structure contacting through the first gate pad contact hole 121 is also not exposed to the etchant. Therefore, this part also can be seen that the partial etching does not occur.

Next, as shown in FIGS. 13L, 14L, and 15L, the fourth photoresist pattern remaining on the data line 138 and the source and drain electrodes 140 and 143 (186 of FIGS. 13K, 14K, and 15K) is illustrated. ) Is removed by performing a wet process of the strip to complete the array substrate 101 for a transverse electric field type liquid crystal display device according to the present invention.

16 and 17 are photographs of the gate pad part of the transverse electric field type liquid crystal display device according to the related art and the present invention, respectively.

Referring to FIG. 16, it can be seen that in the conventional gate pad part, a portion corresponding to the plurality of gate pad contact holes is not very good as if the foreign material is interposed therebetween. This is due to partial etching of the upper layer of the gate pad electrode.

However, referring to FIG. 17, in the gate pad portion of the array substrate for a transverse electric field type liquid crystal display device according to the present invention, partial etching of the upper layer of the gate pad electrode made of copper or copper alloy occurs in the center and both sides thereof. It can be seen that the surface is very clean by not doing so.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

2A and 2B are cross-sectional views showing operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

FIG. 3 is a cross-sectional view of one pixel area including a thin film transistor of a conventional transverse field type liquid crystal display array substrate. FIG.

 4 is a cross-sectional view of one pixel region of an array substrate manufactured by a conventional four mask process.

Fig. 5 is a plan view of a gate pad portion of an array substrate manufactured by a four mask process in which the active layer and the source and drain electrodes are dualized.

6A-6G are cross-sectional views of some manufacturing steps for the portion of FIG. 5 taken along cut line VI-VI.

7 is a plan view of one pixel region of the array substrate according to the present invention;

8 is a plane view of a portion of a gate pad portion in which a gate pad electrode of an array substrate is formed according to the present invention;

9 is a plan view of a portion of a data pad portion on which a data pad electrode of an array substrate is formed according to the present invention;

FIG. 10 is a cross-sectional view of a portion taken along the line VII-VII of FIG. 7. FIG.

FIG. 11 is a cross-sectional view of a portion cut along the cutting line XXXI-XI of FIG. 8. FIG.

FIG. 12 is a cross-sectional view of a portion taken along the cutting line XXX-XII of FIG. 9. FIG.

13A to 13L are cross-sectional views of manufacturing steps of a portion cut along the line VII-VII of FIG. 7.

14A to 14L are cross-sectional views of manufacturing steps for a portion cut along the cutting line VIII-XI of FIG. 8.

15A to 15M are cross-sectional views of manufacturing steps of a portion taken along cut line XII-XII of FIG. 9;

16 and 17 are surface photographs of a gate pad part including one gate pad electrode of an array substrate for a transverse field type liquid crystal display device according to the related art and the present invention, respectively.

Description of the Related Art

101: array substrate 116: gate pad electrode

116a: lower layer of gate pad electrode 116b: upper layer of gate pad electrode

118 gate insulating film 121 first gate pad contact hole

148: gate auxiliary pad electrode 148a: lower layer of gate auxiliary pad electrode

148b: top layer of gate auxiliary pad electrode

   170: protective layer 172: second gate pad contact hole

GPA: Gate Pad

Claims (7)

A gate wiring and a common wiring of a double layer structure in which a pixel region including a switching region extends in one direction and is spaced apart from each other on a defined substrate; A double layer gate pad electrode connected to an end of the gate line on the substrate; A plurality of common electrodes having a plurality of single layer structures formed in the pixel area on the substrate by branching from the common wiring; A plurality of single-layered pixel electrodes formed alternately in parallel with common wirings of the plurality of single-layered structures in the pixel area on the substrate, and connected at both ends thereof; A double layer gate electrode formed in the switching region on the substrate and connected to the gate wiring;  A first gate pad contact hole formed over the boundary of each pixel region, the switching region, and the gate pad electrode, and exposing the gate pad electrode on both sides of the gate pad electrode; A gate insulating film having a pixel contact hole exposing an end of one of the plurality of pixel electrodes; A double layer data line formed on the gate insulating layer to cross the gate line to define the pixel area; A data pad electrode formed on the gate insulating layer so as to be connected to one end of the data line, a central portion having a single layer structure, and both sides having a double layer structure; A gate auxiliary pad electrode contacting the gate pad electrode of the double layer structure over the gate insulating layer through the first gate pad contact hole, a central portion thereof having a single layer structure, and both ends thereof having a double layer structure; A semiconductor layer formed in the switching region over the gate insulating film; A double layer source electrode connected to the data line over the semiconductor layer, and a double layer drain electrode spaced apart from the source electrode on the semiconductor layer and contacting one of the plurality of pixel electrodes through the pixel contact hole. and; A central portion having a single layer structure covering the switching region and the data line and formed at a boundary between each pixel region and at the same time covering a double layer structure corresponding to the gate auxiliary pad electrode and the data pad electrode. Correspondingly, a protective layer formed with a second gate pad contact hole and a data pad contact hole exposing them, respectively. Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 1, The electrode and the wiring of the double layer structure, the lower layer is made of molybdenum (Mo) or molybdenum (MoTi), the upper layer is an array substrate for a transverse electric field type liquid crystal display device, characterized in that made of copper (Cu) or copper alloy . The method of claim 2, The plurality of pixel electrodes and the common electrode constituting the single layer structure, and the portion forming the single layer of the gate auxiliary pad electrode and the data pad electrode are made of molybdenum (Mo) or molybdenum (MoTi). Array substrate for devices. The method of claim 1, And the drain electrode is formed to overlap the common wiring so that the overlapping portion forms a storage capacitor. A pixel layer including a switching region has a double layer structure, a gate wiring extending in one direction and a gate pad electrode at an end thereof, and a gate electrode connected to the gate wiring in the switching region, Forming a common wiring extending parallel to the gate wiring, a plurality of common electrodes having a plurality of double layer structures branching from the common wiring in the pixel region, and a plurality of double layer structure pixel electrodes alternately with the common electrode;  Sequentially forming a gate insulating film and a pure and impurity amorphous silicon layer over the gate wiring; Patterning the impurity and the pure amorphous silicon layer and a gate insulating layer thereunder to expose the gate pad electrode to both sides of the pixel contact hole exposing one end of the pixel electrode and the center portion of the gate pad electrode, respectively; Forming a gate pad contact hole, and forming an active layer and an impurity amorphous silicon pattern over the gate insulating layer in the switching region; A double layer structure over the gate insulating layer, a data line defining the pixel region is formed to cross the gate line, a data pad electrode is formed at an end thereof, and the data is formed on the impurity amorphous silicon pattern of the switching region. Forming a source electrode connected to a wire and a drain electrode spaced apart from the source electrode and in contact with the pixel electrode through the pixel contact hole; Forming an ohmic contact layer under the source and drain electrodes by removing the impurity amorphous silicon pattern exposed between the source and drain electrodes; Forming a protective layer over the data line and patterning the protective layer to expose the plurality of pixel electrodes and the common electrode, and exposing a central portion of the gate auxiliary pad electrode and a central portion of the data pad electrode; Forming a single layer structure by performing wet etching to remove a plurality of pixel electrodes having the double layer structure, the common electrode, the gate auxiliary pad electrode, and the data pad electrode exposed to the outside of the protective layer by wet etching. And a gate insulating layer disposed below the gate auxiliary pad electrode exposed to the wet etching to prevent the central portion of the gate pad electrode from being exposed to the etchant for the wet etching. A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device. 6. The method of claim 5, A pixel contact hole exposing one end of the pixel electrode and a first gate pad contact hole exposing the gate pad electrode on both sides of the center portion of the gate pad electrode, the gate insulating layer being formed in the switching region The step of forming the active layer and the impurity amorphous silicon pattern, A first photoresist pattern having a first thickness is formed on the impurity amorphous silicon layer to correspond to the gate electrode, and the impurity amorphous silicon layer is formed to correspond to a portion where the pixel contact hole is to be formed and both sides of the gate pad electrode. Exposing and forming a second photoresist pattern of a second thickness thinner than said first thickness corresponding to the other regions; The pixel contact hole and the gate pad electrode exposing one end of the pixel electrode by etching the impurity amorphous silicon layer exposed to the outside of the first and second photoresist patterns, the pure amorphous silicon layer below the gate insulating film, and the gate insulating film Forming a first gate pad contact hole to expose; Removing the second photoresist pattern; Forming the island-like active layer and the impurity amorphous silicon pattern in the switching region by removing the impurity amorphous silicon layer exposed by removing the second photoresist pattern and the pure amorphous silicon layer thereunder; Removing the first photoresist pattern Method of manufacturing an array substrate for a transverse electric field type liquid crystal display device comprising a. 6. The method of claim 5, The electrode and the wiring of the double layer structure, the lower layer is made of molybdenum (Mo) or molybdenum (MoTi), the upper layer is an array substrate for a transverse electric field type liquid crystal display device, characterized in that made of copper (Cu) or copper alloy Method of preparation.

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