KR101274212B1 - Power Factor Correction Circuit - Google Patents

Abstract

The present invention relates to a power factor correction circuit.

To this end, the present invention, the first inductor electrically connected to the first end of the input terminal, the second inductor magnetically connected to the first inductor to form a transformer and the first voltage and power factor correction circuit generated in the second inductor And a power factor correction integrated circuit configured to receive a feedback voltage corresponding to an output voltage output through an output terminal of the power supply and increase a current flowing through the first inductor at a first time point when the current flowing through the first inductor becomes zero. The circuit provides a power factor correction circuit including a first switch having a first end connected to a second end of a first inductor, and a switching controller for controlling the first switch to be turned on at a first time point.

According to the present invention, a power factor correction circuit capable of high integration and low power driving can be implemented by reducing the number of input / output terminals of the PFC IC and including a switch Qsw inside the PFC IC.

Power Factor Correction Circuit, PFC IC

Description

Power Factor Correction Circuit

1 is a diagram schematically showing a conventional power factor correction circuit using SG6561A as a PFC IC.

2 is a diagram illustrating a power factor correction circuit 100 according to an exemplary embodiment of the present invention.

3 is a diagram schematically illustrating an internal configuration of the PFC IC 110 according to the embodiment of the present invention.

4 is a diagram schematically illustrating a PFC IC 120 according to another embodiment of the present invention.

5 is a diagram illustrating a lamp generator 1113 included in the PFC IC 120 according to another embodiment of the present invention shown in FIG.

The present invention relates to a power factor correction circuit.

Recently, power factor correction circuits have been used in most switching mode power supplies (SMPS) due to current harmonic regulations such as EN61000-3-2. SMPS is a device that converts an input supply voltage into one or more DC output voltages, and is mainly used in power supplies such as mobile phones and laptop computers. In such SMPS, a power factor correction circuit is used that compensates for the power factor by causing the input current to follow the input voltage. That is, a power factor correction (PFC) circuit is a circuit that outputs an alternating current (AC) voltage as a constant direct current (DC) voltage while simultaneously allowing an input current to follow an input voltage applied to the outside.

The power factor correction circuit includes an inductor, and the operating mode of the power factor correction circuit includes a continuous conduction mode, a discontinuous conduction mode, and a critical conduction mode depending on the state of the current flowing through the inductor. ) Are divided into three. The continuous conduction mode is an operation mode such that there is no time point when the current flowing through the inductor becomes zero, and the discontinuous conduction mode is an operation mode such that there is a time point when the current flowing through the inductor becomes zero. On the other hand, the critical conduction mode is a mode that operates at the boundary between the continuous conduction mode and the discontinuous conduction mode, and is an operation mode that increases the current flowing through the inductor when the current flowing through the inductor becomes zero.

As a power factor correction circuit operating in a conventional threshold current mode, there is a Korean Patent Publication 2006-0026701 'Power Factor Correction circuit'. Korean Patent Laid-Open Publication No. 2006-0026701 has a power factor of FAN7529 to overcome the zero-crossing distortion in which the input current corresponding to the AC voltage input to the conventional power factor correction circuit passes through zero ampere. It is a power factor correction circuit used as a compensation integrated circuit (hereinafter, PFC IC).

FIG. 1 schematically illustrates a conventional power factor correction circuit using the FAN7529 as a PFC IC. As shown in FIG. 1, the conventional power factor correction circuit 10 includes a PFC IC including eight input / output terminals.

Recently, research for miniaturization of SMPS has been actively conducted. However, the distance between the input and output terminals of the PFC IC cannot be reduced to a certain level or less, and thus, the area of a printed circuit board (PCB) on which the power factor correction circuit 10 is mounted is implemented to a predetermined level or less. There was a limit. Accordingly, there is an urgent need for a method for implementing a smaller power factor correction circuit.

In order to solve this problem, the present invention provides a power factor correction circuit capable of high integration and low power driving.

A power factor correction circuit according to a feature of the present invention for achieving the above object is a power factor correction circuit including a first inductor having a first end electrically connected to an input terminal, the transformer being magnetically connected to the first inductor A second inductor forming a second voltage and a first voltage generated in the second inductor and a feedback voltage corresponding to an output voltage output through an output terminal of the power factor correction circuit, the current flowing through the first inductor becomes zero; A power factor correction integrated circuit configured to increase a current flowing through the first inductor at a first point in time, wherein the power factor correction integrated circuit includes a first switch having a first end connected to a second end of the first inductor; And a switching controller for controlling the switch to be turned on at the first time point.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

Now, a power factor correction circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a power factor correction circuit 100 according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the power factor correction circuit 100 according to an embodiment of the present invention includes a bridge diode BD connected to an AC voltage input terminal, an inductor L1 connected to one end of the bridge diode BD, and an anode. Is a diode D1 connected to the other end of the inductor L1, a capacitor C1 having one end connected to the cathode of the diode D1 and the other end connected to the ground terminal, and one end connected to the cathode of the diode D1. (R1), a resistor R2 having one end connected to the other end of the resistor R1 and the other end connected to the ground terminal, and an inductor having one end connected to the ground terminal and magnetically connected to the inductor L1 to form a transformer ( L2), a resistor R3 having one end connected to the other end of the inductor L2, a diode D2 having the anode connected to the other end of the inductor L2, one end connected to the cathode of the diode D2, and the other end being grounded. Capacitor (C2) connected to one end, the comparison voltage (Comp) input of the PFC IC (110) It is connected to a terminal (I / O # 4) and the other end comprises a capacitor (C3) and the PFC IC (110) connected to the ground terminal.

The PFC IC 110 includes a switching controller 111 and a switch Qsw, and includes a drain terminal (I / O # 1), a ground (GND) terminal (I / O # 2), and a power supply voltage (Vcc). ) Input terminal (I / O # 3), comparison voltage (Comp) input terminal (I / O # 4), V _ZCD voltage input terminal (I / O # 5) and feedback voltage (Vfb) input terminal (I / O 6 input / output terminals of # 6). The drain terminal I / O # 1 is connected to the contact of the inductor L1 and the diode D1, and the ground (GND) terminal I / O # 2 is connected to the ground terminal. The power supply voltage (Vcc) input terminal (I / O # 3) is connected to the contact of the diode (D2) and the capacitor (C2), the comparison voltage (Comp) input terminal (I / O # 4) of the capacitor (C3) It is connected to one end. The V _ZCD voltage input terminal I / O # 5 is connected to the other end of the resistor R3, and the feedback voltage Vfb input terminal I / O # 6 is connected to the contact of the resistor R1 and the resistor R2. Connected.

On the other hand, unlike shown in Figure 2, the power supply voltage (Vcc) input terminal (I / O # 3) of the PFC IC 110 is connected to the other power supply not shown in Figure 2 of the PFC IC 110 Of course, it can be implemented to receive the power supply voltage (Vcc) for driving.

The power factor correction circuit 100 according to the exemplary embodiment of the present invention illustrated in FIG. 2 includes the power factor correction circuit 100 by including a switch Qsw inside the PFC IC 110, unlike the conventional power factor correction circuit 10 illustrated in FIG. 1. ) Can improve the degree of integration.

In the conventional power factor correction circuit 10 shown in FIG. 1, in order to include the switch Qsw in the PFC IC, the PFC is connected to the drain of the switch Qsw so as to be connected to the contact of the inductor L1 and the diode D1. The number of input and output terminals of the IC must be increased. That is, a drain terminal I / O # 1 is required among the six input / output terminals of the PFC IC 110 shown in FIG. Due to such an increase in the number of input and output terminals, it is difficult to secure the gap between the input and output terminals of the PFC IC to a certain level or more, and thus, the conventional power factor correction circuit (10 in FIG. 1) includes a switch Qsw inside the PFC IC to increase integration. It was hard to improve.

The power factor correction circuit 100 according to the embodiment of the present invention includes a PFC IC 110 having an internal structure different from that of the prior art, and thus, the PFC IC 110 includes a switch Qsw in the PFC IC 110. The number of input / output terminals of the IC 110 is further reduced to improve the degree of integration. This will be described later with reference to FIG. 3, which shows a PFC IC 110 according to an embodiment of the present invention.

3 is a diagram schematically illustrating an internal configuration of the PFC IC 110 according to the embodiment of the present invention. For reference, since the PFC IC 110 according to the embodiment of the present invention shown in FIG. 3 has many parts similar to those described in the product specifications of the FAN7529, which are known to those skilled in the art, only the parts different from the FAN7529 will be described below.

As shown in FIG. 3, the PFC IC 110 according to the embodiment of the present invention includes a switching controller 111 and a switch Qsw.

The switch Qsw is driven in accordance with a control signal input from the gate driver 1119 to the control electrode. The drain of the switch Qsw is connected to the drain terminal I / O # 1, and the source is connected to the ground (GND) terminal I / O # 2.

The switch Qsw is formed as a kind of sense FET (Field Effect Transistor) having a second source terminal which is proportional to the amount of current flowing to the source terminal of the switch Qsw but flows a very small current compared to the current flowing to the source terminal. The second source terminal of the switch Qsw is connected to the ground terminal through the resistor R4, and the overcurrent protection unit in which the amount of source terminal current of the switch Qsw sensed through the resistor R4 is included in the switching controller 111. It becomes an input signal of 1112.

The switching controller 111 may include a zero current detector 1111, an over current protection (OCP) 1112, a lamp generator 1113, a comparator 1114, a voltage converter 1115, a comparator 1116, and a logic sum. A gate 1117, a flip flop 1118, and a gate driver 1119 are included.

When the current flowing through the inductor L1 becomes zero, the zero current detector 1111 falls to the set terminal S of the flip-flop 1118 when the voltage V _ZCD drops to reach the preset reference voltage. Transmit signal to turn on switch Qsw.

The overcurrent protection unit 1112 turns off the switch Qsw when the amount of current at the source terminal of the switch Qsw detected through the resistor R4 exceeds a set level.

The ramp generator 1113 is not connected to the input / output terminal, and generates a ramp waveform voltage Vramp having a constant ramp slope using an internal current source (not shown) to generate a non-inverting input terminal of the comparator 1116 ( Output as +)

The comparator 1114 compares the feedback voltage Vfb and the reference voltage Vref1 input to the inverting input terminal (-) and the non-inverting input terminal (+), respectively, and compares the difference between the feedback voltage Vfb and the reference voltage Vref1. The corresponding output voltage Veao is output to the voltage converter 1115.

The voltage converter 1115 supplies the Veao 'voltage generated by adjusting the voltage level of the output voltage Veao input from the comparator 1114 to the inverting input terminal (-) of the comparator 1116.

The comparator 1116 compares the output signal Veao 'of the voltage converter 1115 inputted to the inverting input terminal (-) and the non-inverting input terminal (+) with the output signal of the lamp generator 1113, and the ramp generator ( When the output signal of 1113 coincides with the output signal Veao 'of the voltage converter 1115, the high level signal is output to the OR gate 1117 to turn off the switch Qsw.

The OR gate 1117 performs an OR operation on the output signal of the overcurrent protection unit 1112 and the output signal of the comparator 1116 and transfers the OR signal to the reset terminal R of the flip-flop 1118.

The flip-flop 1118 performs a logical operation on the output signal of the zero current detector 1111 and the output signal of the OR gate 1117, which are respectively input through the set stage S and the reset stage R, and non-inverts the result. The signal is transferred to the gate driver 1119 through the output terminal Q.

The gate driver 1119 generates a gate control signal for controlling the on / off of the switch Qsw in response to the logic signal input from the flip-flop 1118.

On the other hand, unlike shown in FIG. 3, the switching controller 111 may be implemented not to include the voltage converter 1115. In this case, the comparator 1116 compares the output voltage Veao of the comparator 1114 input through the inverting input terminal (−) and the output signal of the ramp generator 1113 input through the non-inverting input terminal (+), The high level signal is output when the output signal of the ramp generator 1113 coincides with the output voltage Veao of the comparator 1114.

Specific driving of the switching control unit 111 shown in FIG. 3 will be appreciated by those skilled in the art, and thus a detailed description thereof will be omitted.

Unlike the conventional PFC IC illustrated in FIG. 1, the PFC IC 110 according to the exemplary embodiment of the present invention may remove an input / output terminal (MOT terminal) for changing a ramp slope of the lamp generator 1113. A drain terminal I / O # 1 may be formed in the PFC IC 110, and thus, the switch Qsw may be included in the PFC IC 110. In addition, since the switch Qsw is included in the PFC IC 110, the input / output terminal (CS terminal) for the overcurrent protection unit 1112 input signal can also be removed. As a result, the package size of the power factor correction circuit 100 may be further reduced while maintaining the interval between the input and output terminals of the PFC IC by reducing the number of input / output terminals of the PFC IC.

On the other hand, without increasing the number of input and output terminals of the PFC IC 110 according to the embodiment of the present invention shown in Figure 3 ramp ramp waveform Vramp having a different ramp inclination according to the input voltage (Vin) ), Which will be described with reference to FIGS. 4 and 5.

4 is a diagram schematically illustrating a PFC IC 120 according to another embodiment of the present invention. For reference, FIG. 4 shows only portions different from the PFC IC 110 according to the embodiment of the present invention shown in FIG. 3. In addition, in the PFC IC 120 according to another embodiment of the present invention shown in FIG. 4, the same reference numerals are used for the same components as the PFC IC 110 according to the embodiment of the present invention shown in FIG. It was.

As shown in FIG. 4, the PFC IC 120 according to another embodiment of the present invention is implemented such that the lamp generator 1113 receives a current from the current source I _THD included in the zero current detector 1111 and is driven. The switching control unit 121 is included.

The amount of output current of the current source I _THD varies in proportion to the amount of current I _ZCD flowing through the V _ZCD voltage input terminal I / O # 5 to the resistor (R3 in FIG. 2), and thus the lamp generator 1113 The ramp voltage waveform Vramp output from) has a different ramp slope depending on the input voltage Vin.

5 is a diagram illustrating a lamp generator 1113 included in the PFC IC 120 according to another embodiment of the present invention shown in FIG. For reference, the lamp generator 1113 according to the embodiment of the present invention shown in FIG. 5 generates a ramp voltage waveform Vramp in which the lamp generator 1113 has a different ramp slope according to the output current amount of the current source I _THD . As an example illustrated to illustrate the present invention, a lamp generator implemented in a different form may be used.

As shown in FIG. 5, the lamp generator 1113 according to an embodiment of the present invention includes a current source I _RAMP , a current source I _RAMP , and a voltage source supplying 1V connected to a power supply Vcc1 supplying a Vcc1 voltage. Capacitor C4 connected therebetween, including a transistor Qramp and an inverter 1113-1 connected to a current source I _RAMP and a contact of capacitor C4 and connected to a voltage source to which the emitter supplies 1V. do. Here, the contact of the current source I _RAMP and the capacitor C4 becomes the output terminal of the lamp generator 1113, which is connected to the non-inverting input terminal (+) of the comparator 1116. Meanwhile, the amount of output current is proportional to the amount of current I _ZCD flowing through the V _ZCD voltage input terminal I / O # 5 to the resistor (R3 in FIG. 2) at the contact point of the current source I _RAMP and the capacitor C4. A current source I _THD having a varying size is connected, and thus, a current supplied from the current source I _THD included in the zero current detector 1111 and a current supplied from the current source I _RAMP charge the capacitor C4. Let's do it.

The transistor Qramp is driven on / off according to a gate control signal which is an output signal of the gate driver 1119 which is inverted into the control electrode through the inverter 1113-1. That is, when the switch Qsw is turned off, the transistor Qramp is turned on, so that a current supplied from the current source I _THD and the current source I _RAMP flows to the transistor Qramp. When the transistor Qramp is turned on, current supplied from the current source I _THD and the current source I _RAMP flows to the voltage source supplying 1V through the transistor Qramp, and the voltage charged in the capacitor C4 Discharged. In contrast, when the switch Qsw is turned on, the transistor Qramp is turned off. At this time, the current flowing from the current source I _THD to the capacitor C4 is proportional to the magnitude of the current I _ZCD flowing through the V _ZCD voltage input terminal I / O # 5 to the resistor R3.

Since the V _ZCD voltage is inversely proportional to the input voltage Vin, the amount of current I _ZCD flowing through the V _ZCD voltage input terminal I / O # 5 to the resistor R3 is transferred to the power factor correction circuit (100 in FIG. 2). The input current corresponding to the input AC voltage AC IN is the smallest at the zero crossing point and passes the largest at the point at which the input current becomes the maximum. The current supplied from the current source I _THD to the capacitor C4 is proportional to the amount of current I _ZCD flowing through the V _ZCD voltage input terminal I / O # 5 to the resistor R3, which causes the capacitor ( The slope of the voltage charged in C4) changes so that the slope of the ramp waveform voltage Vramp output from the lamp generator 1113 changes.

On the other hand, since the output voltage Vout generally has a constant voltage, the output voltage Veao of the comparator 1114 becomes a constant voltage, thereby keeping the output voltage Veao ′ of the voltage converter 1115 constant. do. The comparator 1116 compares the ramp waveform voltage Vramp with the output voltage Veao 'of the voltage converter 1115 and at the point when the ramp waveform voltage is equal to the output voltage Veao' of the voltage converter 1115. Output a high level signal. As a result, the switch Qsw is turned off, and the ON state holding period of the switch Qsw is changed according to the magnitude of the input voltage Vin. That is, when the input voltage Vin is low, the ON state holding period of the switch Qsw is long, and when the input voltage Vin is high, the ON state holding period of the switch Qsw becomes short.

The lamp generator 1113 included in the PFC IC 120 according to another embodiment of the present invention shown in FIG. 5 may change the ON state holding period of the switch Qsw according to the input voltage Vin to compensate for the power factor. Zero-crossing distortion that is distorted when the input current corresponding to the alternating voltage AC IN input to the circuit 100 of FIG. 2 passes through the zero ampere may be removed.

The power factor correction circuit 100 according to the embodiment of the present invention includes a switch Qsw in the PFC IC 110 so that a printed circuit board that may occur when a control signal is transmitted from the conventional PFC IC to the switch Qsw ( Noise input through the leads on a printed circuit board (PCB) can be eliminated.

In addition, the area of a printed circuit board (PCB) on which the power factor correction circuit 100 is mounted may be reduced, and set design may be facilitated.

In addition, even though the number of input / output terminals of the PFC IC 110 is reduced, all of the functions of the conventional power factor correction circuit can be implemented, thereby implementing a power factor correction circuit capable of high integration and low power driving.

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

As described above, according to the present invention, a power factor correction circuit having a high degree of integration can be implemented by reducing the number of input / output terminals of a PFC IC.

In addition, by including the switch Qsw inside the PFC IC, noise input through a conductive line on a printed circuit board (PCB), which may occur when a control signal is transmitted from the conventional PFC IC to the switch Qsw, may be removed. .

In addition, the area of a printed circuit board (PCB) on which the power factor correction circuit is mounted can be reduced, and set design can be facilitated.

Claims (16)

A power factor correction circuit comprising a first inductor having a first end electrically connected to an input terminal, A second inductor magnetically connected to the first inductor to form a transformer; The first inductor at a first time point at which a current flowing through the first inductor becomes zero by receiving a feedback voltage corresponding to a first voltage generated in the second inductor and an output voltage output through an output terminal of the power factor correction circuit; A power factor correction integrated circuit for increasing a current flowing in the The power factor correction integrated circuit, A first switch having a first end connected to a second end of the first inductor; And a switching controller to control the first switch to be turned on at the first time point. Wherein the switching control unit comprises: A zero current detector configured to output a first signal that is a first level signal when a voltage of a second input / output terminal connected to one end of the second inductor through a first resistor is not greater than a first reference voltage; A first comparator comparing a feedback voltage input through a third input / output terminal of the power factor correction circuit with a second reference voltage and outputting a second voltage corresponding to a difference between the feedback voltage and the second reference voltage; A ramp generator generating a ramp waveform voltage using a current corresponding to a current flowing through the first resistor; And A second comparator for comparing the ramp waveform voltage with the second voltage and outputting a third signal having a third level at a second time point when the ramp waveform voltage coincides with the second voltage; A power factor correction circuit for turning off the first switch according to the output of the second comparator. The method of claim 1, Wherein the switching control unit comprises: And an overcurrent protection unit configured to detect an amount of current flowing through the second end of the first switch and to output a second signal having a second level when the amount of current flowing through the second end of the first switch exceeds a set current amount. Power factor correction circuit. 3. The method of claim 2, Wherein the switching control unit comprises: An OR gate for outputting a fourth signal generated by performing an OR operation on the second and third signals; And a first logic calculator configured to logically operate the first and fourth signals input to the first and second stages, respectively, and output a fifth signal having a fourth level at the first time point. The method of claim 3, Wherein the switching control unit comprises: And a gate driver generating a gate control signal having a fifth level and turning on the first switch when the fifth signal has the fourth level. The method of claim 3, Wherein the switching control unit comprises: And a voltage converter configured to change a voltage level of the second voltage to generate a third voltage. And the second comparator compares the ramp waveform voltage with the third voltage and outputs the third signal having a sixth level at a third time point when the ramp waveform voltage coincides with the third voltage. 5. The method of claim 4, The lamp generator, A first current source having one end connected to a first power supply for supplying a fourth voltage and supplying a current corresponding to a current flowing through the first resistor; A second capacitor having one end connected to the other end of the first current source and the other end connected to a second power supply for supplying a fifth voltage; A second switch having a first end connected to a first node which is a contact point of the first current source and the second capacitor, and having a second end connected to the second power source; And an inverter for inverting the gate control signal to supply the control electrode of the second switch, and outputting the ramp waveform voltage to the second comparator through the first node. The method of claim 6, The zero current detector includes a second current source, one end of which is connected to a third power supply for supplying a sixth voltage and supplies a current corresponding to the amount of current flowing through the second input / output terminal to the first resistor. The lamp generator, A power factor correction circuit coupled to the other end of the second current source and generating the ramp waveform voltage having a ramp slope proportional to the amount of current supplied from the second current source to the second capacitor .  The method of claim 6, And the ramp waveform voltage always has a constant ramp slope. The method of claim 7, wherein The amount of current supplied from the second current source to the second capacitor is proportional to the amount of current flowing through the second input and output terminals to the first resistor. 10. The method of claim 9, The ON state holding period of the first switch is inversely proportional to the magnitude of the input voltage input through the input terminal. The method according to any one of claims 2 to 10, The power factor correction integrated circuit, A fourth input / output terminal connected to a first capacitor charged with a seventh voltage corresponding to the second voltage; A fifth input / output terminal connected to the ground terminal; And A sixth input / output terminal to which a power supply voltage for driving the power factor correction integrated circuit is input; A power factor correction circuit further comprising. 12. The method of claim 11, A power factor correction circuit having a second end of the first switch connected to the fifth input / output terminal. The method of claim 12, The first switch, And a third stage connected to the fifth input / output terminal through a second resistor, wherein the amount of current flowing through the second resistor is an amount of current flowing through the second terminal of the first switch to the fifth input / output terminal. Power factor correction circuit proportional to. 12. The method of claim 11, The sixth input and output terminal, A power factor correction circuit having an anode connected to a contact point of one end of a second capacitor including a first diode connected to a contact of the second inductor and the first resistor and the other end connected to the ground terminal. 12. The method of claim 11, The power factor correction circuit further comprises a power supply, The sixth input / output terminal is connected to an output terminal of the power supply device and receives a voltage input from the power supply device. 14. The method of claim 13, The overcurrent prevention unit, And a power factor correction circuit for sensing the amount of current flowing through the second resistor and determining whether the amount of current flowing through the second end of the first switch exceeds the set current amount.

Images