KR101244660B1 - Liquid Crystal Display And Driving Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof in which the duty ratio of the gate shift clock can be reduced to improve the display quality as the scanning sequence becomes late. .

A liquid crystal display according to the present invention includes a plurality of data lines to which video data is applied; A plurality of gate lines intersecting the plurality of data lines and supplied with a scan pulse; A plurality of thin film transistors formed at intersections of the data lines and the gate lines and turned on in response to the scan pulse; A plurality of liquid crystal cells having pixel electrodes supplied with data voltages from the thin film transistors; A gate driving circuit configured to sequentially generate the scan pulses and supply them to the gate lines in response to a start pulse and a gate shift clock; A data driving circuit converting digital video data into an analog data voltage and supplying the analog gamma voltage as the video data to the data lines; And a control circuit for reducing the duty ratio of the gate shift clock toward the gate line having a late scan order.

Description

Liquid Crystal Display And Driving Method Thereof

1 is a view schematically showing a driving device of a conventional liquid crystal display device.

FIG. 2 illustrates a portion of a conventional liquid crystal display device driven according to a storage on gate method. FIG.

3 is a diagram showing parasitic capacitance present in the gate line and the data line of a conventional liquid crystal display.

4A is an ideal waveform diagram for gray to gray response speed.

4b is an actual waveform diagram for gray to gray response speed.

5 is a view showing a driving device of a liquid crystal display according to an embodiment of the present invention.

FIG. 6 is a diagram showing a detailed configuration of the gate driving circuit shown in FIG. 5; FIG.

7 and 8 are waveform diagrams showing a gate shift clock (GSC) in which the duty ratio decreases toward the gate line with a late scan order.

FIG. 9 is a diagram illustrating a circuit configuration of first and second stages of a shift register and first and second level shifters in the gate driving circuit shown in FIG. 6; FIG.

FIG. 10 is a view showing a drive signal waveform of the circuit shown in FIG. 9; FIG.

11 is a waveform diagram of first and second clock signals and corresponding first and second gate voltages;

Description of the Related Art

102: liquid crystal panel 104: data driving circuit

106: gate driving circuit 108: timing controller

161 shift shift Cgd gate-drain parasitic capacitor

Clc: liquid crystal cell Cst: storage capacitor Ec: common electrode Ep: pixel electrode

GL [1]: to GL [n]: Gate line DL [1]: to DL [m]: Data line

S [1] to S [n]: Stage LS [1] to LS [n]: Level Shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof in which the duty ratio of the gate shift clock can be reduced to improve the display quality as the scanning sequence becomes late. .

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to data signals. The liquid crystal display device is implemented in an active matrix type in which switching elements are formed in each cell, and is applied to display devices such as computer monitors, office equipment, and cellular phones. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

1 schematically shows a driving device of a conventional liquid crystal display.

Referring to FIG. 1, in the conventional LCD, m × n liquid crystal cells Clc are arranged in a matrix type, and m data lines D1 to Dm and n gate lines G1 to Gn are arranged in a matrix type. A liquid crystal panel 2 that intersects and a TFT is formed at an intersection thereof, a data driving circuit 4 for supplying a data signal to the data lines D1 to Dm of the liquid crystal panel 2, and gate lines G1. And a gate driver circuit 6 for supplying scan signals to Gn) and a timing controller 8 for controlling the data driver circuit 4 and the gate driver circuit 6.

The liquid crystal panel 2 includes a plurality of liquid crystal cells Clc disposed in a matrix at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn. Each TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data lines D1 to Dm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line G. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst may be formed between the pixel electrode of the liquid crystal cell Clc and the previous gate line or may be formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain the voltage of the liquid crystal cell Clc constant .

The gate driving circuit 6 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal CS from the timing controller 8 so that the data signal is supplied horizontally. Select a line.

The data driving circuit 4 converts the digital video data R, G, and B into analog gamma voltages (data signals) corresponding to the gray scale values in response to the control signal CS from the timing controller 8. The analog gamma voltage is supplied to the data lines D1 to Dm.

The timing controller 10 generates a control signal CS for controlling the gate driving circuit 6 and the data driving circuit 4 using the synchronization signals and the clock signal supplied from the outside. Here, the control signal CS for controlling the gate driving circuit 6 includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like. This includes. The control signal CS for controlling the data driving circuit 4 includes a source start pulse (GSP), a source shift clock (SSC), and a source output signal (SOC). And a polarity signal (POL). The timing controller 10 rearranges the data Data supplied from the outside and supplies the data to the data driving circuit 4.

The conventional liquid crystal display maintains a constant data voltage charged in the liquid crystal cell Clc for one frame through the storage capacitor Cst formed between the pixel electrode of the liquid crystal cell Clc and the front gate line. The storage capacitor Cst formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line maintains the data voltage charged in the liquid crystal cell Clc constant for one frame. The former is called a storage on gate method, and the latter is called a storage on common method. Among them, the storage on gate method does not require a separate common electrode line, so it is generally used for cost reduction.

2 illustrates a portion of a conventional liquid crystal display device driven according to a storage on gate method.

As shown in FIG. 2, a conventional liquid crystal display device driven by a storage on gate method includes a pixel disposed on an nth horizontal line selected by a scan pulse of an n (n is a positive integer) th gate line Gn. A storage capacitor is connected between the electrode and the n−1 th gate line Gn−1. However, in the conventional liquid crystal display which is driven according to the storage on gate method, when complete discharge is not performed in the storage capacitor (for example, Cst1), the remaining charges are accumulated in the storage capacitor (for example, Cst2) of the rear stage. This leads to the problem of more charge being charged to the storage capacitor as the scan sequence goes to a later gate line.

Furthermore, as shown in FIG. 3, parasitic capacitances Cgd exist between the gate line G and the data line D, and these parasitic capacitances remain in the data line toward the gate line with a late scanning order. Since the charge tends to increase due to accumulation of charges, when the same gray scale is implemented, the amount of charge charged in the liquid crystal cell increases as the liquid crystal cell Clc moves away from the data driving circuit 4.

4A and 4B are waveform diagrams for gray to gray response speeds, and ideally, the waveforms should be similar to those of FIG. 4A. However, gray to gray response speed waveforms of the conventional LCD are actually shown in FIG. 4B due to the problems described above. As shown, the ripple component is included every frame.

As a result, in the conventional LCD, the amount of charge charged in the liquid crystal cell is increased in proportion to the distance from the data driver circuit 4 when the same gray scale is implemented, resulting in flicker and the like, thereby degrading the image quality.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can improve display quality by decreasing the duty ratio of the gate shift clock toward the gate line having a late scan order.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention includes a plurality of data lines to which video data is applied; A plurality of gate lines intersecting the plurality of data lines and supplied with a scan pulse; A plurality of thin film transistors formed at intersections of the data lines and the gate lines and turned on in response to the scan pulse; A plurality of liquid crystal cells having pixel electrodes supplied with data voltages from the thin film transistors; A gate driving circuit configured to sequentially generate the scan pulses and supply them to the gate lines in response to a start pulse and a gate shift clock; A data driving circuit converting digital video data into an analog data voltage and supplying the analog gamma voltage as the video data to the data lines; And a control circuit for reducing the duty ratio of the gate shift clock toward the gate line having a late scan order.

The control circuit is a timing controller for supplying the digital video data to the data driving circuit, and controlling the operation timing of each of the gate driving circuit and the data driving circuit.

The timing controller counts an input clock to determine the position of the gate shift clock, and controls the delay amount of the gate shift clock to decrease as the scan sequence goes to a gate line having a late scan order.

According to an exemplary embodiment of the present invention, a liquid crystal display device is connected between an n-th horizontal line and a pixel electrode disposed on an n-th horizontal line selected by a scan pulse of an n-th gate line. It further comprises a storage capacitor.

In addition, according to an embodiment of the present invention, a plurality of data lines to which video data is applied, a plurality of gate lines intersecting the plurality of data lines, and a scan pulse is supplied, intersecting the data lines and the gate lines. The driving method of a liquid crystal display device having a plurality of liquid crystal cells having a plurality of thin film transistors formed in a portion and turned on in response to the scan pulse, and a pixel electrode supplied with data voltages from the thin film transistors, has a slow scanning order. Decreasing the duty ratio of the gate shift clock toward the gate line; Generating a scan pulse whose duty ratio is sequentially reduced in response to a start pulse and the gate shift clock; And supplying the video data to the data lines in response to the scan pulse.

Reducing the duty ratio of the shift clock includes: counting an input clock to determine a position of the gate shift clock; And as a result of the determination, decreasing the delay amount of the gate shift clock as it goes to a gate line having a late scan order.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

5 illustrates a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 5, in the liquid crystal display according to the exemplary embodiment of the present invention, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gate lines ( A liquid crystal panel 102 in which G1 to Gn are crossed and a TFT is formed at the intersection thereof, a data driving circuit 104 for supplying a data signal to the data lines D1 to Dm of the liquid crystal panel 102; A gate driving circuit 106 for supplying a scan signal to the gate lines G1 to Gn, and a timing controller 108 for controlling the data driving circuit 104 and the gate driving circuit 106 are provided.

The liquid crystal panel 102 includes a plurality of liquid crystal cells Clc disposed in a matrix at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn. Each TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data lines D1 to Dm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line G. The storage capacitor Cst is formed between the liquid crystal cell Clc connected to the j th gate line (where j is a positive integer between 1 and n) and the j-1 th front gate line to form the liquid crystal cell Clc. Keep the voltage constant for one frame.

The gate driving circuit 106 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal GDC from the timing controller 108 to supply a horizontal signal to the liquid crystal panel 102. Select a line. This will be described in detail with reference to FIG. 6.

The data driving circuit 104 converts the digital video data R, G, and B into analog gamma voltages (data signals) corresponding to the gray scale values in response to the control signal DDC from the timing controller 108. The analog gamma voltage is supplied to the data lines D1 to Dm.

The timing controller 110 rearranges the data RGB supplied from the outside and supplies the data RGB to the data driving circuit 104. In addition, the timing controller 110 controls the gate control signal GDC and the data driving circuit 104 to control the gate driving circuit 106 by using the vertical / horizontal synchronization signals V and H and the clock CLK. Generates a data control signal DDC for control. Here, the control signal GDC for controlling the gate driving circuit 106 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output signal (GOE). Etc. are included. In addition, the control signal DDC for controlling the data driving circuit 104 includes a source start pulse (GSP), a source shift clock (SSC), and a source output signal (SOE). ) And the polarity signal (POL).

In particular, the gate shift clock GSC is generated such that the duty ratio decreases toward the gate line with a late scan order. This will be described in detail with reference to FIGS. 7 and 8.

FIG. 6 is a diagram illustrating a detailed configuration of the gate driving circuit shown in FIG. 5.

Referring to FIG. 6, the gate driving circuit 106 sequentially shifts the gate start pulse GSP to generate shift output signals Vs [1] to Vs [n] as shown in FIG. 5. 161 and the shift output signals Vs [1] to Vs [n] from the shift register 161 are scan signals Vg [1] to Vg [n] having a voltage level suitable for driving the thin film transistor TFT. ) And level shifters LS [1] to LS [n] for supplying the gate lines GL [1] to GL [n].

The shift register 161 includes a plurality of stages S [1] to S [n] connected in cascade. Each of the stages S [1] to S [n] is an input signal to be shifted as the gate start pulse GSP or the shift output signal Vs [1 of the previous stages S [1] to S [n-1]. ] To Vs [n-1]) to output shift output signals Vs [1] to Vs [n] shifted by one clock, that is, by one horizontal period. That is, the gate start pulse GSP is supplied to the first stage S [1] as an input signal to be shifted, and the second to nth stages S [2] to S [n] as an input signal to be shifted. The shift output signals Vs [1] to Vs [n-1] of the preceding stages S [1] to S [n-1] are supplied respectively, except for the first stage S [1]. An input signal input terminal to be shifted in the k-th stage S [k] is connected to an output terminal of the shift output signal Vs [k-1] of the k-th stage S [k-1].

The level shifters LS [1] to LS [n] are shift output signals Vs [1] to Vs [outputted from the respective stages S [1] to S [n] of the shift register 161, respectively. n]) is converted into scan signals Vg [1] through Vg [n] that swing between the gate low voltage Vgl and the gate high voltage Vgh to convert the gate lines GL [1] through GL [n]. Supplies). The gate high voltage Vgh is equal to or greater than the threshold voltage of the TFTs of the liquid crystal display panel 102, that is, the gate-on voltage, and the gate low voltage Vgl is less than the threshold voltage of the TFTs. That is, the gate-off voltage. On the other hand, the gate high voltage Vgh and the gate low voltage Vgl are supplied from an external voltage source.

7 and 8 are waveform diagrams illustrating a gate shift clock GSC in which a duty ratio decreases toward a gate line having a late scan order. For reference, in the exemplary embodiment of the present invention, a case where the gate shift clock GSC is implemented as the first to fourth clock signals C1 to C4 will be described as an example.

First, referring to FIG. 7, the first clock signal C1 is a control signal that controls the high logic section of the fourth k + 1 (k is an integer of 0 or more) th scan pulse generated by the gate driving circuit 106. The pulse width is set to W (4k + 1). The second clock signal C2 is a control signal for controlling the high logic section of the fourth scan pulse (k is an integer of 0 or more) generated from the gate driving circuit 106 and its pulse width is W (4k + 2). Is set to). The third clock signal C3 is a control signal for controlling the high logic section of the fourth scan pulse (k is an integer of 0 or more) generated by the gate driving circuit 106 and its pulse width is W (4k + 3). Is set to). The fourth clock signal C4 is a control signal for controlling the high logic section of the fourth scan pulse (k is an integer of 0 or more) generated by the gate driving circuit 106 and its pulse width is W (4k + 4). Is set to). Here, the pulse width W of the clock signal decreases as the value of k increases. That is, the pulse width W of the clock signal is set according to the relation W1> W2> ...> Wm so that the width of the high logic section becomes narrower as scan pulses are generated in a later order. To this end, the timing controller 108 includes a counter (not shown) to count the input clock and determine the number of scan pulses by which the gate shift clock GSC controls the scan pulse. In addition, the timing controller 108 uses a delay (not shown) based on the determined information to control the delay amount of the gate shift clock GSC corresponding to the gate line with a late scan order to decrease the delay amount of the clock signal. The relationship W1> W2> ... Wm is satisfied.

Next, referring to FIG. 8, the first clock signal C1 is a control signal for controlling a high logic section of a fourth k + 1 th (k is an integer greater than or equal to 0) th pulse generated from the gate driving circuit 106. The second clock signal C2 is a control signal for controlling a high logic section of the fourth scan pulse (k is an integer of 0 or more) generated by the gate driving circuit 106. The third clock signal C3 is a control signal for controlling a high logic period of the fourth scan pulse (k is an integer of 0 or more) generated by the gate driving circuit 106, and the fourth clock signal C4 is The control signal controls the high logic section of the fourth scan pulse (k is an integer of 0 or more) generated in the gate driving circuit 106. Here, the pulse width of the clock signal is set in accordance with the relation W1 = W2 = W3 = W4> W5 = W6 = W7 = W8> ... Wn-3 = Wn-2 = Wn-1 = Wn The late scan pulse block causes the width of the high logic section to be narrower. Here, one scan pulse block is composed of four scan pulses that are generated in succession. To this end, the timing controller 108 includes a counter (not shown) to count the input clock and determine whether the gate shift clock GSC is a signal for controlling the scan pulse of the block. In addition, the timing controller 108 uses a delay (not shown) based on the determined information to control the delay amount of the gate shift clock GSC corresponding to a scan pulse block having a slower scan order, thereby reducing the pulse of the clock signal. W1 = W2 = W3 = W4> W5 = W6 = W7 = W8> Wn-3 = Wn-2 = Wn-1 = Wn.

FIG. 9 is a diagram illustrating a circuit configuration of the first and second stages of the shift register and the first and second level shifters in the gate driving circuit shown in FIG. 6, and FIG. 10 is a drive signal waveform of the circuit shown in FIG. 9. 11 is a waveform diagram of first and second clock signals and first and second gate voltages corresponding thereto.

Hereinafter, the operation of the gate driving circuit 106 will be described with reference to FIGS. 9 to 11. On the other hand, the second to nth stages S [2] to S [n] of the shift register 161 are the previous stages S [1] to S [n-1 instead of the gate start pulse GSP as the shift input signal. Has the same circuit configuration as that of the first stage S [1] except that the shift output signals Vs [1] to Vs [n-1] are supplied, and the second to nth level shifters LS Since [2] to LS [n] also have the same circuit configuration as that of the first level shifter LS [1], the operation description is the first stage S [1] and the first level of the shift register 161. The shifter LS [1] is used as a reference, and a description thereof will be omitted. For convenience of explanation, only the case where the pulse width of the gate shift clock (GSC) signal shown in FIG. 7 is W1> W2> ... Wn will be described as an example.

First, referring to FIGS. 9 and 10, the gate start pulse GSP is the high logic voltage and the first and fourth transistors during the t1 period during which the first and second clock signals C1 and C2 maintain the low logic voltage. It is supplied to the gate electrodes of T1 and T4 to turn on the first and fourth transistors T1 and T4. At this time, while the voltage V _N1 on the first node N1 rises to the intermediate voltage Vm, the fifth transistor T5 is turned on but the first clock signal C1 is maintained at the low logic voltage. The voltage on the node N3, that is, the first shift output signal Vs [1], maintains a low logic voltage. As the voltage V _N2 on the second node _N2 is lowered by the turn-on of the fourth transistor T4, the second transistor T2 and the sixth transistor T6 are turned off, and thus the first and second transistors T4 and T6 are turned off. The discharge paths of the third nodes N1 and N3 are blocked.

During the t2 period, the gate start pulse GSP is inverted to a low logic voltage while the first clock signal C1 is inverted to a high logic voltage. At this time, the first transistor T1 and the fourth transistor T4 are turned off, and the voltage V _N1 on the first node N1 is a fifth transistor supplied with the high logic voltage of the first clock signal C1. As the voltage charged to the parasitic capacitance between the drain electrode and the gate electrode of T5 is added, the voltage rises above the threshold voltage of the fifth transistor T5. That is, the voltage V _N1 on the first node N1 rises to a voltage Vh higher than the t1 period by bootstrapping. Accordingly, the fifth transistor T5 is turned on during the t2 period, and the first shift output signal Vs [1] is the voltage of the first clock signal C1 supplied by the conduction of the fifth transistor T5. Rise up and invert to high logic voltage. When the shift output signal Vs [1] of the first stage S1 is inverted to a high logic voltage, the seventh transistor T7 of the first level shifter LS [1] is turned on so that the first gate line is turned on. The gate high voltage Vgh is supplied to GL [1]. As such, the gate high voltage Vgh supplied to the first gate line GL [1] is turned on to turn on the thin film transistors TFTs having the gate electrode connected to the first gate line GL [1]. The data voltage Vd is supplied to Clc).

During the t3 period, the first clock signal C1 is inverted to a low logic voltage and the second clock signal C2 is inverted to a high logic voltage. At this time, the high potential power voltage Vdd is supplied to the second node N2 via the third transistor T3 which is turned on in response to the second clock signal C2 to supply the voltage on the second node N2 ( V _N2 ) is raised. The rising voltage V _N2 on the second node N2 turns on the second transistor T2 to discharge the voltage V _N1 on the first node _N1 to the base voltage Vss. The sixth transistor T6 is turned on to discharge the voltage on the third node N3 to the base voltage Vss. When the voltage on the third node N3 is discharged to the base voltage Vss, that is, when the shift output signal Vs [1] of the first stage S1 is inverted to a low logic voltage, the first level shifter LS [ 1]), the seventh transistor T7 is turned off. At this time, the eighth transistor T8 of the first level shifter LS [1] is turned on by the second clock signal C2, and the gate low voltage Vgl is supplied to the first gate line GL. Thus, the gate low voltage Vgl supplied to the first gate line GL [1] turns off the thin film transistors TFTs having the gate electrode connected to the first gate line GL [1].

When the second clock signal C2 is inverted to a low logic voltage during the t4 period, the third transistor T3 is turned off. At this time, the high logic voltage is floating on the second node N2. The high logic voltage floated on the second node N2 until the fourth transistor T4 is turned on by the gate start pulse GSP in the next frame period until the voltage of the second node N2 is discharged. maintain.

As described above, the section in which the shift output signal Vs [1] of the first stage S [1] shows the high logic voltage is determined according to the width of the high logic section of the first clock signal C1. The section in which the shift output signal Vs [2] of the second stage S [2] shows the high logic voltage is determined according to the width of the high logic section of the second clock signal C2. Further, the high logic section of the first shift output signal Vs [1] determines the high logic section of the gate voltage Vg [1] supplied to the first gate line GL [1], and the second shift. The high logic section of the output signal Vs [2] determines the high logic section of the gate voltage Vg [2] supplied to the second gate line GL [2], resulting in a duty ratio of each clock signal. Determines the duty ratio of the gate voltage supplied to each gate line. As described with reference to FIG. 7, since the width of the high logic section of the gate shift clock according to the embodiment of the present invention is smaller than the first clock signal C1, the second clock signal C2 is smaller than that shown in FIG. 10. Similarly, the width of the high logic section of the gate voltage Vg [2] supplied to the second gate line GL [2] is the gate voltage Vg [1] supplied to the first gate line GL [1]. It is narrower than the width of the high logical section. That is, the driving method of the liquid crystal display according to the present invention decreases the duty ratio of the clock signal as the gate shift clock GSC corresponding to the gate line with the late scan order decreases the duty ratio of the gate voltage Vg according to the scan order. To be gradually reduced. Accordingly, as the liquid crystal cell is further away from the gate driving circuit, the width of the high logic section of the gate voltage for charging the data voltage to the liquid crystal cell Clc gradually decreases. That is, the conduction time of the thin film transistor connected to the gate line with a slower scanning order is set less than the conduction time of the thin film transistor connected to the gate line with a faster scanning order, so that the period during which the data voltage is charged decreases as the scanning order is late. Accordingly, the problem that the data voltage charged in the liquid crystal cell increases as the distance from the data driving circuit 104 increases in implementing the same gradation.

Meanwhile, in the gate driving circuit 106 illustrated in FIG. 6, the shift register 161 and the level shifters LS [1] to LS [n] are other known shift registers and level shifters in addition to the circuit illustrated in FIG. 9. Can be replaced with.

As described above, the liquid crystal display and the driving method thereof according to the present invention control the duty ratio of the clock signal to decrease as the gate shift clock corresponding to the gate line having the slower scan order decreases the duty ratio of the gate voltage according to the scan order. To be reduced. Accordingly, as the liquid crystal cell moves away from the gate driving circuit, the width of the high logic section of the gate voltage gradually decreases, and the amount of charge charged in the liquid crystal cell increases in proportion to the distance from the data driving circuit due to parasitic capacitance and the like. The flicker phenomenon generated by this can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (6)

A plurality of data lines to which video data is applied; A plurality of gate lines intersecting the plurality of data lines and supplied with a scan pulse; A plurality of thin film transistors formed at intersections of the data lines and the gate lines and turned on in response to the scan pulse; A plurality of liquid crystal cells having pixel electrodes supplied with data voltages from the thin film transistors; A gate driving circuit configured to sequentially generate the scan pulses and supply them to the gate lines in response to a start pulse and a gate shift clock; A data driving circuit converting digital video data into an analog data voltage and supplying the analog gamma voltage as the video data to the data lines; And And a control circuit for reducing the duty ratio of the gate shift clock as the scan line goes to a gate line having a late scan order. The method of claim 1, The control circuit, And a timing controller for supplying the digital video data to the data driving circuit and for controlling the operation timing of each of the gate driving circuit and the data driving circuit. The method of claim 2, The timing controller includes: And determining the position of the gate shift clock by counting an input clock, and controlling the delay amount of the gate shift clock to be smaller as the scan line goes to a later gate line. The method of claim 1, and a storage capacitor connected between the n-th horizontal line and the pixel electrode arranged on the n-th horizontal line selected by the scan pulse of the n-th gate line. LCD display device. A plurality of data lines to which video data is applied, a plurality of gate lines intersecting the plurality of data lines and supplied with scan pulses, formed at intersections of the data lines and the gate lines, and responding to the scan pulses. A method of driving a liquid crystal display device comprising a plurality of liquid crystal cells having a plurality of thin film transistors turned on and a pixel electrode supplied with a data voltage from the thin film transistor, Decreasing the duty ratio of the gate shift clock toward the gate line with a late scan order; Generating a scan pulse whose duty ratio is sequentially reduced in response to a start pulse and the gate shift clock; And And supplying the video data to the data lines in response to the scan pulse. 6. The method of claim 5, Reducing the duty ratio of the shift clock, Counting an input clock to determine a position of the gate shift clock; And And determining the delay amount of the gate shift clock as the scan line goes to a gate line having a late scan order.

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