KR101225423B1 - Liquid Crystal Display Panel Capable of Controlling View-angle and Liquid Crystal Display Device Thereof - Google Patents

Abstract

A liquid crystal panel capable of viewing angle control without degrading the brightness of an image is disclosed.

The liquid crystal panel is provided with a plurality of color pixels each having red, green, and blue sub pixels. Each of these color pixels has an interfering sub-pixel which is located on the same plane as them and controls the light transmitted in the lateral direction except the front side.

The viewing angle can be controlled by the interfering sub-pixels. In addition, the interfering sub-pixels are provided on the same plane with the color sub-pixels so that the thickness and weight do not increase. Furthermore, the reduction in the amount of light as well as the decrease in the luminance can be prevented.

Liquid crystal panel, viewing angle, interference, lateral, vertical electric field, horizontal electric field, plane.

Description

Liquid Crystal Display Panel Capable of Controlling View-angle and Liquid Crystal Display Device Thereof}

In order to better understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a cross-sectional view schematically showing a conventional liquid crystal panel capable of controlling a viewing angle.

2A to 2C are views for explaining the state of an image according to the viewing angle when the liquid crystal panel of FIG. 1 is driven in the narrow viewing angle mode.

3 is a plan view schematically illustrating a liquid crystal panel capable of controlling a viewing angle according to an exemplary embodiment of the present invention.

4 is a plan view schematically illustrating a liquid crystal panel capable of controlling a viewing angle according to another exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the liquid crystal panel of FIG. 3 and FIG. 4 taken along a line A-A '.

6A to 6C illustrate polarization characteristics of the liquid crystal panel illustrated in FIG. 5.

7 is a block diagram illustrating a liquid crystal display capable of controlling a viewing angle according to an exemplary embodiment of the present invention.

8A and 8B are views showing the state of the image on the liquid crystal panel seen from the side in the case of the narrow viewing angle mode and the wide viewing angle mode by the liquid crystal display of FIG.

FIG. 9 is a detailed block diagram illustrating an embodiment of an interference data generation unit in FIG. 7.

FIG. 10A is a diagram illustrating characteristics of reference luminance data used in the calculating unit of FIG. 9.

10B and 10C are diagrams for explaining an example of the interfering sub pixel data calculated by the calculating unit of FIG. 9.

FIG. 11 is a flowchart for describing an operation procedure of an interference data generating unit having the configuration shown in FIG. 9.

FIG. 12 is a detailed block diagram illustrating another exemplary embodiment of the interference data generator of FIG. 7.

FIG. 13 is a diagram illustrating a memory map of the memory illustrated in FIG. 12.

FIG. 14 is a detailed block diagram illustrating another embodiment of the interference data generator shown in FIG. 7 in detail.

FIG. 15 is a flowchart for describing an operation procedure of a memory controller illustrated in FIG. 14 in detail.

16 is a block diagram illustrating a liquid crystal display capable of controlling a viewing angle according to another exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS to the main parts of the drawings "

10: normal panel 12: interference panel

30,30A: liquid crystal panel 31: lower glass substrate

32: gate insulating film 33: protective layer

34A, 34B: first and second pixel electrodes 35A, 35B: first and second common electrodes

36: upper glass substrate 37: black matrix

38: color filter 39: overcoat layer

40: interference data generation unit 42,42A: video data combination unit

44,44A: Gate Driver 46,46A: Data Driver

48,48A: Timing control unit 50: Register

52: data collecting unit 54: calculating unit

56: selection unit 58, 72: memory control unit

60,70: Memory PXC: Color Pixel

RSP: Red Sub Pixel GSP: Green Sub Pixel

BSP: blue subpixel ESP: interference subpixel

CLC: liquid crystal cell MN: thin film transistor

The present invention relates to a liquid crystal panel capable of controlling the viewing angle of an image and a liquid crystal display including the same.

The liquid crystal display device displays an image by controlling an intensity of an electric field applied to the liquid crystal to adjust an amount of light passing through the liquid crystal. Since a liquid crystal panel, which is a main component of such a liquid crystal display, displays an image by using light from the outside, it is inevitably limited in the angle (that is, the viewing angle) at which the user can view the image. In order to enlarge the limited viewing angle of the liquid crystal panel, a liquid crystal panel has been introduced with a method of applying an electric field in a horizontal direction, a method using a compensation film, and a multi-division mode method using an opening pattern or protrusion on a transparent electrode. By such a lateral electric field driving method, a compensation film method and a multi-division mode method, the liquid crystal panel can secure a viewing angle of sufficient size.

In recent years, users of information terminals such as mobile phones, personal digital assistants (hereinafter referred to as "PDAs"), computers, and the like require users to prevent others from reading information. In response to requests for confidentiality and security of such information terminals, liquid crystal displays used as display devices of information terminals are also required to accommodate not only a large viewing angle mode but also a small viewing angle mode.

In order to satisfy the demands of the multiple viewing angle mode, a dual structure liquid crystal panel has been proposed. The liquid crystal panel of the dual structure is composed of a top panel 10 for displaying an image as shown in FIG. 1 and an interference panel 12 positioned on the top panel 10. The top panel 10 is used to display an image while the interfering panel 12 causes the light traveling toward the side of the panel to interfere. The liquid crystal panel of the dual structure enables switching of the viewing angle mode for the image by the optical interference by the interference panel 12.

The viewing angle controllable liquid crystal display device including the dual structure liquid crystal panel selectively drives the interference panel 12 to implement a wide viewing angle mode and a narrow viewing angle mode. In other words, the liquid crystal display causes the interference panel 12 to be turned on or turned off depending on the viewing angle mode.

In such a dual structure liquid crystal panel, since the external light must pass through the double liquid crystal layer, the brightness of the image is significantly lowered. In addition, the liquid crystal panel of the dual structure causes thickness and weight to increase. In addition, even in the liquid crystal display capable of controlling the viewing angle including the dual structure liquid crystal panel, in the narrow viewing angle mode in which the interference panel is turned on, the image from the front as shown in FIG. 2A is the same as in FIGS. 2B and 2C. Faintly seen on the left and right. For this reason, the liquid crystal display device containing the liquid crystal panel of the dual structure was difficult to achieve airtightness and security.

Accordingly, an object of the present invention is to provide a liquid crystal panel capable of controlling the viewing angle without deteriorating the brightness of an image.

Another object of the present invention is to provide a liquid crystal panel capable of controlling the viewing angle without increasing the thickness and weight.

Another object of the present invention is to provide a liquid crystal display device capable of controlling the viewing angle, which enables confidentiality and security of a user.

According to an aspect of the present invention, there is provided a viewable angle controllable liquid crystal panel, including: a plurality of color pixels each having red, green, and blue subpixels; And a plurality of interfering subpixels positioned on the same plane as the color pixels and included in each of the color pixels to control light transmitted from the side direction except for the front side.

The sub-pixels included in each of the color pixels are arranged to be connected to a pair of gate lines and a pair of data lines.

The sub-pixels included in each of the color pixels may be arranged to be commonly connected to one gate line and to each of four data lines.

The red, green, and blue sub-pixels are driven by a horizontal electric field, and the interfering sub-pixels are driven by a vertical electric field.

A plate-shaped pixel electrode in which the red, green, and blue sub-pixels include at least one or more band-shaped common electrodes alternately arranged with at least one or more band-shaped pixel electrodes, and the interference sub-pixels face each other; It includes a plate-shaped common electrode.

According to another aspect of the present invention, there is provided a liquid crystal display capable of controlling a viewing angle, comprising: a data driver configured to supply a pixel driving signal input by the sub pixels on the liquid crystal panel by one line; An interference data generator for generating interference data supplied to the interference sub pixels; And a data combination unit for adding the interference data to the video data supplied toward the data driver.

The interference data generation unit may include a memory in which interference sub-pixel data for implementing an image including an interference pattern is stored; And a memory controller for controlling a read operation of the memory.

The interference data generator may include an op-cept sub-pixel data generator having a logic value corresponding to an offset voltage; And a selector for selectively transmitting offset subpixel data from the offset subpixel data generator and interfering subpixel data from the memory to the data combination unit in response to the optical / narrow mode control signal. It can be provided as.

Preferably, the offset sub-pixel data generation unit includes any one of a register and a switch element.

The memory may further store offset sub-pixel data having a logic value corresponding to the offset voltage. In this case, the memory controller controls the memory such that the interfering subpixel data and the offset subpixel data stored in the memory are selectively read and supplied to the data combination unit in response to the optical / narrow mode control signal. desirable.

The interference data generating unit calculates and calculates the interference sub pixel data based on a data collecting unit for collecting red, green and blue sub pixel data included in the video data and the collected sub pixel data from the data collecting unit. An operation unit may be provided to supply the interfering sub-pixel data to the data combination unit.

The calculating unit causes the interfering sub-pixel data to be distributed at the reference gray level.

The computing unit sets the sum of the red, green, blue, and interfering sub-pixel data of any one gradation level lower than the maximum gradation level as reference luminance data, and the red, green collected from the collecting unit from the reference luminance data. And subtracting the sum of the blue sub pixel data to calculate the interfering sub pixel data.

The calculating unit may include a processor for performing the operation of the interfering sub-pixel data from the collected red, green and blue sub-pixel data from the collecting unit and the collected red, green and blue sub-pixel data from the collecting unit. It may be provided with any one of the look-up table for supplying the interfering sub-pixel data to the data combination unit.

The interference data generator may include an op-cept sub-pixel data generator having a logic value corresponding to an offset voltage; And a selection unit for selectively transmitting offset sub-pixel data from the offset sub-pixel data generator and interference sub-pixel data from the calculation unit toward the data combination unit in response to the optical / narrow mode control signal. It may be.

According to the above configuration, the viewing angle controllable liquid crystal panel according to the present invention can control the viewing angle including interference subpixels in addition to the color subpixels. In addition, the liquid crystal panel according to the present invention allows the interfering sub-pixels to be provided on the same plane together with the color sub-pixels so that the thickness and the weight do not increase. In addition, the liquid crystal panel allows the interfering sub-pixels to be provided on the same plane together with the color sub-pixels, so that not only the viewing angle can be controlled by a single liquid crystal layer but also the light amount can be prevented and the luminance can be prevented.

In addition, the viewing angle controllable liquid crystal display device according to the present invention causes the interfering subpixels on the liquid crystal panel to be driven by the interfering subpixel data forming an image of the interference pattern. This causes the image to be seen to the side of the liquid crystal panel to be changed. As a result, the viewing angle controllable liquid crystal display device according to the present invention enables enhanced confidentiality and security.

In addition to the object of the present invention as described above, other objects, other advantages and other features of the present invention will become apparent from the detailed description of the preferred embodiment with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view schematically illustrating a liquid crystal display including a liquid crystal panel according to an exemplary embodiment of the present invention.

In the liquid crystal panel 30 of FIG. 3, subpixels are disposed in respective regions divided by a plurality of data lines DL1 through DL2m arranged in a horizontal direction and a plurality of gate lines GL1 through GL2n arranged in a vertical direction. (RSP11 ~ RSPmn, GSP11 ~ GSPmn, BSP11 ~ BSPmn, ESP11 ~ ESPmn) are prepared. Each of these sub-pixels RSP11 to RSPmn, GSP11 to GSPmn, BSP11 to BSPmn, and ESP11 to ESPmn each includes a data line in response to a scan signal on the liquid crystal cell CLC and the gate line GL connected to the common electrode Vcom. The thin film transistor MN for switching the sub pixel driving signal to be transmitted from the DL to the liquid crystal cell CLC is provided. Among the sub pixels, the red sub pixels RSP11 to RSPmn are connected to the odd gate lines GL1 to GL2n-1 and the odd data lines DL1 to DL2m-1, respectively, and the green sub pixels GSP11 to GSPmn are connected to each other. ) Are connected to the odd-numbered gate lines GL1 to GL2n-1 and even-numbered data lines DL2 to DL2m, respectively, and the blue sub-pixels BSP11 to BSPmn are respectively the even-numbered gate lines GL2 to GL2n and even. The interfering sub-pixels ESP11 to ESPmn are connected to the even-numbered gate lines GL2 to GL2n and the odd-numbered data lines DL1 to DL2m-1, respectively. In addition, the interference sub-pixels ESP11 to ESPmn may be controlled in a pair with the red, green, and blue sub-pixels RSP11 to RSPmn, GSP11 to GSPmn, and BSP11 to BSPmn adjacent to each other in the up and right directions. Color pixels PXC11 to PXCmn are constituted. Accordingly, the first and second color pixels PXC11 of the first line are commonly connected to the first gate line GL1 and red and green subpixels connected to the first and second data lines DL1 and DL2, respectively. It includes common and connected to the RSP11 and GSP11 and the second gate line GL2, and the interference and blue subpixels ESP11 and BSP11 connected to the first and second data lines DL1 and DL2, respectively. In this manner, the last color pixel PXCmn of the last line is also commonly connected to the 2n-1th gate line GL2n-1 and connected to the 2m-1 and 2mth data lines DL2m-1 and DL2m, respectively. Interference and blue subpixels commonly connected to the red and green subpixels RSPmn and GSPmn and to the 2nth gate line GL2n and connected to the 2m-1 and 2mth data lines DL2m-1 and DL2m, respectively. (ESPmn, BSPmn).

Each of the red, green, and blue sub-pixels RSP11 to RSPmn, GSP11 to GSPmn, and BSP11 to BSPmn is driven in a horizontal electric field to display an image so that it can be viewed from a wide angle. On the other hand, each of the interfering sub-pixels ESP11 to ESPmn is driven in a vertical electric field manner, so that the image to be viewed from the side except the front side is selectively interfered with the interfering sub-pixel signal. When the image to be seen from the side is interfered by these interfering sub-pixels ESP11 to ESPmn, the image displayed on the liquid crystal panel 30 may be viewed only in a narrow angle range based on the definition of the liquid crystal panel 30. do. In other words, when there is interference by the interfering sub-pixels ESP11 to ESPmn, the liquid crystal panel 30 causes the image of the narrow viewing angle mode to be displayed. In contrast, when there is no interference by the interfering sub-pixels ESP11 to ESPmn, the image of the wide viewing angle mode is displayed on the liquid crystal panel 30.

4 is a view illustrating a liquid crystal panel that can control a field angle according to another exemplary embodiment of the present invention.

Referring to FIG. 4, in the liquid crystal panel 30A, regions separated by a plurality of data lines DL1 through DL4m arranged in a horizontal direction and a plurality of gate lines GL1 through GLn arranged in a vertical direction, respectively. Sub-pixels RSP11 to RSPmn, GSP11 to GSPmn, BSP11 to BSPmn, and ESP11 to ESPmn are provided. Each of these sub-pixels RSP11 to RSPmn, GSP11 to GSPmn, BSP11 to BSPmn, and ESP11 to ESPmn each includes a data line in response to a scan signal on a liquid crystal cell CLC and a gate line GL connected to a common electrode Vcom. The thin film transistor MN for switching the sub pixel driving signal to be transmitted from the DL to the liquid crystal cell CLC is provided. Among these sub-pixels, the red sub-pixels RSP11 to RSPmn are connected to the 4k-3rd data lines DL1 to DL4m-3, respectively, and the green sub-pixels GSP11 to GSPmn are respectively connected to the 4k-2nd data line. Blue subpixels BSP11 to BSPmn are connected to the 4k-1 th data lines DL3 to DL4m-1, and interference subpixels ESP11 to ESPmn are each 4k. It is connected to the first data line DL4 to DL4m.

In addition, each of the interfering sub-pixels ESP11 to ESPmn can be controlled in a pair with the red, green, and blue sub-pixels RSP11 to RSPmn, GSP11 to GSPmn, and BSP11 to BSPmn disposed adjacent to each other in the left direction. Color pixels PXC11 to PXCmn are constituted. Accordingly, the first color pixel PXC11 of the first line is commonly connected to the first gate line GL1 and red, green, blue, and interference connected to the first to fourth data lines DL1 to DL4, respectively. The sub pixels RSP11, GSP11, BSP11, and ESP11 are included. In this form, the last color pixel PXCmn of the last line is also connected to the nth gate line GLn and the red and green subs connected to the 4m-3 to 4mth data lines DL4m-3 and DL4m, respectively. Pixels RSPmn, GSPmn, BSPmn, and ESPmn are included.

Each of the red, green, and blue sub-pixels RSP11 to RSPmn, GSP11 to GSPmn, and BSP11 to BSPmn is driven in a horizontal electric field to display an image so that it can be viewed from a wide angle. On the other hand, each of the interfering sub-pixels ESP11 to ESPmn is driven in a vertical electric field manner, so that the image to be viewed from the side except the front side is selectively interfered with the interfering sub-pixel signal. When the image to be seen laterally is interfered by these interfering sub-pixels ESP11 to ESPmn, the image displayed on the liquid crystal panel 30A can be viewed only in a narrow angle range with respect to the front side of the liquid crystal panel 30A. do. In other words, when there is interference by the interfering sub-pixels ESP11 to ESPmn, the liquid crystal panel 30A causes the image of the narrow viewing angle mode to be displayed. On the contrary, in the case where there is no interference by the interfering sub-pixels ESP11 to ESPmn, the image of the wide viewing angle mode is displayed on the liquid crystal panel 30A.

FIG. 5 is a cross-sectional view of the liquid crystal panel 30 of FIGS. 3 and 4 taken along a line A-A '. The structure of the color sub-pixels RSP, GSP, and BSP and the interfering sub-pixel ESP in FIGS. 3 and 4 will be described by the cross-sectional view of FIG. 5.

The liquid crystal panels 30 and 30A of FIG. 5 include a liquid crystal layer CL positioned between the lower glass substrate 31 and the upper organic substrate 36. The gate insulating layer 32, the data line DL, and the protective layer 33 are sequentially formed on the lower glass substrate 31. A thin film transistor and a gate line (not shown) are formed between the gate insulating film 32 and the lower glass substrate 31. The data line DL is electrically connected to the thin film transistor via the gate insulating layer 32. The left half of the gate line DL corresponds to the blue subpixel BSP, and the right portion of the gate line DL corresponds to the interfering subpixel ESP. The first pixel electrodes 24A and the common electrodes 35A are alternately formed on a surface of the passivation layer 33 positioned on the left half of the data line DL. On the other hand, the second pixel electrode 34B is formed on the surface of the protective layer 33 of the right half of the data line DL. The first pixel electrodes 34A and the first common electrodes 35A are formed in the shape of a band, while the second pixel electrode 34B is formed in the shape of a flat plate having a size of an area of the sub-pixel.

A black matrix 37 is formed on the bottom surface of the upper glass substrate 36 to divide the sub pixel region. Among the pixel regions divided by the black matrix 37, each of the color sub pixel regions includes a color filter (that is, a blue filter in the blue sub pixel region BSP located at the left half of the data line DL). 38) is formed. The overcoat layer 39 is formed on the surfaces of the black mattress 37 and the color filter 38. The second common electrode 35B having the size of the sub pixel region is formed in the right half of the overcoat layer 39 (that is, the right region of the data line DL).

As described above, the blue sub-pixel ESP is formed in the horizontal direction on the liquid crystal layer CL by the first pixel electrodes 34A and the first common electrodes 35A that are alternately arranged on the lower glass substrate 31. Let is applied. Then, the liquid crystal molecules CLCM included in the blue sub-pixel BSP responsive to the voltage applied between the first pixel electrodes 34A and the first common electrodes 35A are illustrated in FIG. 6A. Likewise, as the viewing angle increases toward the side toward the front, the light transmitted is polarized so that the amount of light decreases. Accordingly, the image displayed on the liquid crystal panels 30 and 30A is also viewed from the side of the wide angle with respect to the front surface of the liquid crystal panels 30 and 30A. In other words, the liquid crystal panels 30 and 30A cause the image of the wide viewing angle mode to be displayed.

On the other hand, the interfering sub-pixel ESP is perpendicular to the liquid crystal layer CL by the second pixel electrode 34B and the second common electrode 35B disposed on the lower and upper glass substrates 31 and 36, respectively, facing each other. Allow an electric field in the direction to be applied. The liquid crystal molecules CLME in the interfering sub-pixel ESP corresponding to the magnitude of the vertical electric field applied between the second pixel electrode 34B and the second common electrode 35B are as shown in FIG. 6B. On the basis of the front surfaces of the liquid crystal panels 30 and 30A, the light is polarized so as to maximize the amount of light on the side of about 40 ° on both sides. In other words, the liquid crystal molecules CLMe included in the interfering sub-pixel ESP polarize the light to move toward both sides except the front side. The light traveling toward the side by the interfering sub-pixel ESP is summed with the light traveling toward both sides via the other red and green sub-pixels RSP and GSP including the blue sub-pixel BSP, and FIG. 6C. As shown in FIG. 2, the amount of light traveling toward the side of the liquid crystal panel 30 and 30A toward the side at a 40 ° angle is maximized, whereas the amount of light is decreased at the front side of the liquid crystal panels 30 and 30A. Will have The amount of light from the interfering sub-pixel ESP that is transmitted at an angle of about 40 ° on both sides with respect to the front of the liquid crystal panels 30 and 30A is added to the amount of light from the blue sub-filter BSP so that the liquid crystal panel 30 An image of information different from the original information is displayed on the liquid crystal panels 30 and 30A to be viewed at an angle of 40 degrees on both sides of the side.

As described above, the liquid crystal panels 30 and 30A including the interfering sub-pixels ESP in addition to the color sub-pixels RSP, GSP, and BSP can control the viewing angle. In addition, in the liquid crystal panels 30 and 30A, the interfering sub-pixel ESP is disposed on the same plane along with the color sub-pixels RSP, GSP, and BSP so that the thickness and the weight thereof do not increase. In addition, the liquid crystal panels 30 and 30A together with the color sub-pixels RSP, GSP, and BSP allow the interfering sub-pixels ESP to be provided on the same plane, so that the viewing angle can be controlled by only one liquid crystal layer and the amount of light can be obtained. Can be prevented, as well as a decrease in luminance.

7 is a block diagram illustrating a liquid crystal display capable of controlling a viewing angle according to an exemplary embodiment of the present invention.

The liquid crystal display of FIG. 7 includes an interference data generator 40 for generating interference data to be supplied to the interfering sub-pixels ESP11 to ESPmn on the liquid crystal panel 30, and the interference from the interference data generator 40. And a video data combination unit 42 for adding the data IDF to the video data VD from the outside. As shown in FIG. 3, the liquid crystal panel 30 includes red subpixels RSP11 to RSPmn connected to the odd gate lines GL1 to GL2n-1 and the odd data lines DL1 to DL2m-1. Green sub-pixels GSP11 to GSPmn, odd-numbered gate lines GL2 to GL2n, and odd-numbered data lines DL1 connected to the odd-numbered gate lines GL1 to GL2n-1 and the even-numbered data lines DL2 to DL2m. To the blue subpixels BSP11 to BSPmn connected to the DL2m-1, and the interference subpixels ESP11 to ESPmn connected to the even-numbered gate line GL2 to GL2n and the even-numbered data line DL2 to DL2m. M x n color pixels PXC11 to PXCmn are included.

The interference data generator 40 switches a wider or narrower viewing angle of the liquid crystal panel 30 in response to the optical / narrow mode control signal W / N from an external video source (for example, a computer graphics card). To the video data combination unit 42. This interference data IFD refers to the front side of the liquid crystal panel 30 when the light / narrow mode control signal W / N has a specific logic (e.g., high logic or low logic) that specifies the narrow viewing angle mode. This includes interfering sub-pixel data Ed forming an image of a fixed interference pattern that allows interfering light to be added to both sides. Alternatively, the interference data IDF may include interfering sub pixel data Ed, which constitutes an interference pattern that varies from image to image. In order to generate the interference data IDF of the interference pattern that varies from image to image, the interference data generator 40 may input video data VD from an external video source (for example, a graphic card of a computer). have. On the other hand, when the light / narrow mode control signal W / N has initialization logic (for example, low logic or high logic) for designating the wide viewing angle mode, the interference data IDF is generated from the liquid crystal panel 30. Off-set sub-pixel data Eoff having an offset value that prevents the interfering light from traveling toward both sides with respect to the front side.

The video data combination unit 42 inputs video data VD including color sub pixel data for red, green, and blue sub pixels RSP, GSP, and BSP from an external video source (not shown). do. The video data combiner 42 adds the interference data IDF from the interference data generator 40 to the video data VD. In addition, the video data combiner 42 rearranges and combines the color sub pixel data and the interference (or offset) sub pixel data Ed (or Eoff) to match the arrangement state of the sub pixels on the liquid crystal panel 30. Allow video data (CVD) to be generated. The combined video data CVD provided by the video data combination unit 42 includes red and green sub-pixels RSP and GSP connected to the odd-numbered gate lines GL1 to GL2n-1 of the liquid crystal panel 30. ) Includes a sub-pixel data stream in which the red and green sub-pixel data Rd and Gd are alternated, while the interference and the blue sub-connected to the even-numbered gate lines GL2 to GL2n of the liquid crystal panel 30 are scanned. When the pixels ESP and BSP are scanned, an interference (or offset) and a blue sub data Ed (or Eoff, Bd) include a sub pixel data stream alternately.

In addition, the liquid crystal display according to the exemplary embodiment may include a gate driver 44 for sequentially driving the gate lines GL1 to GL2n on the liquid crystal panel 30, and data lines on the liquid crystal panel 30. Data driver 46 for driving DL1 to DL2m, and a timing control unit 48 for controlling the operation timing of these data and gate drivers 44,46. The gate driver 44 generates 2n scan signals that sequentially enable the gate lines GL1 to GL2n in response to the gate timing signal GTS from the timing control unit 48.

The data driver 46 responds to the data timing signal DTS from the timing control unit 48 so that each time one of the gate lines GL1 to GL2n is enabled, the 2m data lines DL1 to The sub pixel driving signals are supplied on the DL2m. For this purpose, the data driver 46 inputs the combined video data CVD transmitted in the serial form from the video data combining unit 42. When a column of the red and green sub-pixels RSP and GSP connected to any of the odd-numbered gate lines GL1 to GL2n-1 is scanned, the data driver 46 stores the red and green sub-pixel data Rd and Gd. ) Is supplied with alternating sub data streams to supply a red sub pixel driving signal to each of the odd-numbered data lines DL1 to DL2m-1 and a green sub pixel driving signal to each of the even-numbered data lines DL2 to DL2m. To be. On the other hand, when a column of the interference and blue sub-pixels ESP and BSP connected to one of the even-numbered gate lines GL2 to GL2n is scanned, the data driver 46 may detect the interference (or offset) and the blue sub. Input the sub data stream in which the pixel data Ed (or Eoff, Bd) are alternately input, and each of the odd-numbered data lines DL1 to DL2m-1 has an interfering sub-pixel driving signal and even-numbered data lines DL2 to DL2m. ) Are supplied with blue sub-pixel driving signals.

The interfering sub-pixel driving signal has a specific logic for specifying the narrow viewing angle when the light / narrow mode control signal W / N specifies the narrow viewing angle, so that the interfering sub-pixel ESP is opposite to the front side of the liquid crystal panel 30. It has a voltage that allows the interfering light to be transmitted. The amount of light transmitted to both sides by the interfering sub-pixel ESP is adjusted according to the voltage level of the interfering sub-pixel driving signal. The amount of light transmitted to both sides by the interfering sub-pixels ESP is added to the amount of light transmitted to both sides by the red, green, and blue sub-pixels RSP, GSP, and BSP so that the luminance component from the side interferes. To be. As a result, as shown in FIG. 8A, an image which cannot be seen from the side is displayed on the liquid crystal panel 30. In addition, the interfering sub-pixel driving signals have different voltage levels at positions of the interfering sub-pixels ESP11 to ESPmn corresponding to the interference pattern, thereby causing a difference in luminance interference for each color pixel PXC. Accordingly, the image displayed on the liquid crystal panel 30 cannot be identified at all on both sides. As a result, secrecy and security in the narrow viewing angle mode are further enhanced.

On the contrary, when the light / narrow mode control signal W / N has initialization logic for specifying the wide viewing angle, the interfering sub-pixel ESP transmits the interfering light to both sides thereof including the front of the liquid crystal panel 30. In response to the offset pixel drive signal of the offset voltage. Due to the offset sub-pixel driving signal of the offset voltage, there is no light passing through the interfering sub-pixel ESP. Only the light transmitted to the front and both sides thereof. Accordingly, the image displayed on the liquid crystal panel 30 is clearly seen not only from the front but also from the side as in FIG. 8B.

Finally, the timing control unit 48 inputs synchronization signals (ie horizontal and vertical synchronization signals and a data clock) from an external video source. The tie control unit 48 generates the gate timing signal GTS to be supplied to the gate driver 44 and the data timing signal DTS to be supplied to the data driver 46 using the synchronization signals. In addition, the timing control unit 48 generates an interference control signal ECS necessary for the data generation operation of the interference data generating unit 40 and a combination control signal CCS necessary for the data combining operation of the video data combining unit 42. do.

FIG. 9 is a detailed block diagram illustrating an embodiment of the interference data generator 40 in FIG. 7 in detail.

Referring to FIG. 9, the interference data generating unit 40 includes a data collecting unit constituting a serial circuit with respect to the video data VD from the register 50 and an external video source (ie, a computer graphics card) ( 52, a calculation unit 54, and a selection unit 56 are provided. The register 50 stores the op-cept sub-pixel data Eoff corresponding to the offset value. This register 50 may be replaced with a plurality of switches that may generate offset sub-pixel data Eoff.

The data collecting unit 52 sequentially inputs red, green, and blue sub pixel data Rd, Gd, and Bd that are input in a serial form, and thus, the red, green, and blue sub pixel data Rd, Gd, Bd) is simultaneously transmitted to the calculation unit 54. To this end, the data collecting unit 52 responds to the first interference control signal ECS1 from the timing control unit 48 in FIG. As the first interference control signal ECS1, a data clock having the same period as that of the sub pixel data is preferably used. The data collector 52 sequentially shifts the red, green, and blue sub-pixel data Rd, Gd, and Bd from an external video source in response to the first interference control signal ECS1 such as a data clock. A shift register may be used.

The calculation unit 54 generates the interfering sub pixel data Ed by using the red, green, and blue sub pixel data Rd, Gd, and Bd collected by the data collecting unit 52. In order to input the collected red, green and blue sub-pixel data Rd, Gd, and Bd, the calculation unit 54 responds to the second interference control signal ECS2 from the timing control unit 48 in FIG. . The second interference control signal ECS2 has a frequency (that is, three times the period) of 1/3 of the first interference control signal ECS1. As the second interference control signal ECS2, a three-divided data clock is preferable. In order to calculate the interfering sub-pixel data Ed, the calculator 54 subtracts the red, green, and blue sub-pixel data Rd, Gd, and Bd collected from the reference luminance data Yd as in Equation 1. The reference luminance data Yd is any one gradation level lower than the maximum gradation level HGL each of the red, green, blue, and interfering sub-pixel data Rd, Gd, Bd, and Ed may have as shown in FIG. 10A. The reference gradation level REL is set and determined by the sum of the red, green, blue, and interfering sub-pixel data Rref, Gref, Bref, and Eref of the reference gradation level REL. The reference gray level REL is preferably an intermediate gray level that each sub-pixel data can have.

[Equation 1]

Ed = Yd-(Rd + Gd + Bd)

   = (Rref + Gref + Bref + Eref)-(Rd + Gd + Bd)

According to Equation 1, as the gradation level of each of the collected red, green, and blue sub-pixel data Rd, Gd, and Bd is lower than the reference gradation level REL (that is, close to the base gradation level). In addition, as shown in FIG. 10B, the interfering sub-pixel data Ed has a gradation level close to the maximum gradation level HGL, whereas the collected red, green and blue sub-pixel data Rd, Gd, Bd) As each gradation level becomes higher than the reference gradation level REL (i.e., closer to the maximum gradation level HGL) as in FIG. 10C, the interfering sub-pixel data Ed becomes closer to the base gradation level. It has a low gradation level.

Thus, the gray level is opposite to the gray level of the red, green, and blue sub pixel data in which the interfering sub pixel data Ed is collected, so that the luminance at the side of the color pixel PXC is distributed near the reference value. . By keeping the luminance at the side of the color pixel PXC constant at the reference value (for example, the intermediate luminance value), the image displayed on the liquid crystal panel 30 in the narrow viewing angle mode is completely absent from the side as in FIG. 8A. It will not be identified. As a result, the liquid crystal display device of the present invention further enhances confidentiality and security in the narrow viewing angle mode. A processor having an arithmetic function may be used as the arithmetic unit 54 that calculates such interference sub-pixel data Ed. Alternatively, the calculation unit 54 uses the collected red, green, and blue subpixel data Rd, Gd, and Bd as one address signal, and the interference stored at the address corresponding to the logical value of the subpixel data. It may be replaced by a look-up table that allows sub-pixel data Ed to be read. In this case, the look-up table is once each time three sub-pixel data (ie, red, green, and blue sub-pixel data Rd, Gd, and Bd) are input in response to the second interference control signal ECS2. The read operation is performed.

The selector 56 selects the offset sub-pixel data Eoff from the register 50 or the operation unit 54 according to the logic value of the optical / narrow mode control signal W / N from an external video source. The interfering sub-pixel data Ed is transmitted to the video data combiner 42 of FIG. 7 as the interfering data IFD. If the light / narrow mode control signal W / N has a specific logic (i.e., high logic or low logic) to specify the narrow viewing angle mode, the selector 56 selects the interfering sub-pixel data Ed from the calculator 54. ) Is supplied as the interference data IDF to the video data combination section 42 of FIG. Conversely, if the wide / narrow mode control signal W / N has initialization logic (i.e., low logic or high logic) that specifies the wide viewing angle, the selector 56 may offset the offset sub-pixel from the register 50. The data EFF is supplied to the video data combination section 42 of FIG. 7 as the interference data IDF.

FIG. 11 is a flowchart for explaining an operation procedure of the interference data generating unit 40 configured as shown in FIG.

Referring to FIG. 11, the interference data generator 40 checks whether the light / narrow mode control signal W / N is a specific logic (ie, high logic or low logic) designating a narrow viewing angle mode (S10). step). When the light / narrow mode control signal W / N has a specific logic for specifying the narrow viewing angle mode, the interference data generator 40 may red, green, and blue sub-pixel data Rdi, Gdi from an external video source. (Bdi) are sequentially input (step S12), and the input red, green, and blue sub-pixel data Rdi, Gdi, and Bdi are collected (step S14). Subsequently, the interference data generation unit 40 calculates the interference sub-pixel data Edi by Equation 2 using the collected red, green, and blue sub-pixel data Rdi, Gdi, and Bdi (step S16). The calculated interfering sub-pixel data Edi is supplied to the video data combining unit 42 as the interfering data IDF (step S18).

On the contrary, if the optical / narrow mode control signal W / N has initialization logic (that is, low logic or high logic) designating the wide viewing angle mode in step S10, the interference data generator 40 may offset the offset. The sub pixel data Eoff is supplied to the video data combiner 42 as the interference data IDF (step S20). After performing step S18 or step S20, the interference data generating unit 40 returns to step S10.

12 is a detailed block diagram illustrating another embodiment of the interference data generator 40 shown in FIG. 7 in detail. The interference data generator 40 of FIG. 12 includes a memory 58 and a memory controller 60 instead of the data collector 52 and the calculator 54 included in the interference data generator 40 of FIG. 9. Except that, it has the same configuration as the interference data generator 40 of FIG. Accordingly, components having the same name, function, and role as those of FIG. 9 among the components included in the interference data generator 40 of FIG. 12 will be referred to by the same reference numerals as in FIG. 9.

In FIG. 12, the memory 58 stores interfering subpixel data Ed of the number of interfering subpixels ESP11 to ESPmn on the liquid crystal panel 30 forming a specific interference pattern. The memory 58 is capable of updating the read-only memory or the interfering sub-pixel data Ed, in which the interfering sub-pixel data Ed is not erased even when the power is not supplied. A nonvolatile memory such as an EEPROM in which the interfering sub pixel data Ed is not erased can be used. In order to store the interfering sub-pixel data Ed forming a specific interference pattern, the memory 58 includes the same number of storage regions as the included interfering sub-pixels ESP11 to ESPmn of the liquid crystal panel 30. Some of the storage areas may store interfering sub-pixel data having a specific gray level and remaining sub-interference data having a lower or higher gray level than a specific gray level. For example, when interfering sub-pixel data Ed forming a black pattern of "b" is stored in the memory 58, as shown in FIG. 13, the n-th color pixel line n from the second line 02 as shown in FIG. -1) storage areas of the second and third rows, and storage areas of the n-th and n-th lines from the third column 03 to the m-th column m-1. Interference sub-pixel data Ed having a gradation level corresponding to black is stored therein, and interference sub-pixel data Ed having a gradation level corresponding to white is stored in the remaining storage areas. The memory 58 may store interfering sub-pixel data Ed corresponding to the number of interfering sub-pixels ESP11 to ESPmn on the liquid crystal panel 30 forming any interference pattern other than "b".

As such, the interfering sub-pixel data Ed forming an image of a specific interference pattern stored in the memory 58 uses red, green, and blue sub-pixel data Rd, Gd, and Bd included in the video data VD. In this case, the processing path of video data is simplified. As a result, the response speed of the video data combination unit 42 is improved.

The memory control unit 60 controls the memory 58 by using the interference control signal ECS from the timing control unit 48 in FIG. 7, and interfering sub-pixel data for one image stored in the memory 58. Causes Ed to be read sequentially. The interference control signal ECS supplied to the memory control unit 60 is a read mode control signal that periodically specifies a read operation period and a read that can cause the interfering sub-pixel data Ed to be read once during the read operation period. A clock can be included. Also, the memory controller 60 may respond to the light / narrow mode control signal W / N. In this case, the memory controller 60 performs a read operation only when the light / narrow mode control signal W / N has a specific logic for specifying the narrow viewing angle mode, thereby preventing unnecessary power consumption.

The selector 56 selects the offset sub-pixel data Eoff from the register 50 or from the memory 58 according to the logic value of the optical / narrow mode control signal W / N from an external video source. The interfering sub-pixel data Ed is transmitted to the video data combiner 42 of FIG. 7 as the interfering data IFD. Specifically, if the light / narrow mode control signal W / N has a specific logic (i.e., high logic or low logic) to specify the narrow viewing angle mode, the selector 56 may select from the memory 58. The interfering sub-pixel data Ed is supplied to the video data combining section 42 of FIG. 7 as the interfering data IDF. Conversely, if the wide / narrow mode control signal W / N has initialization logic (i.e., low logic or high logic) that specifies the wide viewing angle, the selector 56 may offset the offset sub-pixel from the register 50. The data EFF is supplied to the video data combination section 42 of FIG. 7 as the interference data IDF.

FIG. 14 is a detailed block diagram illustrating another embodiment of the interference data generator 40 shown in FIG. 7 in detail.

Referring to FIG. 14, the interference data generator 40 includes a memory controller 72 that controls a read operation of the memory 70. The memory 70 stores the interfering subpixel data Ed of the number of the interfering subpixels ESP11 to ESPmn on the liquid crystal panel 30 forming one image including a specific interference pattern. An image of the interference pattern stored in the memory 70 may be mapped to the memory 70 in the same manner as the image of the interference pattern stored in the memory 58 in FIG. 12. Therefore, a detailed description of the image of the specific interference pattern stored in the memory 70 will be omitted. In addition to the image of this particular interference pattern, the memory 70 stores the op-cept sub-pixel data Eoff corresponding to the offset value. As such, the memory 70 storing the offset sub-pixel data Eoff and the interfering sub-pixel data Ed forming an image of a specific interference pattern may not lose data even when no power is supplied. Only memory) or non-volatile memory such as EEPROM capable of updating data as well as not losing data even without a power supply may be used. The offset sub-pixel data Eoff or the interfering sub-pixel data Ed read out from the memory 70 are supplied to the video data combination unit 42 of FIG. 7 as the interference data IDF.

The memory control unit 72 controls the continuous read operation of the memory 70 by using the interference control signal ECS from the timing control unit 48 in FIG. 7, so that the offset sub-stored in the memory 70 is stored. Repeated reading of the pixel data Eoff or sequential reading of the interfering sub-pixel data Ed forming an image of a specific interference pattern is performed. In addition, the memory controller 72 displays an image of a specific interference pattern and offset sub-pixel data Eoff stored in the memory 70 in response to the light / narrow mode control signal W / N from an external video source. The interfering sub-pixel data Ed may be selectively read out. In fact, when the light / narrow mode control signal W / N has a specific logic for specifying the narrow viewing angle mode, the memory control unit 72 forms the interfering sub-pixel data forming an image of a specific interference pattern stored in the memory 70. (Ed) is sequentially read so as to be supplied to the video data combination section 42 of Fig. 7 as the interference data IDF. On the contrary, when the wide / narrow mode control signal W / N has initialization logic for specifying the wide viewing angle mode, the memory control unit 72 repeatedly repeats the offset sub-pixel data Eoff on the memory 70. It is read out and supplied as the interference data IDF to the video data combination section 42 of FIG.

As such, the memory controller 72 stores the op-cept sub data Eoff and the interfering sub pixel data Ed forming an image of a specific interference pattern, and the memory controller 72 responsive to the optical / narrow mode control signal W / N. The interference data generation unit 40 of FIG. 14 that includes) has a simpler circuit than the interference data generation unit 40 of FIG. 12.

FIG. 15 is a flowchart for explaining an operation procedure performed by the memory controller 72 illustrated in FIG. 14 step by step.

According to the flowchart of FIG. 15, the memory controller 72 determines whether a narrow viewing angle mode or a wide viewing angle mode is designated by checking a logic value of the light / narrow mode control signal W / N (step S30).

If the wide / narrow mode control signal W / N is a particular logic (e.g., high logic or low logic) specifying the narrow viewing angle mode, then the memory control unit 72 assigns an interference sub assigned to any one of its own registers. The pixel data flag is set to " 1 " to set the reading mode of the interfering sub pixel data Ed (step S32). In addition, the memory controller 72 sequentially specifies the storage areas of the memory 70 in which the image of the specific interference pattern is stored so that the interfering sub-pixel data Ed forming the image of the specific interference pattern is sequentially read out. Step S34). The sequentially read-out interference sub pixel data Ed is supplied to the video data combination unit 42 of FIG. 7 as the interference data IDF.

Conversely, if the wide / narrow mode control signal W / N is initialization logic (e.g., low logic or high logic) specifying the wide viewing angle mode, then the memory controller 72 is assigned to any one of the registers within itself. The interfering sub pixel data flag is reset to " 0 " to set the read mode of the offset sub pixel data Eoff (step S36). Also, the memory controller 72 repeatedly designates a storage area of the memory 70 in which the offset sub-pixel data Eoff is stored so that the offset sub-pixel data Eoff is repeatedly read. The repeatedly read-out interference sub-pixel data Eoff is supplied to the video data combination unit 42 of FIG. 7 as the interference data IDF.

16 is a block diagram illustrating a liquid crystal display capable of controlling a viewing angle according to another exemplary embodiment of the present invention.

Referring to FIG. 16, the liquid crystal display includes an interference data generator 40 for generating interference data to be supplied to the interference subpixels ESP11 to ESPmn on the liquid crystal panel 30A, and the interference data generator 40. And a video data combination unit 42A for adding the interference data IFD from the video data to the video data VD from the outside. As shown in FIG. 4, the liquid crystal panel 30A is connected to the 4k-3rd data lines DL1 to DL4m-3 and the red subpixels RSP11 to RSPmn and the 4k-2nd data lines DL2 to DL4m-. To the green sub-pixels GSP11 to GSPmn connected to 2), the blue sub-pixels BSP11 to BSPmn connected to the 4k-1th data lines DL3 to DL4m-1, and the 4kth data lines DL4 to DL4m. M x n color pixels PXC11 to PXCmn each having the connected interfering sub-pixels ESP11 to ESPmn.

The interference data generating unit 40 may cause the viewing angle of the liquid crystal panel 30A to be broadly or narrowly switched in response to the optical / narrow mode control signal W / N from the outside (for example, a computer graphics card). The data IDF is supplied to the video data combination unit 42A. This interference data IFD refers to the front side of the liquid crystal panel 30A when the light / narrow mode control signal W / N has a specific logic (e.g., high logic or low logic) that specifies the narrow viewing angle mode. And interfering sub-pixel data constituting a fixed interference pattern allowing interference light to be added to both sides. Alternatively, the interference data IDF may include interfering sub pixel data Ed, which constitutes an interference pattern that varies from image to image. In order to generate the interference data IDF of the interference pattern that varies from image to image, the interference data generator 40 may input video data from an external video source (for example, a graphic card of a computer). On the other hand, when the wide / narrow mode control signal W / N has initialization logic (for example, low logic or high logic) for specifying the wide viewing angle mode, the interference data IDF is generated by the liquid crystal panel 30A. It includes the interfering sub-pixel data Eoff of the offset value that prevents the interfering light from traveling on both sides with respect to the front side.

The video data combiner 42A inputs video data VD including color sub pixel data for red, green and blue sub pixels from an external video source (not shown). The video data combination unit 42A adds the interference data IDF from the interference data generation unit 40 to the video data VD so as to match the arrangement state of the subpixels on the liquid crystal panel 30A. The combination video data CVD, in which blue and interfering (or offset) sub-pixel data Rd, Gd, Bd, IFD (ie, Ed or Eoff) are sequentially and repeatedly arranged, is generated.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention may include a gate driver 44A for sequentially driving the gate lines GL1 to GL2n on the liquid crystal panel 30A, and data lines on the liquid crystal panel 30A. A data driver 46A for driving the DL1 to DL2m, and a timing control unit 48A for controlling the operation timing of these gates and the data drivers 44A and 46A. The gate driver 44A generates n scan signals for sequentially enabling the gate lines GL1 to GLn in response to the gate timing signal GTS from the timing control unit 48A.

The data driver 46A, in response to the data timing signal DTS from the timing control unit 48A, each time one of the gate lines GL1 to GL2n is enabled, the 4m data lines DL1 to. The sub pixel driving signals are supplied on the DL4m. For this purpose, the data driver 46A inputs the combined video data CVD transmitted in the serial form from the video data combining section 42A. Each time one of the gate lines GL1 to GL2n-1 is enabled, the data driver 46A is configured to transmit the red, green, blue, and interference (or offset) sub-pixel data Rd, Gd, Bd, and the like. Input a sub-pixel data stream in which IFD (Ed or Eoff)) is sequentially- altered to provide a red sub-pixel signal to each of the 4k-3rd data lines DL1 to DL4m-3, and a 4k-2nd data line DL2. DL4m-2) has a green sub-pixel driving signal, each of the 4k-1st data lines DL3-DL4m-1 has a blue subpixel driving signal, and each of the 4kth data lines DL4-DL4m has interference. (Or offset) causes the sub pixel drive signal to be supplied.

The interfering sub-pixel driving signal has both the sides of the interfering sub-pixel (ESP) with respect to the front side of the liquid crystal panel 30A when the light / narrow mode control signal W / N has a specific logic for specifying the narrow viewing angle. It has a voltage that allows the interfering light to be transmitted. The amount of light transmitted to both sides by the interfering sub-pixel ESP is adjusted according to the voltage level of the interfering sub-pixel driving signal. The amount of light transmitted to both sides by the interfering sub-pixels ESP is added to the amount of light transmitted to both sides by the red, green, and blue sub-pixels RSP, GSP, and BSP so that the luminance component from the side interferes. To be. As a result, as shown in Fig. 8A, an image which cannot be seen from the side is displayed on the liquid crystal panel 30A. In addition, different voltage levels are provided at positions of the interfering sub-pixels ESP11 to ESPmn corresponding to the interference pattern of the interfering sub-pixel driving signals, thereby causing a difference in the amount of interference of luminance for each of the color pixels PXC. Accordingly, the image displayed on the liquid crystal panel 30A cannot be identified at all on both sides. As a result, secrecy and security in the narrow viewing angle mode are further enhanced.

On the contrary, when the light / narrow mode control signal W / N has an initialization logic for specifying a wide viewing angle, the interfering light is transmitted to the interfering sub-pixels ESP from both sides thereof including the front of the liquid crystal panel 30. The offset sub-pixel driving signal is applied. There is no light passing through the interfering sub-pixel ESP by the offset-sub-pixel driving signal, and only the front and the front of the liquid crystal panel 30A by the red, green, and blue sub-pixels RSP, GSP, and BSP. There is only light that is transmitted to both sides. As a result, the image displayed on the liquid crystal panel 30A is clearly seen not only from the front but also from the side as in FIG. 8B.

Finally, the timing control unit 48A inputs synchronization signals (i.e., horizontal and vertical synchronization signals and a data clock) from an external video source. The tie control unit 48A generates the gate timing signal GTS to be supplied to the gate driver 44A and the data timing signal DTS to be supplied to the data driver 46A using the synchronization signals. In addition, the timing control unit 48A generates an interference control signal ECS necessary for the data generation operation of the interference data generation unit 40 and a combination control signal CCS necessary for the data combination operation of the video data combination unit 42A. do.

As described above, the liquid crystal panel according to the present invention can control the viewing angle by including an interference sub-pixel in addition to the color sub-pixels. In addition, the liquid crystal panel according to the present invention allows the interfering sub-pixels to be provided on the same plane together with the color sub-pixels so that the thickness and the weight do not increase. In addition, the liquid crystal panel allows the interfering sub-pixels to be provided on the same plane together with the color sub-pixels, so that not only the viewing angle can be controlled by a single liquid crystal layer but also the light amount can be prevented and the luminance can be prevented.

In addition, the viewing angle controllable liquid crystal display device according to the present invention causes the interfering subpixels on the liquid crystal panel to be driven by the interfering subpixel data forming an image of the interference pattern. This causes the image to be seen to the side of the liquid crystal panel to be changed. As a result, the viewing angle controllable liquid crystal display device according to the present invention enables enhanced confidentiality and security.

As described above, the present invention has been described to be limited to the embodiments shown in the drawings, which are merely exemplary, and a person of ordinary skill in the art without departing from the spirit and scope of the present invention. It will be apparent that various modifications, changes, and equivalent other embodiments are possible.

Claims (17)

A plurality of color pixels each having red, green, and blue sub-pixels; And Located on the same surface as the color pixels, and included in each of the color pixels, the control panel includes a plurality of interference sub-pixels for controlling the light transmitted from the side direction except the front . The method of claim 1, And the sub-pixels included in each of the color pixels are arranged to be connected to a pair of gate lines and a pair of data lines. The method of claim 1, And the sub-pixels included in each of the color pixels are commonly connected to one gate line and arranged to be connected to four data lines, respectively. 4. The method according to any one of claims 1 to 3, The red, green, and blue sub pixels are driven by a horizontal electric field, And the interference sub-pixel is driven by a vertical electric field. 4. The method according to any one of claims 1 to 3, The red, green, and blue sub-pixels include at least one or more band-shaped common electrodes alternately arranged with at least one or more band-shaped pixel electrodes, And a plate-shaped pixel electrode and a plate-shaped common electrode in which the interfering sub-pixels face each other. A liquid crystal panel according to claim 1; A data driver for supplying a pixel driving signal input by the subpixels on the liquid crystal panel by one line; An interference data generator for generating interference data supplied to the interference sub-pixels; And And a data combination unit for adding the interference data to video data supplied toward the data driver. The method of claim 6, wherein the interference data generating unit A memory in which interfering sub-pixel data for implementing an image including an interference pattern is stored; And And a memory controller for controlling a read operation of the memory. The method of claim 7, wherein the interference data generating unit, An op-cept sub-pixel data generator having a logic value corresponding to the offset voltage; And A selector for selectively transmitting offset subpixel data from the offset subpixel data generator and interference subpixel data from the memory to the data combination section in response to an optical / narrow mode control signal; A liquid crystal display capable of controlling the viewing angle, characterized in that. 9. The method of claim 8, And the offset sub-pixel data generator includes any one of a register and a switch element. The method of claim 7, wherein The memory further stores offset sub-pixel data of a logic value corresponding to an offset voltage, And the memory controller controls the memory such that the interfering subpixel data and the offset subpixel data stored in the memory are selectively read and supplied to the data combination unit in response to the wide / narrow mode control signal. Controllable liquid crystal display. The method of claim 6, wherein the interference data generating unit A data collecting unit for collecting red, green, and blue sub-pixel data included in the video data; And an operation unit configured to calculate interfering sub pixel data based on the collected sub pixel data from the data collecting unit and to supply the calculated interfering sub pixel data to the data combining unit. . The method of claim 11, And the calculating part calculates the interference sub-pixel data so that the luminance value is distributed in the reference gradation level. The method of claim 12, wherein the operation unit, The sum of the red, green, blue, and interfering sub-pixel data of any one gradation level lower than the maximum gradation level is set as reference luminance data, and the collected red, green, and blue subs from the collecting unit from this reference luminance data. And subtracting the sum of pixel data to calculate the interfering sub-pixel data. The method of claim 13, wherein the operation unit And a processor configured to calculate the interfering sub-pixel data from the collected red, green, and blue sub-pixel data from the collecting unit. The method of claim 13, wherein the operation unit And a look-up table for supplying the interfering sub-pixel data to the data combining unit by using the collected red, green, and blue sub-pixel data from the collecting unit. Device. The method according to any one of claims 11 to 15, wherein the interference data generating unit An op-cept sub-pixel data generator having a logic value corresponding to the offset voltage; And And a selector for selectively transmitting offset subpixel data from the offset subpixel data generator and interfering subpixel data from the calculator to the data combination section in response to an optical / narrow mode control signal. A liquid crystal display capable of controlling the viewing angle, characterized in that. 17. The method of claim 16, And the offset sub-pixel data generator includes any one of a register and a switch element.

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