KR101201888B1 - Program method of semiconductor device - Google Patents

Abstract

The present invention provides a method of programming a selected memory cell by applying a program pulse to a selected word line; Applying a verification voltage having a preliminary level lower than a target level to the selected word line to perform a first verify operation of the selected memory cells; Determining whether the first verification operation passes or not; Applying the target level to the selected word line to perform a second verify operation of the selected memory cells; Repeating a program operation including the first and second verify operations while raising the program pulse until the first verify operation passes; And repeating the third verifying operation and the program operation of setting the target level as the verifying voltage until the threshold voltages of all the selected memory cells reach the target level when the first verifying operation passes. It is made by the program method of the device.

Description

Program method of semiconductor device

The present invention relates to a method of programming a semiconductor device, and more particularly, to a method of programming a semiconductor device for shortening the operating time of a program.

Although there are many methods for programming a semiconductor device, an ISPP (incremental step pulse program) type program operation is mainly used to prevent the threshold voltage from being widened. The ISPP program operation is performed by first programming using a low level program pulse and then gradually raising the level of the program pulse. Specifically, after the threshold voltage of the selected memory cells is raised by applying a program pulse to the selected word line, a verification operation is performed to determine whether the threshold voltage of the selected memory cells has reached a target level. As a result of the determination, if the threshold voltage does not reach the target level, the step of performing the verification operation while gradually increasing the program pulse until the threshold voltage reaches the target level is repeated.

Recently, in order to further narrow the distribution of the threshold voltage, a program method of improving the ISPP method has been studied. Among them, a program operation of the ISPP method applying a double verify operation has been mainly studied.

The double verify operation is performed on the principle of narrowing the distribution range of the threshold voltage by lowering the threshold voltage rise rate of cells near the target level. That is, the double verify operation not only prevents the threshold voltages of cells close to the target level from increasing rapidly, but also widens the threshold voltages, and further narrows the threshold voltages by gradually increasing the threshold voltages. To this end, the verification operation is performed using a target level and a preliminary level lower than the target level. In detail, the double verifying operation is performed. After the program pulse is applied, the verifying operation using the preliminary level is first performed, the result is stored in the first latch, and the verifying operation using the target level is performed, and the result is displayed as the second. Store in a latch. Subsequently, a check operation is performed to determine whether the corresponding cell is lower than the preliminary level, between the preliminary level and the target level, or reaches the target level according to the data stored in the first and second latches, respectively. . The program and verification operations are repeated until all threshold voltages of the cells reach the target level while setting the potentials of the bit lines corresponding to the cells according to the check result.

However, the program method is such that the verification operation using the preliminary level is performed even after the threshold voltages reach the preliminary level until all of the threshold voltages of the memory cells to be programmed reach the target level. That is, the verification operation using the preliminary level performed after the threshold voltages of the memory cells to be programmed have reached the preliminary level is meaningless, and thus an unnecessary operation time is required.

The problem to be solved by the present invention is the verification operation time by omitting the verification operation using the preliminary level after the threshold voltage of the selected memory cells reaches the preliminary level during the verify operation using the target level and the preliminary level lower than the target level. We want to shorten.

A program method of a semiconductor device according to an embodiment of the present disclosure may include: programming selected memory cells by applying a program pulse to a selected word line; Applying a verification voltage having a preliminary level lower than a target level to the selected word line to perform a first verify operation of the selected memory cells; Determining whether the first verification operation passes or not; Applying the target level to the selected word line to perform a second verify operation of the selected memory cells; Repeating a program operation including the first and second verify operations while raising the program pulse until the first verify operation passes; And when the first verify operation passes, repeating the third verify operation and the program operation to set the target level as the verify voltage until the threshold voltages of all the selected memory cells reach the target level.

As a result of the first verification operation, the evaluation operation for the second verification operation is omitted after performing the second verification operation until the threshold voltages of all the selected memory cells reach the preliminary level.

Precharging bit lines respectively associated with the selected memory cells prior to performing the first verify operation.

After performing the first verify operation, if the potentials of the bit lines maintain the precharge level, the first verify operation is determined as a pass.

The first verification operation is performed by applying the verification voltage of the preliminary level to the selected word line and applying the verification voltage to the remaining word lines.

The second verification operation is performed by continuously applying a verification voltage of the target level to the selected word line to which the verification voltage of the preliminary level is applied.

The pass voltage is continuously applied to the remaining word lines while the second verify operation is performed.

After performing the second verify operation, all word lines including the selected word line are discharged.

When the program pulse is applied to the selected word line, a pass voltage is applied to the remaining word lines.

In another embodiment, a method of programming a semiconductor device may include: applying a program pulse to a selected word line; Performing a first verification operation by applying a verification voltage having a preliminary level lower than a target level to the selected word line, and sequentially performing a second verification operation by applying the verification voltage of the target level; And when the threshold voltages of the selected memory cells connected to the selected word line have reached the preliminary level as a result of the first verification operation, the threshold voltages of the selected memory cells have reached the target level. The verification operation using the preliminary level is omitted, and the verification operation using the target level as the verification voltage and the program operation of gradually raising the program pulse are repeated.

The program operation is performed by an incremental step pulse program (ISPP) method.

As a result of the first verify operation, the evaluation operation for the second verify operation is omitted until all threshold voltages of the selected memory cells connected to the selected word line reach the preliminary level.

After the threshold voltages of the selected memory cells connected to the selected word line have reached the preliminary level as a result of the first verify operation, the evaluation operation for the second verify operation is performed.

The second verification operation is performed by continuously applying a verification voltage of the target level to the selected word line to which the verification voltage of the preliminary level is applied.

In another embodiment, a method of programming a semiconductor device may include: programming selected memory cells by applying a program pulse to a selected word line; And performing a double verify operation to verify the memory cells by sequentially applying a preliminary level and a verify voltage having a target level higher than the preliminary level to the selected word line, wherein threshold voltages of all the selected memory cells are applied to the preliminary level. After reaching, the method may further include performing a program operation of performing only a verification operation using the verification voltage of the target level.

The double verify operation may include: performing a verify operation of setting the preliminary level as a verify voltage until all of the threshold voltages of the selected memory cells reach the target level; Evaluating a verification operation for setting the preliminary level as a verification voltage; And performing a verification operation of setting the target level as a verification voltage.

Until all threshold voltages of the selected memory cells reach the target level, the evaluation operation for the verification operation using the target level as the verification voltage is omitted.

The program operation is performed by an incremental step pulse program (ISPP) method.

The present invention can shorten the verification operation time by omitting the verification operation using the preliminary level after the threshold voltages of the selected memory cells have reached the preliminary level during the verify operation using the target level and the preliminary level lower than the target level. have. Therefore, an operation time for programming the selected memory cells to various levels can be shortened.

1 is a block diagram illustrating a semiconductor device according to the present invention.
FIG. 2 is a circuit diagram for describing the page buffer of FIG. 1 in detail.
3 is a flowchart illustrating a program method according to an exemplary embodiment of the present invention.
4 is a graph illustrating threshold voltages of memory cells to be programmed in a program operation according to an exemplary embodiment of the present invention.
5 is a timing diagram illustrating a program method according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

1 is a block diagram illustrating a semiconductor device according to the present invention.

Referring to FIG. 1, a nonvolatile memory device may include a circuit group 130, 140, 150, 160, configured to perform a program operation or a read operation of a memory cell array 110, memory cells included in the memory cell array 110. 170 and 180 and a control circuit 120 configured to control the circuit groups 130, 140, 150, 160, 170, and 180 to set threshold voltage levels of the selected memory cells according to the input data.

In the case of a NAND flash memory device, a circuit group includes a voltage generation circuit 130, a row decoder 140, a page buffer group 150, a column select circuit 160, an input / output circuit 170, and a pass / fail determination circuit 180. ).

The memory cell array 110 includes a plurality of memory cell blocks, one of which is shown in FIG. 1. Each memory cell block includes a plurality of strings ST. Some of the strings ST are designated as normal strings, and some are designated as flag strings. Each string ST is configured identically to each other, and has a source select transistor SST connected to a common source line CSL, a plurality of memory cells F0 to Fn, and a drain select connected to a bit line BL1. It consists of a transistor DST. The cells included in the flag string are called flag cells, but the structure is the same as the memory cells. The gates of the source select transistors SST are connected to the source select line SSL and the gates of the memory cells F0 to Fn are connected to the word lines WL0 to WLn respectively. Is connected to a drain select line (DSL). The strings ST are connected to the bit lines BL1 to BLk corresponding to the strings ST, respectively, and are commonly connected to the common source line CSL.

The control circuit 120 internally outputs the program operation signal PGM, the read operation signal READ or the erase operation signal ERASE in response to the command signal CMD, and according to the type of operation, the page buffer group 150. Output page buffer signals PB SIGNALS for controlling the page buffers included in the " In addition, the control circuit 120 internally outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD. In addition, the control circuit 120 checks whether the threshold voltages of the selected memory cells have increased to the target voltage according to the check signal CS output from the pass / fail determination circuit 180 during the program verification operation, and according to the check result, Determine if the operation should be repeated or completed.

The voltage supply circuits 130 and 140 select drain voltages of the memory cell block for selecting the voltages required for the program operation, the erase operation, or the read operation of the memory cells according to the signals READ, PGM, ERASE, and RADD of the control circuit 120. The line DSL is provided to the word lines WL0 to WLn and the source select line SSL. This voltage supply circuit includes a voltage generation circuit 130 and a row decoder 140.

The voltage generation circuit 130 outputs operation voltages to global lines to program, read, or erase the memory cells in response to the operation signals PGM, READ, and ERASE, which are internal command signals of the control circuit 120, When programming memory cells, operating voltages (eg, Vpgm, Vpass, and Vread) for programming are output as global lines.

In response to the row address signals RADD of the control circuit 120, the row decoder 140 may generate operating voltages generated by the voltage generation circuit 130 and local lines DSL and WL [n: of the selected memory cell block. 0], SSL).

The page buffer group 150 includes page buffers (not shown) connected to the bit lines BL1 to BLk, respectively. In response to the page buffer signals PB SIGNALS output from the control circuit 120, voltages necessary for storing data in the memory cells F0 to Fn are applied to the bit lines BL1 to BLk, respectively. In detail, the page buffer group 150 may precharge the bit lines BL1 to BLk or the voltages of the bit lines BL1 to BLk during the program operation, the erase operation, or the read operation of the memory cells F0 to Fn. In response to the change, data corresponding to the threshold voltage levels of the detected memory cells F0 to Fn is latched. That is, the page buffer group 150 applies a program allowance voltage (eg, 0V) or a program prohibition voltage (eg, Vcc) to bit lines according to data input to a latch during a program operation, and a memory during a read operation. The data stored in the memory cells F0 through Fn is detected by adjusting the voltages of the bit lines BL1 through BLk according to the data stored in the cells F0 through Fn.

The column select circuit 160 selects the page buffers included in the page buffer group 150 in response to the column address signal CADD output from the control circuit 120. The latched data of the page buffer selected by the column select circuit 160 is output. In addition, the data output from the page buffer group 150 may be received through the column line CL, and may be transferred to the pass / fail determination circuit 180.

The input / output circuit 170 inputs data DATA input from the outside to the page buffers of the page buffer group 150 during the program operation, and outputs the data DATA under the control of the control circuit 120. Forward to 160. When the column selection circuit 160 transfers the transferred data to the page buffers of the page buffer group 150 in order, the page buffers store the input data in an internal latch. In addition, during the read operation, the input / output circuit 170 outputs data DATA transferred through the column select circuit 160 from the page buffers of the page buffer group 150 to the outside.

The pass / fail determination circuit 180 checks whether error cells having a threshold voltage lower than a target voltage among programmed memory cells are generated in the program verifying operation performed after the program operation, and outputs the result as a check signal PFC. In addition, the pass / fail determination circuit 180 also counts the number of error cells generated when an error cell occurs and outputs a counting result as a counting signal CS.

The control circuit 120 adjusts the level of the program voltage applied to the selected word line during the program operation of the memory cells, and allows the voltage generation circuit 130 to selectively apply the verify voltages applied to the selected word line during the program verify operation. ). In this case, the control circuit 120 may control the voltage generation circuit 130 according to the check signal CS of the pass / fail determination circuit 180.

FIG. 2 is a circuit diagram for describing the page buffer of FIG. 1 in detail.

Referring to FIG. 2, the page buffer PB0 senses a bit line selection circuit 210 for selecting one of the bit lines BL0 and BL1 and a potential of the selected bit line during a read operation. A sensing circuit 220 for transferring to SO, a precharge circuit 230 for precharging the sensing node SO, a first latch 240 and a second latch 250 for storing data; The first node 260 transmits the data QA stored in the first latch 240 to the sensing node SO, and the data node QB stored in the second latch 250. A second transfer circuit 270 for transferring to the first latch, a first set / reset circuit 280 for setting up or resetting the first latch 150, and setting up or resetting the second latch. The second set / reset circuit 290 for discharging, the discharge circuit 300 for discharging the common node CON, and the data QA stored in the first latch 240 through the column line CL. column A first data transfer circuit 310 for transferring to the tag circuit 160 and a data QB stored in the second latch 250 for transferring to the column selection circuit 160 through the column line CL. 2 includes a data transmission circuit 320.

The bit line selection circuit 210 may include a bit line discharge circuit 212 and an even bit line BLe or an odd bit line for discharging the even bit line BLe or the odd bit line BLO during a program operation. A selection circuit 214 for selecting (BLo).

The bit line discharge circuit 212 may include a first switch N01 for discharging the even bit line BLe in response to the even discharge signal PDE, and an odd bit in response to the odd precharge signal PDO. And a second switch N02 for precharging the line BLo. The first switch N01 is implemented as an NMOS transistor connected between the even bit line BLo and the first terminal to which the variable voltage VIRPWR is applied. The second switch N02 is formed of the odd bit line BLo and the first switch N02. It is implemented with an NMOS transistor connected between one terminal.

The selection circuit 214 selects the third switch N03 for selecting the even bit line BLe in response to the even selection signal BSLE, and selects the odd bit line BLO in response to the odd selection signal BSLO. And a fourth switch N04. The third switch N03 and the fourth switch N04 are implemented with NMOS transistors.

The sensing circuit 220 includes a fifth switch N05 connecting the selected bit line and the sensing node SO in response to the sensing signal PBSENSE, and the fifth switch N05 is implemented as an NMOS transistor.

The precharge circuit 230 includes a sixth switch N06 for precharging the sensing node SO by connecting the power supply voltage VDD terminal and the sensing node SO in response to the precharge signal PRECHb. The sixth switch N06 is implemented with a PMOS transistor.

The first latch 240 is composed of first and second interleavers I1 and I2. The output terminal of the first inverter I1 and the input terminal of the second inverter I2 are connected to each other, and the output terminal of the second inverter I2 and the input terminal of the first inverter I1 are connected to each other. The first data QA stored in the first latch 240 is stored in the output terminal of the first interleaver I1.

The second latch 250 is composed of third and fourth interverters I3 and I4. The output terminal of the third inverter I3 and the input terminal of the fourth inverter I4 are connected to each other, and the output terminal of the fourth inverter I4 and the input terminal of the third inverter I3 are connected to each other. The second data QB stored in the second latch 250 is stored in the output terminal of the third interleaver I3. Although the page buffer PB shown in FIG. 2 includes two latches 240 and 250, two or more latches may be included depending on the device.

The first transfer circuit 260 may include a seventh switch N07 connecting the input terminal of the first inverter I1 and the sensing node SO in response to the first transfer signal TRAN_A, and the second transfer signal TRAN_B. In response, an eighth switch N08 connecting the output terminal of the first inverter I1 and the sensing node SO. The seventh and eighth switches N07 and N08 are implemented with NMOS transistors.

The second transfer circuit 270 may include a ninth switch N09 connecting the input terminal of the third inverter I3 and the sensing node SO in response to the third transfer signal TRAN_C, and the fourth transfer signal TRAN_D. In response, a tenth switch N10 connecting the output terminal of the third inverter I1 and the sensing node SO. The ninth and tenth switches N09 and N10 are implemented with NMOS transistors.

The first set / reset circuit 280 resets the first latch 240 by connecting the output terminal of the second inverter I2 and the common node CON in response to the first reset signal RESET_A. A twelfth switch that sets up the first latch 240 by connecting the 11 switch N11 and the input terminal of the second inverter I2 and the common node CON in response to the first set signal SET_A. N12). The eleventh and twelfth switches N11 and N12 are implemented with NMOS transistors.

The second set / reset circuit 290 resets the second latch 250 by connecting the output terminal of the fourth inverter I4 and the common node CON in response to the second reset signal RESET_B. The 14th switch for setting up the second latch 250 by connecting the 13 switch N13 and the input terminal of the fourth inverter I4 and the common node CON in response to the second set signal SET_B. N14). The thirteenth and fourteenth switches N13 and N14 are implemented with NMOS transistors.

The discharge circuit 300 includes a fifteenth switch N15 that discharges the common node CON by connecting the common node CON and the ground terminal Vss in response to the sensing node SO. N15 is implemented with an NMOS transistor.

The first data transfer circuit 310 is implemented as an NMOS transistor for transferring the first data QA to the column line CL in response to the first check signal CHKa.

The second data transmission circuit 320 is implemented as an NMOS transistor for transferring the second data QB to the column line CL in response to the second check signal CHKb.

FIG. 3 is a flowchart illustrating a program method according to an exemplary embodiment of the present invention, and FIG. 4 is a graph illustrating threshold voltages of memory cells to be programmed during a program operation according to the present invention.

3 and 4, the program method will be described in detail.

(S01) Program pulse application step.

When a program operation is started, a program allowance voltage (ground voltage) is applied to bit lines associated with selected memory cells, and a program prohibition voltage (power supply voltage) is applied to bit lines associated with remaining non-selected memory cells. A program pulse is applied to a word line (selected word line) connected to selected memory cells. When a program pulse is applied, the selected memory cells increase their threshold voltage due to the difference between the program pulse and the program allowable voltage.

(S02) First verification step.

A first verify operation is performed to verify whether the threshold voltages of the selected memory cells have reached the verification voltage at the preliminary level (Vp in FIG. 4) lower than the target level (Vt in FIG. 4). Data for the result of the first verification operation is stored as the first data QA in the first latch 240 of the page buffer PB of FIG. 2.

(S03) First verification pass determining step.

It is determined whether the first verification passes according to the first data QA stored in the first latch 240. That is, it is determined whether all threshold voltages of the selected memory cells have reached the verification voltage of the preliminary level Vp. If the threshold voltages of the selected memory cells have all reached the verification voltage of the preliminary level Vp (B), it is determined that the first verification has passed, and at least the cells whose threshold voltage has not reached the verification voltage of the preliminary level Vp are at least. If any one is detected (A), it is determined that the first verification has not passed.

(S04) Second verification step.

In step S03, if it is determined that the first verification has not passed (A), the second verification operation is performed according to a predetermined algorithm. The second verify operation verifies whether the threshold voltages of the selected memory cells have reached a target level, and data for the result of the second verify operation is stored in the second latch 250 of FIG. 2 is stored as data QB. In operation S04, an operation of determining a result of the second verify operation after performing the second verify operation is omitted. Since there are cells that have not reached the verification voltage of the preliminary level lower than the target level, the operation time can be shortened by omitting the operation of determining the result of the second verification operation.

(S05) Bit line potential setup step.

The potential of the bit lines is set up according to the first data QA input to the first latch 240 as a result of the first verification. Specifically, when the first data QA is changed (B), since the threshold voltage of the corresponding memory cells has reached the verification voltage of the preliminary level Vp, a program inhibit voltage is applied to the bit lines associated with the memory cells. A program permission voltage is applied to bit lines associated with memory cells in which the first data QA maintains a previous state (A). The program allowable voltage is the ground voltage, and the program prohibition voltage is the power supply voltage.

(S06) Program pulse rising step.

Raise the level of the program pulse by the step pulse.

Subsequently, the step S01 of applying the elevated program pulse to the selected word line is performed again. In this manner, steps S01 to S06 are repeated until all threshold voltages of the selected memory cells reach the verification voltage of the preliminary level Vp. After repeating steps S01 to S06, in step S03, if the first verification passes (B), step S07 is performed.

(S07) third verification step.

A second verify operation is performed to verify whether the threshold voltages of the selected memory cells have reached the target level Vt. Data for the result of the third verification operation is stored as the second data QB in the second latch 250 of FIG. 2 (the PB of FIG. 2).

(S08) Third verification pass determination step.

It is determined whether the second verification passes according to the second data QB stored in the second latch 250. That is, it is determined whether all threshold voltages of the selected memory cells have reached the target level Vt. If the threshold voltages of the selected memory cells all reach the target level Vt (C), it is determined that the second verification has passed and the program operation is terminated. However, if at least one cell whose threshold voltage does not reach the target level Vt is detected (B), it is determined that the third verification has not passed.

(S09) Bit line potential setup step.

The potential of the bit lines is set up according to the second data QB input to the second latch 250 as a result of the third verification. Specifically, since the memory cells having the second data QB changed (C) are cells in which the threshold voltage reaches the target level, the program inhibit voltage is applied to the bit lines associated with the memory cells, and the second data QB. The program permission voltage is applied to the bit lines associated with the memory cells B which maintain their previous states. The program allowable voltage is the ground voltage, and the program prohibition voltage is the power supply voltage.

(S10) program pulse rising step.

Raise the level of the program pulse by the step pulse.

Subsequently, the step S11 of applying the elevated program pulse to the selected word line is performed. In step S11, after performing the program operation using the elevated program pulse, the first verification operation is omitted and the second verification operation S07 is performed. This is because, since the threshold voltages of the memory cells already selected in the step S03 have reached the verification voltage of the preliminary level Vp, it is not meaningful to perform the first verification operation again. Accordingly, after passing the first verify operation, the program operation time is shortened by omitting the first verify operation and repeating steps S07 to S11 using only the third verify operation. As described above, if the third verification passes in step S07 to step S08, the program operation ends.

Next, a method of performing the above-described program operation using the semiconductor device will be described.

5 is a timing diagram illustrating a program method according to an exemplary embodiment of the present invention.

A program method will be described with reference to FIGS. 5 and 2 as follows.

In the T1 period, a program pulse is applied to the selected word line connected to the selected memory cell to increase the threshold voltages of the selected memory cells. In this case, a program pass voltage is applied to the remaining unselected word lines. When the program pulse is applied to the selected word line, the potentials of the bit lines BLe are determined according to the first data QA, and the first data QA associated with the selected cells to perform the program operation is '0'. Data is input, and the first data QA associated with unselected cells has '1' data. In FIG. 5, since the program operation of the selected cells is described, the first data QA is illustrated as '0'. Therefore, when the second transfer signal TRAN_B and the even selection signal BSLE are applied at a high level when the program pulse is applied, both the eighth switch N08 and the third switch N03 are turned on to select the even bit line. A program allowable voltage (ground voltage) is applied to BLe.

In the T2 section, the precharge operation of the bit line for performing the verification operation of the program operation performed in the T1 section is performed. To this end, the sensing node SO is precharged by applying the high level sensing signal PBSENSE and the precharged sensing node SO and the selected bit lines Sel by applying the even selection signal BSLE of the high level. Connect BL). Accordingly, the selected bit lines Sel. BL are precharged.

In the T3 period, the selected memory cells are verified. In detail, a double verify operation is performed to narrow the threshold voltage distribution of the memory cells. The double verification operation is a verification operation using two or more verification voltages for one program state. In the present embodiment, a verification operation using two verification voltages will be described. In the double verify operation, a target voltage Vt and a preliminary level Vp lower than the target level Vt to finally program the selected memory cell are used. The verification operation is performed in the order of performing the verification operation using the verification voltage of the preliminary level Vp first and then performing the verification operation using the verification voltage of the target level Vt.

First, in order to perform a verification operation using the verification voltage of the preliminary level Vp, a verification voltage of the preliminary level Vp is applied to the selected word line Sel. In this case, a pass voltage is applied to the remaining unselected word lines Unsel. Although not shown in FIG. 5, when a verification voltage of the preliminary level Vp or the target level Vt is applied to the selected word line Sel. WL, a turn-on voltage is applied to the source select line (SSL in FIG. 2). . Then, when the threshold voltage of the selected memory cell is lower than the preliminary level Vp, a channel is formed in the selected memory cell. Thus, the common source line CSL and the selected bit line Sel. BL of the ground level are connected to each other. The potential of (Sel. BL) is lowered. On the other hand, if the threshold voltage of the selected memory cell is higher than the preliminary level Vp, no channel is formed in the selected memory cell, and thus the common source line CSL and the selected bit line Sel. BL are blocked to select the selected bit line Sel. The precharge level of BL) is maintained. Accordingly, when the potential of the selected word line Sel. WL decreases as in the period T3 of FIG. 5, it means that the threshold voltage of the selected memory cell is lower than the preliminary level Vp. Accordingly, when the high level sensing signal PBSENSE and the first reset signal RESET_A are applied to each of the switches N05 and N11, the corresponding switches N05 and N11 are turned on and the selected bit line Sel. BL is turned on. The potential of is reflected in the first data QA of the first latch 240. That is, when the potential of the selected bit line Sel. BL is lowered to the low level as in the period T3, the potential of the sensing node SO is also lowered to the low level, so that the fifteenth switch N15 is turned off. Accordingly, since the common node CON and the ground terminal are not connected, the first data QA maintains previous data even when the eleventh switch N11 is turned on.

After the verification operation using the verification voltage of the preliminary level Vp is performed, the high level first check signal CHKa is applied to the sixteenth switch N16 to determine whether the selected memory cell is programmed. At this time, the sensing signal PBSENSE transitions to the low level. When the sixteenth switch N16 is turned on, the first data is transferred to the column line CL, and the column select circuit 160 of FIG. 1 passes the data received through the column line CL to pass / fail determination circuit 180. To pass). The pass / fail determination circuit 180 determines whether the verification operation using the verification voltage of the preliminary level Vp has passed according to the received data. In the T3 section, since the first data QA is kept low, the verification operation using the verification voltage of the preliminary level Vp is not passed.

Subsequently, a verification operation of applying a verification voltage having a target level Vt to the selected word line Sel. WL is performed. Specifically, the verification voltage of the target level Vt is continuously applied to the selected word line Sel. WL to which the verification voltage of the preliminary level Vp is applied. At this time, the thirteenth switch N13 is turned on by applying the high level to the second reset signal REST_B. However, since it is determined that the threshold voltages of the selected memory cells do not reach the preliminary level Vp, the target level Vt cannot be further reached. Therefore, since the potentials of the selected bit lines Sel. BL are lowered to the low level, and the potential of the sensing node SO is also lowered to the low level, the fifteenth switch N15 is turned off. The operation time of the verification section can be further shortened by omitting the evaluation operation of the verification operation using the verification voltage of the target level Vt until the verification operation using the verification voltage of the preliminary level Vp is passed. The reason for the verify operation using the verify voltage of the target level Vt is to set the data stored in the first and second latches 240 and 250 for the subsequent program operation. When the verification voltage of the target level Vt is applied, the signal transitions to the high level by the sensing signal PBSENSE.

In the T4 period, the word lines Sel. WL and Unsel. WL are discharged. At this time, the potentials of the bit lines may be set according to the verification operation result using the verification voltage of the preliminary level Vp.

In the T5 section, the program pulse is raised and the selected program cell is programmed by applying the elevated program pulse to the selected word line (Sel. WL). That is, the present invention performs an incremental step pulse program (ISPP) program operation which is advantageous for narrowing the threshold voltage distribution width, thereby gradually raising the program pulse. When the program pulse is applied to the selected word line Sel. WL, a pass voltage is applied to the remaining unselected word lines Unsel. WL.

In the T6 section, the bit line precharge operation for performing the verification operation of the program operation performed in the T5 section is performed. To this end, the sensing node SO is precharged by applying the high level sensing signal PBSENSE and the precharged sensing node SO and the selected bit lines Sel by applying the even selection signal BSLE of the high level. Connect BL). Accordingly, the selected bit lines Sel. BL are precharged.

In the T7 section, in order to perform a verification operation using the verification voltage of the preliminary level Vp, the verification voltage of the preliminary level Vp is applied to the selected word line Sel. In this case, a pass voltage is applied to the remaining unselected word lines Unsel. Although not shown in FIG. 5, when a verification voltage of the preliminary level Vp or the target level Vt is applied to the selected word line Sel. WL, a turn-on voltage is applied to the source select line (SSL in FIG. 2). . Then, when the threshold voltage of the selected memory cell is lower than the preliminary level Vp, a channel is formed in the selected memory cell. Thus, the common source line CSL and the selected bit line Sel. BL of the ground level are connected to each other. The potential of (Sel. BL) is lowered. On the other hand, if the threshold voltage of the selected memory cell is higher than the preliminary level Vp, no channel is formed in the selected memory cell, and thus the common source line CSL and the selected bit line Sel. BL are blocked to select the selected bit line Sel. The precharge level of BL) is maintained. Accordingly, when the potential of the selected word line Sel. WL decreases as in the period T7 of FIG. 5, it means that the threshold voltage of the selected memory cell is lower than the preliminary level Vp. Accordingly, when the high level sensing signal PBSENSE and the first reset signal RESET_A are applied to each of the switches N05 and N11, the corresponding switches N05 and N11 are turned on and the selected bit line Sel. BL is turned on. The potential of is reflected in the first data QA of the first latch 240. That is, when the potential of the selected bit line Sel. BL is lowered to the low level as in the period T7, the potential of the sensing node SO is also lowered to the low level, so that the fifteenth switch N15 is turned off. Accordingly, since the common node CON and the ground terminal are not connected, the first data QA maintains previous data even when the eleventh switch N11 is turned on.

After the verification operation using the verification voltage of the preliminary level Vp is performed, the high level first check signal CHKa is applied to the sixteenth switch N16 to determine whether the selected memory cell is programmed. At this time, the sensing signal PBSENSE transitions to the low level. When the sixteenth switch N16 is turned on, the first data is transferred to the column line CL, and the column select circuit 160 of FIG. 1 passes the data received through the column line CL to pass / fail determination circuit 180. To pass). The pass / fail determination circuit 180 determines whether the verification operation using the verification voltage of the preliminary level Vp has passed according to the received data. In the T7 section, since the first data QA is kept low, the verification operation using the verification voltage of the preliminary level Vp is not passed.

Subsequently, a verification operation of applying a verification voltage having a target level Vt to the selected word line Sel. WL is performed. Specifically, the verification voltage of the target level Vt is continuously applied to the selected word line Sel. WL to which the verification voltage of the preliminary level Vp is applied. At this time, the thirteenth switch N13 is turned on by applying the high level to the second reset signal REST_B. However, since it is determined that the threshold voltages of the selected memory cells do not reach the preliminary level Vp, the target level Vt cannot be further reached. Therefore, since the potentials of the selected bit lines Sel. BL are lowered to the low level, and the potential of the sensing node SO is also lowered to the low level, the fifteenth switch N15 is turned off. The operation time of the verification section can be further shortened by omitting the evaluation operation of the verification operation using the verification voltage of the target level Vt until the verification operation using the verification voltage of the preliminary level Vp is passed. The reason for the verify operation using the verify voltage of the target level Vt is to set the data stored in the first and second latches 240 and 250 for the subsequent program operation. When the verification voltage of the target level Vt is applied, the signal transitions to the high level by the sensing signal PBSENSE.

In the T8 period, the word lines Sel. WL and Unsel. WL are discharged. At this time, the potentials of the bit lines may be set according to the verification operation result using the verification voltage of the preliminary level Vp.

In the T9 section, the program pulse is raised and the selected program cell is programmed by applying the elevated program pulse to the selected word line (Sel. WL). In this case, a pass voltage is applied to the remaining unselected word lines Unsel.

In the T10 section, the precharge operation of the bit line for performing the verification operation of the program operation performed in the T9 section is performed. To this end, the sensing node SO is precharged by applying the high level sensing signal PBSENSE and the precharged sensing node SO and the selected bit lines Sel by applying the even selection signal BSLE of the high level. Connect BL). Accordingly, the selected bit lines Sel. BL are precharged.

In the T11 section, in order to perform the verification operation using the verification voltage of the preliminary level Vp, the verify voltage of the preliminary level Vp is applied to the selected word line Sel. In this case, a pass voltage is applied to the remaining unselected word lines Unsel. Although not shown in FIG. 5, when a verification voltage of the preliminary level Vp or the target level Vt is applied to the selected word line Sel. WL, a turn-on voltage is applied to the source select line (SSL in FIG. 2). . Then, when the threshold voltage of the selected memory cell is lower than the preliminary level Vp, a channel is formed in the selected memory cell. Thus, the common source line CSL and the selected bit line Sel. BL of the ground level are connected to each other. The potential of (Sel. BL) is lowered. On the other hand, if the threshold voltage of the selected memory cell is higher than the preliminary level Vp, no channel is formed in the selected memory cell, and thus the common source line CSL and the selected bit line Sel. BL are blocked to select the selected bit line Sel. The precharge level of BL) is maintained. As in the period T11 of FIG. 5, when the potential of the selected word line Sel. WL maintains the precharge level, it means that the threshold voltage of the selected memory cell reaches the preliminary level Vp. Accordingly, when the high level sensing signal PBSENSE and the first reset signal RESET_A are applied to each of the switches N05 and N11, the corresponding switches N05 and N11 are turned on and the selected bit line Sel. BL is turned on. The potential of is reflected in the first data QA of the first latch 240. That is, if the potential of the selected bit line Sel. BL maintains the precharge level as in the T11 period, the potential of the sensing node SO also maintains the high level, and thus the fifteenth switch N15 is turned on. Accordingly, since the common node CON and the ground terminal are connected, the first data QA is changed from '0' to '1'. That is, the potential of the output terminal of the first inverter I1 of the first latch 140 in FIG. 2 is changed from the low level to the high level. In FIG. 5, the first data is changed after applying the third program pulse (T9 section). However, this is illustrated to be changed after applying the third program pulse for convenience of description, and limited to the third program pulse. It doesn't happen.

After the verification operation using the verification voltage of the preliminary level Vp is performed, the high level first check signal CHKa is applied to the sixteenth switch N16 to determine whether the selected memory cell is programmed. At this time, the sensing signal PBSENSE transitions to the low level. When the sixteenth switch N16 is turned on, the second data is transferred to the column line CL, and the column selection circuit 160 of FIG. 1 passes the data received through the column line CL to pass / fail determination circuit 180. To pass). The pass / fail determination circuit 180 determines whether the verification operation using the verification voltage of the preliminary level Vp has passed according to the received data. In the T11 section, since the first data QA is changed from the low state to the high state, that is, it is changed from '0' to '1', the verification operation using the verification voltage of the preliminary level Vp passes. Subsequently, a verification operation of applying a verification voltage having a target level Vt to the selected word line Sel. WL is performed. Specifically, the verification voltage of the target level Vt is continuously applied to the selected word line Sel. WL to which the verification voltage of the preliminary level Vp is applied.

In the T12 period, the word lines Sel. WL and Unsel. WL are discharged. At this time, the potentials of the bit lines may be set according to the verification operation result using the verification voltage of the preliminary level Vp.

In the T13 period, the program pulse is raised and the selected program cell is programmed by applying the elevated program pulse to the selected word line (Sel. WL). In this case, a pass voltage is applied to the remaining unselected word lines Unsel.

In the T14 section, the bit line precharge operation for performing the verification operation of the program operation performed in the T13 section is performed. To this end, the sensing node SO is precharged by applying the high level sensing signal PBSENSE and the precharged sensing node SO and the selected bit lines Sel by applying the even selection signal BSLE of the high level. Connect BL). Accordingly, the selected bit lines Sel. BL are precharged.

In the T15 section, since the verification operation using the verification voltage of the preliminary level Vp has already passed, the verification operation using the verification voltage of the preliminary level Vp is omitted, and the verification operation using the verification voltage of the target level Vt is performed. Shorten operating time Specifically, a verification voltage of the target level Vt is applied to the selected word line Sel. WL. In this case, a pass voltage is applied to the remaining unselected word lines Unsel. Although not shown in FIG. 5, when the verification voltage of the target level Vt is applied to the selected word line Sel. WL, a turn-on voltage is applied to the source select line (SSL in FIG. 2). Then, when the threshold voltage of the selected memory cell is lower than the target level Vt, a channel is formed in the selected memory cell. Therefore, the common source line CSL and the selected bit line Sel. BL of the ground level are connected to the selected bit line. The potential of (Sel. BL) is lowered. On the other hand, if the threshold voltage of the selected memory cell is higher than the target level Vt, no channel is formed in the selected memory cell, and thus the common source line CSL and the selected bit line Sel. BL are blocked to select the selected bit line Sel. The precharge level of BL) is maintained. As shown in the period T15 of FIG. 5, when the potential of the selected word line Sel. WL drops to a low level, it means that the threshold voltage of the selected memory cell reaches the target level Vt. Accordingly, when the high level sensing signal PBSENSE and the second reset signal RESET_B are applied to the respective switches N05 and N13, the corresponding switches N05 and N13 are turned on to select the selected bit line Sel. BL. The potential of is reflected in the second data QB of the second latch 250. In the T15 period, the potential of the selected bit line Sel. BL is lowered to the low level, and the potential of the sensing node SO is also lowered to the low level, so the fifteenth switch N15 is turned off. Accordingly, since the common node CON and the ground terminal are blocked, the second data QB maintains the previous state. Next, the high level second check signal CHKb is applied to the seventeenth switch N17 to turn on the seventeenth switch N17. When the seventeenth switch N17 is turned on, the second data QB is transferred to the column line CL, and the column selection circuit 160 of FIG. 1 passes the received data to pass / fail determination circuit 180 of FIG. 1. To pass on. The pass / fail determination circuit 180 determines whether the verify operation using the verify voltage of the target level Vt has passed according to the received data.

In the same manner as described above, the operation of omitting the verification using the verification voltage of the preliminary level Vp is repeated and the program operation of gradually raising the program pulse while performing the verification using only the verification voltage of the target level Vt is repeated. When all threshold voltages of the selected memory cells reach the target level Vt, the corresponding program operation ends. As described above, after the verification operation using the verification voltage at the preliminary level Vp is passed, the verification operation using the verification voltage at the preliminary level Vp can be omitted, so that the time taken for the verification operation can be shortened. Program operating time can also be shortened.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

110: memory cell array 120: control circuit
130: voltage generation circuit 140: low decoder
150: page buffer group 160: column selection circuit
170: input / output circuit 180: pass / fail determination circuit

Claims (18)

Programming the selected memory cells by applying a program pulse to the selected word line;
Applying a verification voltage having a preliminary level lower than a target level to the selected word line to perform a first verify operation of the selected memory cells;
Determining whether the first verification operation passes or not;
Applying the target level to the selected word line to perform a second verify operation of the selected memory cells;
Repeating a program operation including the first and second verify operations while raising the program pulse until the first verify operation passes; And
If the first verify operation passes, repeating the third verify operation and the program operation to set the target level as the verify voltage until the threshold voltages of all the selected memory cells reach the target level. Program way. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
And evaluating the second verification operation after performing the second verification operation until the threshold voltages of all the selected memory cells reach the preliminary level as a result of the first verification operation. Claim 3 has been abandoned due to the setting registration fee. The method of claim 1,
And precharging bit lines respectively associated with the selected memory cells before performing the first verify operation. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3,
And after performing the first verify operation, determining that the first verify operation is a pass when all of the potentials of the bit lines maintain a precharge level. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1,
The first verification operation is performed by applying the verification voltage of the preliminary level to the selected word line and applying the verification voltage to the remaining word lines. Claim 6 has been abandoned due to the setting registration fee. The method of claim 5,
And the second verify operation is performed by continuously applying the verify voltage of the target level to the selected word line to which the verify voltage of the preliminary level is applied. Claim 7 has been abandoned due to the setting registration fee. The method according to claim 6,
And continuously applying a pass voltage to the remaining word lines while performing the second verify operation. Claim 8 was abandoned when the registration fee was paid. The method of claim 1,
And discharging all word lines including the selected word line after performing the second verify operation. Claim 9 has been abandoned due to the setting registration fee. The method of claim 1,
And applying a pass voltage to the remaining word lines when the program pulse is applied to the selected word line. Applying a program pulse to the selected word line;
Performing a first verification operation by applying a verification voltage having a preliminary level lower than a target level to the selected word line, and sequentially performing a second verification operation by applying the verification voltage of the target level; And
When the threshold voltages of the selected memory cells connected to the selected word line have reached the preliminary level as a result of the first verification operation, the preliminary until all of the threshold voltages of the selected memory cells reach the target level. And a verification operation using the target level as the verification voltage and a program operation of gradually raising the program pulse, by omitting the verification operation using the level. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10,
The programming operation of the semiconductor device is performed by an incremental step pulse program (ISPP) method. Claim 12 is abandoned in setting registration fee. The method of claim 10,
And evaluating the second verification operation until the threshold voltages of the selected memory cells connected to the selected word line reach the preliminary level as a result of the first verification operation. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12,
And after the threshold voltages of the selected memory cells connected to the selected word line have reached the preliminary level as a result of the first verifying operation, evaluating the second verifying operation. Claim 14 has been abandoned due to the setting registration fee. The method of claim 10,
And the second verify operation is performed by continuously applying the verify voltage of the target level to the selected word line to which the verify voltage of the preliminary level is applied. Programming the selected memory cells by applying a program pulse to the selected word line; And
A double verification operation is performed to sequentially verify the memory cells by sequentially applying a preliminary level and a verification voltage higher than the preliminary level to the selected word line, wherein the threshold voltages of all the selected memory cells reach the preliminary level. And a program operation of performing only a verification operation using the verification voltage of the target level. Claim 16 has been abandoned due to the setting registration fee. 16. The method of claim 15,
The double verify operation,
Performing a verification operation of setting the preliminary level as a verification voltage until all threshold voltages of the selected memory cells reach the target level;
Evaluating a verification operation for setting the preliminary level as a verification voltage; And
And performing a verification operation of setting the target level as a verification voltage. Claim 17 has been abandoned due to the setting registration fee. 17. The method of claim 16,
And evaluating an operation for verifying the target level as a verify voltage until all threshold voltages of the selected memory cells reach the target level. Claim 18 has been abandoned due to the setting registration fee. 16. The method of claim 15,
The programming operation of the semiconductor device is performed by an incremental step pulse program (ISPP) method.

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