KR101186514B1 - Liquid crystal display device and method for fabricating thereof - Google Patents

Abstract

The present invention relates to a method for manufacturing a liquid crystal display device and a liquid crystal display device formed thereby, and more particularly, to a manufacturing process for reducing the number of masks used.

The present invention uses only a first mask to form a gate line and a pixel electrode, a second mask to form a data line and an active pattern, and a third mask to form a drain electrode and a pixel electrode. By providing a method of forming a liquid crystal display device using only a mask, it can contribute to productivity improvement.

3 masks, amorphous silicon, liquid crystal display, connection pattern

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THEREOF}

1 is a plan view of a unit pixel of a general liquid crystal display device.

2 is a cross-sectional view of a general liquid crystal display device.

3A to 3E are water flow diagrams illustrating a manufacturing process of a conventional general liquid crystal display device.

4 is a plan view showing a unit pixel of a liquid crystal display of the present invention.

5 is a cross-sectional view of the liquid crystal display device of the present invention.

6A to 6G are flowcharts showing the manufacturing process of the liquid crystal display device of the present invention.

********** Description of the symbols for the main parts of the drawings ***********

401: gate line 402: data line

403: active pattern 402s: source electrode

402d: drain electrode 401g: gate electrode

405: storage electrode 406, 407: connection pattern

407a, 406a: Contact hole

The present invention relates to a liquid crystal display device manufactured using three masks and a method of manufacturing the same, and more particularly to a liquid crystal display device manufactured using three masks while using amorphous silicon as a channel layer.

In display devices, particularly flat panel displays such as liquid crystal display devices, active devices such as thin film transistors are provided in each pixel to drive the display devices. The driving method of the display device of this type is commonly referred to as an active matrix driving method. In such an active matrix system, the active elements are arranged in respective pixels arranged in a matrix form to drive the corresponding pixels.

1 is a view showing an active matrix type liquid crystal display element. The liquid crystal display device having the structure shown in the drawing is a thin film transistor liquid crystal display device using a thin film transistor 10 as an active device. As shown in the drawing, each pixel of a thin film transistor liquid crystal display device having N × M pixels arranged vertically and horizontally includes a gate line 101 to which a scan signal is applied from an external driving circuit and a data line to which an image signal is applied. And a thin film transistor 110 formed at an intersection area of the 102.

The thin film transistor 110 includes a gate electrode 106 connected to the gate line 101, a semiconductor layer 103 formed on the gate electrode 106, and activated when a scan signal is applied to the gate electrode 106. And a source electrode 104 and a drain electrode 105 formed on the semiconductor layer 103. As the semiconductor layer 103 is activated by being connected to the source electrode 104 and the drain electrode 105 in the display area of the pixel, an image signal is applied through the source electrode 104 and the drain electrode 105 to provide a liquid crystal. A pixel electrode 120 for operating (not shown) is formed.

FIG. 2 is a cross-sectional view taken along the line I-I of FIG. 1 and will be described in more detail with reference to the drawings.

Referring to FIG. 2, the thin film transistor 110 is formed on the first substrate 201 made of a transparent material such as glass to form the array substrate 210. The thin film transistor 110 may include a gate electrode 106 formed on the first substrate 201, a gate insulating layer 203 stacked over the entire first substrate 201 on which the gate electrode 106 is formed, and A semiconductor layer 103 formed on the insulating layer 203, a source electrode 104 and a drain electrode 105 formed on the semiconductor layer 103, and a protective layer stacked over the entire first substrate 201 ( passivation layer; The pixel electrode 120 connected to the drain electrode 105 of the thin film transistor 106 is formed on the passivation layer 204 through the contact hole 107 formed in the passivation layer 204.

Meanwhile, the color filter substrate 220 facing the array substrate 210 may be formed on the second substrate 202 made of a transparent material such as glass, and formed on the second substrate 202 and forming the thin film transistor 110. Or a black matrix 205 formed in an image non-display area such as between pixels and pixels to prevent light from being transmitted to the image non-display area, and a color filter layer 206 consisting of red, green, and blue to realize actual colors. It is configured to include). When the color filter substrate 220 and the array substrate 210 are bonded together, the liquid crystal layer 240 is filled therebetween to complete the liquid crystal display device. Meanwhile, a common electrode 207 may be further formed on the color filter layer 206 to provide an electric field to the liquid crystal layer 240 together with the pixel electrode 120.

The liquid crystal display device is mainly manufactured by a complex process such as a photolithography process using a mask, and a method of manufacturing the liquid crystal display device will be described with reference to FIG. 3.

Referring to FIG. 3A, a metal layer is laminated on the entire surface of the first substrate 201, then a photoresist is applied thereon, and a photolithography process is performed to connect to a gate line (not shown) and the gate line. The gate electrode 106 is formed.

3B, the gate insulating layer 203, the semiconductor layer 103a, and the ohmic contact layer 211 are sequentially formed over the entire first substrate 201 on which the gate electrode 106 is formed. Subsequently, the photoresist layer 230 is coated on the ohmic contact layer 211 and a photolithography process is performed to form an active pattern. In this case, the active pattern is formed by stacking a semiconductor layer and an ohmic contact layer.

Subsequently, as shown in FIG. 3C, after the conductive layer 212 is stacked over the entire first substrate 201, a photoresist pattern 231 defining a source and a drain electrode is formed, and the photoresist pattern 231 is formed. The source 104 and the drain electrode 105 are formed using the etching mask. Referring to FIG. 3D, when the conductive layer is patterned to form source and drain electrodes, the ohmic contact layer 211 and the conductive layer 212 formed in the center of the active layer 103 are etched to form a channel region in the active layer. Is defined. Through this process, a thin film transistor is completed.

Meanwhile, as illustrated in FIG. 3E, a passivation layer 204 is further formed on the first substrate 201 on which the source electrode 104 and the drain electrode 105 are formed to protect the thin film transistor. Thereafter, a photoresist is applied on the passivation layer 204 and a photolithography process is further performed to form a contact hole 107 exposing the drain electrode 105. Subsequently, a transparent material such as indium tin oxide (ITO) is deposited on the passivation layer 204 including the contact hole 107 and then etched by a photolithography process to etch the pixel electrode 120 on the passivation 204. To form. In this case, the pixel electrode 120 is electrically connected to the drain electrode 105 of the thin film transistor through the contact hole 107 formed in the passivation layer 120.

Although not shown in the drawing, after forming the black matrix and the color filter layer on the second substrate, the first substrate 201 and the second substrate are bonded together and the liquid crystal layer is filled therebetween to form a liquid crystal display device. Complete

However, in order to form the liquid crystal display device using the semiconductor layer as a channel layer, a plurality of mask processes must be performed. In the manufacturing process of the liquid crystal display device described above, five mask processes are performed to form a thin film transistor, and six mask processes are performed until the pixel electrode is formed. However, the mask used in the manufacture of the liquid crystal display device is expensive equipment, and as one mask process is added, a number of secondary processes are further progressed, causing a problem of increasing manufacturing cost. In addition, since the mask process includes an etching process for discharging environmentally harmful substances, there is a problem that the manufacturing process is not environmentally friendly.

Therefore, efforts are being actively made to reduce the number of masks used in the manufacturing process of liquid crystal display devices.

An object of the present invention is to reduce the number of masks used in manufacturing a liquid crystal display device. Moreover, it aims at improving productivity by manufacturing a liquid crystal display element using a small number of masks.

For the above purpose, the method of manufacturing a liquid crystal display device of the present invention comprises the steps of sequentially forming a transparent electrode layer and a first conductive layer on the first substrate; Patterning the transparent electrode layer and the first conductive layer to form a pixel electrode including a stacked gate line of the transparent electrode layer and the first conductive layer and the transparent electrode layer; Forming a first insulating layer on a first substrate on which the gate line and the pixel electrode are formed; Sequentially forming a semiconductor layer, an ohmic contact layer, and a second conductive layer on the first insulating layer; Patterning the semiconductor layer, the ohmic contact layer, and the second conductive layer to form a source electrode, a drain electrode, a storage electrode, and an active pattern; Forming a second insulating layer covering the source electrode, the drain electrode, the storage electrode, and the active pattern; Applying a first photosensitive film on the second insulating layer; Exposing and developing the first photoresist layer to form a first contact hole exposing the drain electrode and a pixel electrode adjacent thereto and a second contact hole exposing the storage electrode and a pixel electrode adjacent thereto; Forming a third conductive layer on the first substrate with the first photoresist pattern remaining; Applying a second photosensitive film on the third conductive layer; Acing the second photoresist film to form a second photoresist pattern so that the second photoresist film remains only in the first contact hole and the second contact hole; And removing the third conductive layer exposed by the second photosensitive film pattern to form a first connection pattern electrically connecting the drain electrode and the pixel electrode.

The liquid crystal display device of the present invention formed by the manufacturing method comprises: a gate line formed on a substrate, the gate line comprising a transparent electrode layer and a first conductive layer stacked thereon; A pixel electrode formed on the substrate and composed of the transparent electrode layer; A first insulating layer formed on the substrate on which the gate line and the pixel electrode are formed; A data line formed on the first insulating layer and vertically crossing the gate line; An active pattern formed on the first insulating layer and formed of a semiconductor; A source electrode formed on the active pattern and branching from the data line and a drain electrode corresponding to the source electrode; A storage electrode formed on the first insulating layer and overlapping the gate line and the pixel electrode; A second insulating layer formed on the source electrode, the drain electrode, and the storage electrode; And a first connection pattern electrically connecting the drain electrode and the pixel electrode and a second connection pattern electrically connecting the storage electrode and the pixel electrode.

An object of the present invention is to reduce the number of masks used in manufacturing a liquid crystal display device. In the present invention, by using only three masks, the number of masks is greatly reduced compared to the conventional one.

The present invention forms a gate line and a pixel electrode using a first mask which is a diffraction mask. In order to form the gate line and the pixel electrode using one mask, a transparent electrode layer and a first conductive layer are sequentially deposited on a substrate, and a photoresist pattern is formed using a first mask, which is a diffraction mask, and a gate is formed through the photoresist pattern. A line is first formed, and the photoresist pattern is aced to expose the pixel region, and the first conductive layer of the pixel region is aceed to form a pixel electrode.

In addition, an active pattern, a data line, a source, and a drain electrode of the thin film transistor, which is a switching element of the liquid crystal display, are formed using the second mask.

The process of using the second mask is as follows.

That is, a semiconductor layer, an ohmic contact layer, and a second conductive layer are sequentially deposited on the first insulating layer covering the gate line and the pixel electrode. Subsequently, a photosensitive film is coated on the second conductive layer and diffraction exposure is performed by applying a second mask which is a diffraction mask.

Subsequently, the second conductive layer, the ohmic contact layer, and the semiconductor layer are etched using the second photosensitive film pattern formed by the diffraction exposure to form an active pattern. In this case, a storage electrode partially overlapping the gate line is further formed in the unit pixel area.

Subsequently, the second photoresist pattern is ashed and the source and drain electrodes are formed by removing the second conductive layer and the ohmic contact layer in the channel region.

Therefore, the present invention is characterized in that the active pattern and the source and drain electrodes of the thin film transistor are formed by one mask in the second mask process.

In addition, the present invention forms a connection pattern for electrically connecting the drain electrode, the pixel electrode, and the pixel electrode and the storage electrode by using a third mask.

The process of using the third mask is to form a conductive material pattern in the contact hole, which is called a contact hole filling (CHF) process.

The process of using the third mask is a process including a contact hole filling process, and a process of forming a contact hole through a photolithography process on a second insulating layer covering the thin film transistor and a contact hole filling process.

The process of forming the connection pattern using the third mask includes forming a second insulating layer on the first substrate on which the source and drain electrodes are formed, forming a first photosensitive film on the second insulating layer, and performing a photolithography process. Forming a contact hole through the drain electrode, a portion of the pixel electrode adjacent to the pixel electrode, and a portion of the pixel electrode and a storage electrode overlapping the pixel electrode on the pixel electrode; Depositing a third conductive layer in the first photosensitive film pattern and the contact hole, applying a second photosensitive film on the third conductive layer, and a third conductive layer formed in the contact hole by acing the second photosensitive film. Exposing the third conductive layer in the remaining region except for the above, removing the third conductive layer, and removing the remaining second photoresist pattern and the first photoresist pattern. It will be achieved through the process.

Hereinafter, a planar structure and a cross-sectional structure of a liquid crystal display device formed using only three masks will be described with reference to FIGS. 4 and 5.

4 is a cross-sectional view illustrating a unit pixel of the present invention, and FIG. 5 is a cross-sectional view of the cutting line I-I of FIG. 4. Referring to FIG. 4, a unit pixel area is defined on a plurality of gate lines 401 and a plurality of data lines 402 perpendicular to the gate lines 401 on a transparent first substrate such as glass.

Referring to FIG. 5, the gate line 401 may include a transparent electrode layer 401a formed on a transparent first substrate 501 such as glass, and a first conductive layer 401b substantially forming the gate line 401. It is a double layer.

In the unit pixel area, a pixel electrode 410 including a transparent electrode layer formed on the first substrate 501 is formed. Therefore, the transparent electrode layer 401a and the pixel electrode constituting the gate line are directly formed on the first substrate 501.

Referring to FIG. 5, the data line 402 is a double layer of a semiconductor layer constituting the active pattern 403 and a second conductive layer constituting a substantial data line.

In the unit pixel area, a switching element for driving the unit pixel and a storage capacitor for holding an image signal provided to the unit pixel are further formed.

4 and 5, an active pattern 403 formed of the same semiconductor as the semiconductor layer constituting a part of the data line is formed on the first insulating layer 502 covering the gate line 401. Source and drain electrodes 402s and 402d are formed on the active pattern 403 via an ohmic contact layer (not shown) for ohmic contact.

The drain electrode 402d is configured such that the active pattern 403 and its ends coincide with each other. That is, the drain electrode 402d or the active pattern 403 is patterned so as to coincide with each other without protruding. Such a structure is advantageous in suppressing generation of wave noise generated by the active pattern protruding from the drain electrode.

According to the present invention, an additional storage electrode 405 is further formed to hold an image signal provided to the unit pixel, and the storage electrode 405 overlaps the gate line in front of the unit pixel and the pixel electrode in the unit pixel, respectively. have.

4 and 5, the storage electrode 405 overlaps the gate line 401c and the pixel electrode 410 in front of the unit pixel and the semiconductor layer on the first insulating layer 502 that insulates the gate line 401. It is formed through the.

In the present invention, since the pixel electrode 410 is directly formed on the first substrate, the pixel electrode 410 is insulated from the drain electrode 402d and the storage electrode 405. The storage electrode 405 and the drain electrode 402d and the pixel electrode ( The connection pattern is further formed to connect the 410 to each other.

The connection patterns 406 and 407 may include a first electrode exposing a portion of the drain electrode 402d and the pixel electrode 410 adjacent thereto and a portion of the storage electrode 406 and the pixel electrode 405 adjacent thereto. It is formed in the contact hole 407a and the second contact hole 406a to connect the drain electrode 402d and the storage electrode 406 with the pixel electrode 410, respectively.

Hereinafter, a manufacturing method of the liquid crystal display device of the present invention will be described with reference to FIGS. 6A to 6G.

Referring to FIG. 6A, a transparent electrode layer 401a such as ITO and a first conductive layer 401b are sequentially formed on the first substrate 501. The transparent electrode layer 401a and the first conductive layer 401b may be deposited by a sputtering method.

Subsequently, a photolithography process for forming a gate line and a pixel electrode is performed by applying the first mask 602.

A diffraction mask is used to form the gate line and the pixel electrode using one mask.

Let's look at the process in more detail.

First, a first photosensitive film is coated on the first conductive layer 401b and a photo process is performed by applying a first mask, which is a diffraction mask. As a result, the pixel region where the pixel electrode is formed is subjected to diffraction exposure to form a photoresist pattern thinner than the region where the gate line is to be formed.

6A illustrates a photo process using a positive photoresist in which photoresist of an exposed area remains.

As a result of applying the first mask 602, a first photosensitive film pattern 601 defining a gate line and a pixel electrode is formed on the first conductive layer 401b. In the first mask pattern 601, portions defining pixel electrodes are diffracted and exposed.

Subsequently, the first photoresist pattern 601 is applied as an etching mask, and the first conductive layer 401b and the transparent electrode layer 401a are etched to form a gate line. In this case, since the pixel region is a double layer of the transparent electrode layer 401a and the first conductive layer 401b, the process of removing the first conductive layer 401b of the pixel region should be further performed.

Therefore, in order to remove the first conductive layer 401b, the first photoresist layer pattern 601 is aced to remove the photoresist pattern on the pixel region.

The ashing is useful for removing a part of the photosensitive film pattern subjected to diffraction exposure by removing oxygen gas by blowing and oxidizing the photosensitive film pattern.

As a result, the photoresist pattern on the pixel region is removed and the first conductive layer is exposed. Subsequently, the first conductive layer is etched to expose the transparent electrode layer of the pixel region, thereby completing the pixel electrode 410.

After the pixel electrode 410 is formed, the result of removing the photoresist pattern is shown in FIG. 6B.

Referring to FIG. 6B, in the first mask process, the gate electrode, which is a double layer of the transparent electrode layer and the first conductive layer, and the pixel electrode including only the transparent electrode layer may be simultaneously formed.

Subsequently, a first insulating layer 502 is deposited on the gate line 401 and the pixel electrode 410.

6C, a semiconductor layer 403a, an ohmic contact layer 411, and a second conductive layer 402a are sequentially deposited on the first insulating layer 502. The semiconductor layer 403a and the ohmic contact layer 411 may be a semiconducting material such as amorphous silicon or polysilicon. In particular, the ohmic contact layer 411 may be formed by doping the semiconductor layer 403a with a high concentration of impurity ions, such as Group 3 or Group 5.

The semiconductor layer and the ohmic contact layer may be formed by a chemical vapor deposition method, and the second conductive layer may be formed by a sputtering method.

Subsequently, a photosensitive film is coated on the second conductive layer 402a and a second mask is applied to form a first photosensitive film pattern 603. The first photoresist layer pattern 603 is formed by an exposure and development process, and includes a diffraction exposure area 604 in which a channel region of the thin film transistor is defined by diffraction exposure. The diffractive exposure area 604 defines a channel area.

In addition, the first photoresist layer pattern 603 includes a photoresist layer pattern defining a storage electrode near a front gate line of a unit pixel.

Applying the first photoresist pattern 603 as a mask, the second conductive layer 402a, the ohmic contact layer 411, and the semiconductor layer 403a are sequentially applied to the active pattern 403 and the storage electrode 405. Form.

Subsequently, the first photoresist layer pattern 603 is aced to remove the photoresist layer of the diffractive exposure region 604 coated with a relatively thin thickness to expose the second conductive layer of the channel region. At this time, the second photoresist pattern (not shown) formed by ace the first photoresist pattern 603 is formed on both sides of the channel region. The second photoresist pattern defines a source and a drain electrode.

Subsequently, the second conductive layer and the ohmic contact layer of the channel region are sequentially etched by applying the second photoresist pattern as an etch mask to form source and drain electrodes 402s and 402d.

Through this process, a thin film transistor which is a switching element of a unit pixel is completed.

Source and drain electrodes 402s and 402d and the storage electrode 405 formed through the second mask process are identified in FIG. 6D.

Referring to FIG. 6D, the pixel electrode 410 in the unit pixel is not connected to the drain electrode 402d and the storage electrode 405, respectively. Therefore, a process of connecting the pixel electrode 410, the drain electrode 402d, and the storage electrode 405, respectively, is further required.

Prior to the process, a second insulating layer 503 that insulates the source, drain electrode, and pixel electrode 405 is formed on the first substrate by a plasma chemical vapor deposition method or the like.

Subsequently, referring to FIG. 6E, the present invention applies a third mask to expose the drain electrode 402d and the pixel electrode 410 adjacent thereto, and the gate line 401c in front of the unit pixel and the first contact hole 610. The second contact hole 620 exposing the storage electrode 405 and the pixel electrode 410 formed on the upper surface of the pixel electrode 410 is formed.

The contact holes are formed by a photolithography process. That is, a first photoresist film is coated on the second insulating layer 503, and a third mask (not shown) is exposed and developed to form a first photoresist pattern 430 including a contact hole formation region.

Subsequently, the insulating layers of the contact hole region are removed by using the first photoresist pattern 430 as an etch mask to expose portions of the drain electrode 402d, the pixel electrode 410, and the storage electrode 405, respectively.

Subsequently, the third conductive layer 407a is deposited on the first substrate on which the contact holes are formed without removing the first photoresist pattern 430. The third conductive layer 407a is for connecting the drain electrode and the storage electrode to the pixel electrode, respectively, and may be any metal having conductivity.

Therefore, referring to FIG. 6F, the third conductive layer 407a is formed on the first photoresist pattern 430 and in the contact holes.

Subsequently, a second photosensitive film 440 is further coated on the third conductive layer 407a. As a result, the second photosensitive film is formed on the third conductive layer 407a while filling the contact holes.

In this case, the second photoresist film is relatively thicker in the contact hole.

Subsequently, the second photoresist film on the third conductive layer 407a except for the contact hole is ashed and removed. In the acing process, since the second photoresist film is formed thicker in the contact hole, the second photoresist film remains in the contact hole and is removed in the remaining area to expose the third conductive layer.

Subsequently, the third conductive layer 407a in the remaining region except for the contact hole is removed using the pattern of the second photosensitive film formed by being aceed as a mask.

In the process, connection patterns 406 and 407 are formed to connect the drain electrode 402d and the storage electrode 405 to the pixel electrode 410, respectively.

Subsequently, a first connection connecting the drain electrode 402d and the pixel electrode 410 by completely removing the first photoresist pattern 430 and the second photoresist pattern in the contact hole, which are used to form the contact holes, through a strip process. The pattern 407 and the second connection pattern 406 connecting the storage electrode 406 and the pixel electrode 410 are completed.

The cross section of the liquid crystal display device of the present invention completed as a result of the above process can be confirmed through Figure 6g.

As described above, the present invention can reduce the number of masks compared to the conventional method for manufacturing a liquid crystal display device using five or four masks by manufacturing the liquid crystal display device using only three masks. In addition, the production cost can be reduced by reducing the use of expensive masks. Reducing the use of masks also reduces the number of additional processes associated with it, resulting in increased productivity.

In addition, by simultaneously forming the active pattern and the drain electrode in the second mask process, it is possible to improve the reliability of the thin film transistor by reducing the generation of wave noise, which may occur due to misalignment of the ends of the drain electrode and the active pattern.

Claims (14)

Sequentially forming a transparent electrode layer and a first conductive layer on the first substrate; Patterning the transparent electrode layer and the first conductive layer to form a pixel electrode including a stacked gate line of the transparent electrode layer and the first conductive layer and the transparent electrode layer; Forming a first insulating layer on a first substrate on which the gate line and the pixel electrode are formed; Sequentially forming a semiconductor layer, an ohmic contact layer, and a second conductive layer on the first insulating layer; Patterning the semiconductor layer, the ohmic contact layer, and the second conductive layer to form a source electrode, a drain electrode, a storage electrode, and an active pattern; Forming a second insulating layer covering the source electrode, the drain electrode, the storage electrode, and the active pattern; Applying a first photosensitive film on the second insulating layer; Exposing and developing the first photoresist layer to form a first contact hole exposing the drain electrode and a pixel electrode adjacent thereto and a second contact hole exposing the storage electrode and a pixel electrode adjacent thereto; Forming a third conductive layer on the first substrate with the first photoresist pattern remaining; Applying a second photosensitive film on the third conductive layer; Acing the second photoresist film to form a second photoresist pattern so that the second photoresist film remains only in the first contact hole and the second contact hole; And And removing the third conductive layer exposed by the second photosensitive film pattern to form a first connection pattern electrically connecting the drain electrode and the pixel electrode. The method of claim 1, wherein the forming of the gate line and the pixel electrode is performed. Coating a photosensitive film on the first conductive layer; Diffractive exposure of the photoresist film to form a photoresist pattern having a photoresist pattern thinner than a region where a gate line is to be formed by applying diffraction exposure to a pixel region where a pixel electrode is to be formed; Applying the photoresist pattern as an etch mask to etch the first conductive layer and the transparent electrode layer to form a stacked gate line of the transparent electrode layer and the first conductive layer; Acing the photoresist pattern to remove the photoresist pattern on the pixel region; And And removing the first conductive layer of the pixel region by applying the aced photosensitive film pattern as a mask to form a pixel electrode formed of the transparent electrode layer. The method of claim 1, wherein the forming of the source electrode, the drain electrode, and the active pattern is performed. Coating a photosensitive film on the second conductive layer; Diffractive exposure of the photosensitive film to form a first photoresist film pattern; Forming an active pattern by sequentially etching the second conductive layer, the ohmic contact layer, and the semiconductor layer by applying the first photoresist pattern as an etching mask; Acing the first photoresist pattern to form a second photoresist pattern for exposing the second conductive layer in the channel region by removing the photoresist in the diffractive exposure region; And And forming a source electrode and a drain electrode by etching the second conductive layer and the ohmic contact layer of the channel region by applying the second photoresist pattern as an etch mask. 4. The method of claim 3, wherein the first photoresist pattern includes a photoresist pattern on which a storage electrode is to be formed near a front gate line. The method of claim 4, wherein the forming of the active pattern further includes a storage electrode overlapping the gate line and the pixel electrode. 4. The method of claim 3, wherein the photosensitive film on the channel region is diffracted and exposed in the step of forming the first photosensitive film pattern. The method of claim 1, wherein the forming of the first connection pattern further comprises a second connection pattern electrically connecting the storage electrode and the pixel electrode. The method of claim 7, wherein the first connection pattern and the second connection pattern are formed of the third conductive layer. delete delete A gate line formed on the substrate and comprising a transparent electrode layer and a first conductive layer stacked thereon; A pixel electrode formed on the substrate and composed of the transparent electrode layer; A first insulating layer formed on the substrate on which the gate line and the pixel electrode are formed; A data line formed on the first insulating layer and vertically crossing the gate line; An active pattern formed on the first insulating layer and formed of a semiconductor; A source electrode formed on the active pattern and branching from the data line and a drain electrode corresponding to the source electrode; A storage electrode formed on the first insulating layer and overlapping the gate line and the pixel electrode; A second insulating layer formed on the source electrode, the drain electrode, and the storage electrode; And And a second connection pattern electrically connecting the drain electrode and the pixel electrode, and a second connection pattern electrically connecting the storage electrode and the pixel electrode. 12. The liquid crystal display of claim 11, wherein the storage electrode overlaps the pixel electrode and the gate line with the semiconductor layer and the first insulating layer interposed therebetween. 12. The liquid crystal display of claim 11, further comprising a first contact hole exposing the drain electrode and a pixel electrode adjacent thereto and a second contact hole exposing the storage electrode and a pixel electrode adjacent thereto. . The liquid crystal display of claim 13, wherein the first connection pattern and the second connection pattern are formed in the first contact hole and the second contact hole, respectively.

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