KR101162508B1 - Semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package is provided to prevent contamination on a substrate or a chip by blocking an underfill material not to flow to a surface of a substrate or a semiconductor chip. CONSTITUTION: A semiconductor chip(20) is laminated on a substrate(10) to be conductive using a bump(30). The semiconductor chip has a plurality of through silicon vias(22). A trench(12) is formed on the top of the substrate adjacent to the circumference of the semiconductor chip. An underfill material(50) is filled in an space between the semiconductor chip and the substrate. A dam(28) is integrally formed on the circumference of the semiconductor chip.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package, and more particularly, to prevent the underfill material applied between the substrate and the semiconductor chip from flowing toward the surface of the substrate or the semiconductor chip, and pockets around the through silicon vias (TSV) of the semiconductor chip. It relates to a semiconductor package formed so that the upper chip can be easily stacked.

In general, a semiconductor package is manufactured by attaching a semiconductor chip to a substrate, connecting the semiconductor chip and the substrate with a conductive wire, and then sealing the semiconductor chip and the wire with a molding resin.

In the configuration of such a semiconductor package, since the conductive wire connecting the conductive pattern of the substrate and the bonding pad of the semiconductor chip has a predetermined length, it is a cause of increasing the size of the semiconductor package substantially, and in particular, the semiconductor chip has a high directivity. As a result, high performance and high speed have become a factor against the efforts to miniaturize semiconductor packages.

In view of this, a semiconductor package is proposed which electrically connects an electrode pad (= bonding pad) of a semiconductor chip to a conductive pattern of a substrate through a flip chip or bump made of a metal material. Flip chip ball grid array (FCBGA), wafer level chip size / scale package (WLCSP), chip-on-glass / tape carrier package ) Package.

1 shows a conventional semiconductor package in which a semiconductor chip and a substrate are connected by flip chip or bump.

In FIG. 1, reference numeral 20 denotes a semiconductor chip showing a structure in which a plurality of through silicon vias 22 are formed, and reference numeral 10 denotes a substrate (for example, a printed circuit board).

The through-silicon via 22 is formed by forming a vertical hole in a portion adjacent to the bonding pad of the semiconductor chip 20 at the wafer level, and electroplating through the plating process in the vertical hole in the form of an insulating film and a seed metal film on the surface of the vertical hole. It is formed by embedding the material, that is, the conductive metal 24.

In this case, the through-silicon via 22 is formed in contact with a bonding pad (not shown) of the semiconductor chip 20 or may be electrically conductive by a bonding pad (not shown) and redistribution of the semiconductor chip 20. You are connected.

Therefore, when the semiconductor chip 20 is attached to the substrate 10, each conductive pattern (not shown) of the substrate 10 and each through silicon via 22 of the semiconductor chip 20 are flip chips or bumps. By 30, it will be in the state connected electrically.

Meanwhile, the flip chip or bump 30 is firmly held in the space between the substrate 10 and the semiconductor chip 20, that is, the space where the flip chip or bump 30 exists, and at the same time between the flip chips or bumps 30. The underfill material, which is a kind of insulating material that can prevent contact of the injector, is injected.

More specifically, when the underfill material is dispensed on one side of the space between the substrate 10 and the semiconductor chip 20, the underfill material is sucked into the space where the flip chip or bump 30 exists due to capillary action. do.

Thereafter, the semiconductor chip 20 on the substrate 10 is formed into a semiconductor package through a molding process for encapsulating the semiconductor chip 20 with a molding resin.

However, the conventional semiconductor package has the following problems.

First, during the underfill process, the underfill material 50 is not only sucked into the space between the substrate 10 and the semiconductor chip 20 but also flows in the opposite direction (the edge of the substrate) to contaminate the substrate. There was a problem (see FIGS. 2A and 2B).

Second, when the underfill material is excessively dispensed, not only the underfill material 50 is sucked into the space between the substrate 10 and the semiconductor chip 20, but also some of the underfill material 50 that cannot be sucked into the semiconductor There was a problem of riding up the upper surface of the chip 20 to contaminate the bonding pad and through silicon via of the semiconductor chip (see FIG. 3).

Third, when the upper chip 40 is stacked on the upper surface of the semiconductor chip (lower chip) having the through silicon via, the copper filler 42 of the upper chip 40 is the through silicon via 22 of the semiconductor chip 20. When bonded to the conductive solder 44 through the media, the conductive solder due to the bridge between the adjacent copper fillers, there was a problem that the misalignment of the upper chip occurs (see Fig. 4).

That is, as shown in FIG. 4, when the upper chip 40 is stacked on the lower chip 20, the copper filler of the upper chip 40 is laminated by applying a thermal compression method that applies pressure while applying heat. 42 and the through-silicon vias 22 of the lower chip 20 are electrically connected to each other by the conductive solder 44. The conductive solder 44 is flattened during the thermal compression process and is in contact with the adjacent conductive solder. As a result, a bridge phenomenon in which adjacent copper fillers are connected is generated.

In addition, when the upper chip is stacked with respect to the lower chip, the upper chip should be stacked while maintaining the exact coordinates. However, since the through silicon vias of the lower chip, including the copper filler of the upper chip, have a fine pitch to each other, the upper chip The copper filler and the through-silicon vias of the lower chip are misaligned with each other.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. An underfill material applied between a substrate and a semiconductor chip is formed by forming a trench in the substrate or forming a dam at the edge of the semiconductor chip. It is an object of the present invention to provide a semiconductor package which can prevent flow toward the surface and form a pocket around the through silicon via (TSV) of the semiconductor chip so that the upper chip can be easily stacked without a misalignment phenomenon.

The present invention for achieving the above object is a semiconductor chip having a plurality of through-silicon vias on the substrate conductively stacked via a flip chip or bump, the space between the substrate and the semiconductor chip in which the flip chip or bump is present In a semiconductor package filled with an underfill material, a trench is formed at a top surface of a substrate adjacent to an edge of the semiconductor chip, and a copper filler of a top chip to be stacked is formed at a peripheral position of each through silicon via on the top surface of the semiconductor chip. Provided is a semiconductor package characterized in that a pocket that can be inserted is formed.

Preferably, a dam having a predetermined height is integrally formed on the upper edge of the semiconductor chip.

More preferably, a blocking groove for blocking the underfill material is further formed on the top edge or bottom edge of the semiconductor chip.

In addition, the bottom surface of the pocket is characterized in that it is formed horizontally with the top surface of each through silicon via, or lower than the top surface of each through silicon via.

In addition, when the bottom surface of the pocket and the through silicon vias are horizontal to each other, a conductive layer conductive with the conductive metal of the through silicon via is further formed on the bottom surface of the pocket.

Through the above-mentioned means for solving the problems, the present invention provides the following effects.

According to the present invention, when the underfill material is filled in the space between the semiconductor chip and the substrate where the flip chip or bump is present, by forming a trench in the substrate or forming a dam at the edge of the semiconductor chip, the underfill material is a trench or dam. By easily blocking the flow toward the surface of the substrate or the semiconductor chip it is possible to prevent contamination of the substrate or chip.

In addition, by forming a pocket around the through silicon via (TSV) of the semiconductor chip to guide the copper filler of the upper chip into the pocket, the upper chip can be easily stacked on the semiconductor chip without misalignment phenomenon.

1 is a schematic cross-sectional view showing a conventional semiconductor package,
2A and 2B are schematic cross-sectional views and actual micrographs illustrating a phenomenon in which a substrate is contaminated during an underfill process in a conventional semiconductor package;
3 is a schematic cross-sectional view illustrating a phenomenon in which a semiconductor chip is contaminated during an underfill process in a conventional semiconductor package;
4 is a schematic cross-sectional view illustrating a problem in stacking an upper chip in a conventional semiconductor package;
5 is a schematic cross-sectional view showing a semiconductor package according to a first embodiment of the present invention;
6 is a schematic cross-sectional view showing a semiconductor package according to a second embodiment of the present invention;
7 is a schematic cross-sectional view showing a semiconductor package according to a third embodiment of the present invention;
8 to 10 are schematic cross-sectional views showing a semiconductor package according to a fourth embodiment of the present invention;
11 to 13 are schematic cross-sectional views illustrating a stacked structure of a semiconductor chip applied to each embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First embodiment

5 is a schematic cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention.

In the package according to the first embodiment of the present invention, a semiconductor chip 10 having a plurality of through-silicon vias 22 is stacked on a substrate 10 so as to be electrically conductive through a flip chip or a bump 30, and a flip chip. Alternatively, the underfill material 50 may be filled in the space between the substrate 10 where the bumps 30 are present and the semiconductor chip 20.

At this time, according to the first embodiment of the present invention, the trench 12 is formed in the upper surface position of the substrate 10 adjacent to the edge of the semiconductor chip 20.

In more detail, the trench 12 may be formed around three or more edges of four edges of the semiconductor chip 20, and preferably, one edge of the four edges of the semiconductor chip is dispensed with an underfill material. It is formed long in the adjacent position and is formed in a predetermined depth in an insulating layer (for example, a solder mask) that forms the uppermost layer of the substrate.

Therefore, when the underfill material 50 is dispensed on one side of the space between the substrate 10 and the semiconductor chip 20, that is, at the position where the trench 12 is formed, the flip chip or bump 30 may be formed by capillary action. The underfill material 50 is sucked into the space between the substrate 10 and the semiconductor chip 20 in which is present.

At this time, during the underfill process, the underfill material 50 may not only be sucked into the space between the substrate 10 and the semiconductor chip 20, but also a part may flow in the opposite direction (the edge of the substrate). However, since the underfill material 50 is trapped in the trench 12, a phenomenon in which a part of the underfill material 50 flows to the substrate can be prevented, and thus the substrate 10 by the underfill material 50 is prevented. ) Can prevent contamination.

In addition, as the underfill material 50 is trapped in the trench 12, a phenomenon in which a portion of the underfill material 50 rises toward the upper surface of the semiconductor chip 20 can be prevented.

Second embodiment

6 is a schematic cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention.

In the package according to the second embodiment of the present invention, a semiconductor chip 10 having a plurality of through-silicon vias 22 is stacked on a substrate 10 so as to be electrically conductive via a flip chip or a bump 30, and a flip chip. Alternatively, the underfill material 50 may be filled in the space between the substrate 10 where the bumps 30 are present and the semiconductor chip 20.

At this time, according to the second embodiment of the present invention, a higher dam 28 is integrally formed at the edge of the semiconductor chip 20.

More specifically, when grinding the back surface of the semiconductor chip 20 in the wafer state, grinding is performed until the through silicon vias 22 are exposed, and then the center region excluding the edge portion of the semiconductor chip is etched. By allowing the through silicon vias 22 to be exposed, the edges of the semiconductor chip 20 are formed higher than other portions to form a kind of dam 28.

In addition, the dam 28 formed at the edge of the semiconductor chip 20 also serves to reinforce the rigidity of the semiconductor chip 20 having a fine thickness.

Accordingly, when the underfill material 50 is dispensed on one side of the space between the substrate 10 and the semiconductor chip 20, the substrate 10 and the semiconductor chip on which the flip chip or the bump 30 exists due to capillary action are present. The underfill material 50 is sucked into the interspace between the 20.

At this time, as the excess underfill material 50 is dispensed, a portion of the underfill material 50 rides up to the upper surface of the semiconductor chip 20 to be blocked at the dam 28, thereby easily preventing contamination of the semiconductor chip. can do.

Third Embodiment

7 is a schematic cross-sectional view illustrating a semiconductor package according to a third embodiment of the present invention.

The semiconductor package according to the third embodiment of the present invention is characterized by combining the first embodiment and the second embodiment.

That is, the semiconductor package according to the third embodiment of the present invention has a structure in which the trench 12 according to the first embodiment is formed on the substrate 10, and the dam 28 according to the second embodiment includes the semiconductor chip 20. The structure formed on the upper edge of the feature is applied at the same time.

Therefore, during the underfill process, the underfill material 50 is in a state in which the underfill material 50 is trapped in the trench 12, so that a part of the underfill material 50 can be prevented from flowing to the substrate, By the dam 28 of the semiconductor chip 10, the effect which can prevent the phenomenon which a part of the underfill material 50 rides up to the upper surface of the semiconductor chip 20 can be acquired simultaneously.

Fourth embodiment

8 to 10 are schematic cross-sectional views illustrating a semiconductor package according to a fourth embodiment of the present invention.

According to the fourth embodiment of the present invention, the top edge or the bottom edge of the semiconductor chip 20 is characterized in that the blocking groove 27 is formed to block the underfill material 50 and become a kind of accommodation space.

After a wide blade along a sawing line of a semiconductor chip in a wafer state passes a scratch of a predetermined depth, a small blade is cut along a substantial sawing line to be sawed into individual semiconductor chips. Blocking grooves 27, such as a right angle or a semicircle, may be formed in each sawing interface of the chip.

Accordingly, when the underfill material 50 is dispensed on one side of the space between the substrate 10 and the semiconductor chip 20, the substrate 10 and the semiconductor chip on which the flip chip or the bump 30 exists due to capillary action are present. Since the underfill material 50 is sucked into the interspace between the 20, at this time a portion of the underfill material 50 is drawn into the blocking groove 27 when it is going to ride up the upper surface of the semiconductor chip 20, As a result, the phenomenon that the underfill material flows toward the upper surface of the semiconductor chip can be easily prevented.

Herein, the stacked structure of the semiconductor chips to be applied to the first to fourth embodiments will be described below.

11 to 13 are schematic cross-sectional views illustrating a laminated structure of a semiconductor chip applied to each embodiment of the present invention.

In the semiconductor chip 20 applied to the first to fourth embodiments of the present invention, a pocket in which the copper filler 42 of the upper chip 40 to be stacked is inserted at a peripheral position of each through silicon via 22 ( 26) is characterized in that formed.

In the method of forming the pocket 26, the photoresist is attached to the upper surface of the semiconductor chip to expose and develop, and then the periphery of the through silicon via 22 is exposed, and then the exposed portion is etched. The pockets 26 having a predetermined depth may be formed around the through silicon vias 22.

As shown in FIG. 11, a pocket 26 of the semiconductor chip 20 is formed around each through silicon via 22, and a bottom surface of the pocket 26 is formed on an upper surface of each through silicon via 22. As shown in FIG. 12, the bottom surface of the pocket 26 may be lower than the top surface of each through silicon via 22.

In addition, as shown in FIG. 13, the bottom surface of the pocket 26 of the semiconductor chip 20 may be leveled with the top surface of each through silicon via 22, and then may be conductive with the through silicon via 22 thereon. The additional conductive layer 29 may be further coated to increase the conductive area that the copper filler 42 of the upper chip 40 to be stacked contacts.

Accordingly, each of the through silicon vias 22 of the semiconductor chip 20 and the copper filler 42 of the upper chip 40 are matched, and the upper chip 40 is stacked on the semiconductor chip 20. As shown in FIG. 2, even though the copper filler 42 of the upper chip 40 is misaligned with respect to the through silicon vias 22 of the semiconductor chip 20, the copper fillers 42 are formed of the through silicon vias 22. It is easily inserted into the peripheral pocket 26.

Accordingly, in the state in which the copper filler 42 of the upper chip 40 is inserted into the pocket 26, the conductive solder 44 applied to the end of the copper filler 42 by the thermal compression process is melted and compressed. At the same time, the through-silicon via 22 is spread, so that the copper filler 42 of the upper chip 40 is easily conductively connected to the through-silicon via 22 by the conductive solder 44.

Meanwhile, as shown in FIG. 13, in the state where the conductive layer 29 is formed to be conductive with the through silicon via 22 on the bottom surface of the pocket 26, the copper filler 42 of the upper chip 40 is formed in the pocket 26. Once the copper filler 42 is inserted into the lower end of the copper filler 42 is connected to the conductive layer 29 via the conductive solder 44, the copper filler 42 of the upper chip 40 is more easily connected to the semiconductor chip ( 20 may be electrically connected to the through silicon via 22.

10 substrate 12 trench
20: semiconductor chip 22: through silicon via
24: conductive metal 26: pocket
27: blocking groove 28: dam
29 conductive layer 30 flip chip or bump
40: upper chip 42: copper filler
44 conductive solder 50 underfill material

Claims (5)

A semiconductor chip 10 having a plurality of through-silicon vias 22 on the substrate 10 is electrically stacked on the substrate 10 via a flip chip or bump 30, and the substrate 10 having the flip chip or bump 30 is present. In a semiconductor package in which an underfill material 50 is filled in the space between the semiconductor chip 20 and the semiconductor chip 20,
A trench 12 is formed at an upper surface position of the substrate 10 adjacent to the edge of the semiconductor chip 20, and an upper chip to be stacked at a peripheral position of each through silicon via 22 on the upper surface of the semiconductor chip 20. The semiconductor package, characterized in that the pocket (26) in which the copper filler (42) of the (40) can be inserted.
The method according to claim 1,
The semiconductor package, characterized in that the dam (28) having a predetermined height integrally formed on the upper edge of the semiconductor chip (20).
The method according to claim 1,
A semiconductor package, characterized in that a blocking groove 27 for blocking the underfill material 50 is further formed on the top edge or bottom edge of the semiconductor chip 20.
The method according to claim 1,
The bottom surface of the pocket (26) is a semiconductor package, characterized in that parallel to the top surface of each through silicon via (22) or lower than the top surface of each through silicon via (22).
The method of claim 4,
When the bottom surface of the pocket 26 and the through silicon via 22 are horizontal to each other, the conductive layer 29 conductive with the conductive metal 24 of the through silicon via 24 over the bottom surface of the pocket 26. ) Is further formed a semiconductor package.

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