KR101153378B1 - Back junction solar cells using a Floating junction and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to a back electrode solar cell using a floating junction and a method of manufacturing the same. The present invention forms an n + BSF layer 108 in which an n-type dopant is diffused and a p + emitter layer 112 in which a p-type dopant is diffused. Then, n + dopant is doped on the surface of the p + emitter layer 112 by a plasma doping method to form an n + layer 118. This state is a floating junction state. When such a floating junction is formed, a barrier is formed in the floating bonded portion due to a pn junction, and thus a hole, which is a plurality of carriers collected from the n-type silicon substrate 100, to the p + emitter layer 112. Due to the barrier, it has the advantage of reducing the loss due to recombination to improve the efficiency of the solar cell. In addition, when the oxide film (SiO ₂ ) is deposited on the back surface of the n-type silicon wafer 100 during the manufacturing process, low-temperature deposition is performed using PECVD (Plasma-enhanced chemical vapor deposition) equipment, thereby reducing the process cost.

Back electrode, back junction, emitter, floating junction, passivation, solar cell

Description

Back junction solar cells using a floating junction and method for manufacturing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back electrode solar cell, and more particularly, to form a floating junction by diffusing different types of dopants in the emitter region of the back of the solar cell, thereby using a back electrode solar using a floating junction to reduce surface recombination. A battery and a method of manufacturing the same.

The electrodes of the solar cell are formed on the front and rear surfaces of the solar cell, respectively, but the electrodes formed on the front face reduce the shadowing loss to sunlight. Therefore, in order to improve the efficiency of solar cells, the general trend is to narrow the area of the electrode formed on the front surface to have a fine pattern as much as possible.

However, even in this case, sunlight does not absorb as much as the electrode area formed on the front surface.

Therefore, in order to fundamentally eliminate the reduction of absorption by the electrode at the front of the solar cell, a rear electrode solar cell in which all the electrodes are installed at the rear has been developed. The back electrode solar cell includes a base junction for collecting a p-type (or n-type) charge on a back surface opposite to a front surface where light is incident on a p-type (or n-type) silicon substrate and n formed on the silicon substrate. Emitter junctions that collect charges of the type (or p-type) are all located, so that electrons and holes are collected by electrodes formed on the back of the solar cell.

The back electrode solar cell will be described with reference to FIG. 1.

Referring to FIG. 1, an n + front surface field layer (3) doped on a front surface of an n-type silicon wafer 1 (that is, a surface into which sunlight is incident) has a higher concentration of impurities than the silicon wafer 1. ) Is formed, and a thermal oxidation film 4 and an antireflection film 5 are formed thereon. The n + FSF layer 3 serves to reduce the recombination of charges on the surface of the silicon wafer 1 and to reduce the resistance loss in the silicon bulk. The thermal oxide film 4 and the anti-reflection film 5 serve as a passivation layer to reduce light reflection on the entire surface of the silicon wafer 1.

On the back surface of the n-type silicon wafer 1, an n + back surface field layer 7 in which an n-type dopant is diffused and a p + emitter layer 9 in which a p-type dopant is diffused are formed at predetermined intervals. do.

A passivation layer 11 is formed on the n + BSF layer 7 and the P + emitter layer 9. The passivation layer 11 serves to reduce the recombination rate at the back surface of the n-type silicon wafer 1.

On the passivation layer 11, n-metal fingers penetrating a portion of the passivation layer 11 and bonding with the n + BSF layer 7 and the p + emitter layer 9 to collect electrons and holes ( 13) and a p-metal finger 15 are formed.

In the above structure, when sunlight is incident on the entire surface of the n-type silicon wafer 1, negatively-charged electrons and positively-charged holes are generated in the silicon wafer 1. The holes are transferred directly through the p + emitter layer 9 to a p-metal finger 15 bonded to the p + emitter layer 9. On the other hand, the electrons are transferred across the n-type silicon wafer 1 or through the n + FSF layer 3 to the n-metal finger 13.

On the other hand, the passivation layer 11 formed to reduce the recombination rate on the back surface of the n-type silicon wafer 1 is formed of silicon dioxide (SiO ₂ ). The formation method uses a thermal oxidation process. Of course, SiNx may be deposited by amorphous silicon or PECVD deposition. However, silicon dioxide formed by the thermal oxidation process provides the best characteristics of the passivation layer 11, and this method is widely used.

However, the structure in which the passivation layer 11 is in direct contact with the p + emitter layer 9 has a problem as follows.

That is, in the passivation layer 11 formed by the thermal oxidation process, interface states such as lattice mismatch and defects exist at the interface with the P + emitter layer 9.

The interfacial state results in loss of recombination of the carrier. This is one of the causes of lowering the efficiency of the solar cell.

In addition, the p + emitter layer 9 is configured to occupy a relatively larger area than the n + BSF layer 7 on the rear surface of the n-type silicon wafer 1. Such a structure is also responsible for increasing recombination at the surface.

Accordingly, an object of the present invention is to solve the above problems, and to reduce the loss due to recombination of holes generated by light at the back surface of the semiconductor substrate.

According to an aspect of the present invention for achieving the above object, a first doped region doped with a first dopant of a first conductivity type and a second doped dopant of a second conductivity type are formed on a rear surface of a semiconductor substrate having a first conductivity type. Forming a doped region; And forming a floating junction by doping with the dopant of the first conductivity type in the second doped region.

The dopant of the first conductivity type is doped with p + dopant or n + dopant.

The floating junction is formed by doping the first conductivity type dopant by plasma doping.

According to another feature of the present invention, a semiconductor substrate of a first conductivity type, a first doped region doped with the first conductivity type formed on the rear surface of the semiconductor substrate and spaced apart from each other, and a second opposite to the first conductivity type A second doped region doped with a conductivity type; And a third doped region formed by floating doping with a second dopant of the first conductivity type in the second doped region.

In the present invention, a p-n junction is formed by doping and floating a dopant having a conductivity type opposite to that of the emitter layer on the surface of the emitter layer formed on the rear surface of the back electrode solar cell.

Therefore, the loss caused by the recombination of carriers on the back surface of the back electrode solar cell can be reduced, and the efficiency of the solar cell can be improved.

In addition, although the passivation layer is conventionally formed by a high temperature process, in the present invention, since the passivation layer can be deposited at a relatively low temperature by using a plasma-enhanced chemical vapor deposition (PECVD) equipment, the cost of the manufacturing process can be reduced. Can be.

Hereinafter, a preferred embodiment of a back electrode solar cell and a method of manufacturing the same using a floating junction of the present invention will be described in detail with reference to the accompanying drawings.

In this embodiment, an n-type silicon wafer will be described as an example.

2 is a cross-sectional view illustrating a method of manufacturing a back electrode solar cell using a floating junction according to an exemplary embodiment of the present invention.

FIG. 2A illustrates a silicon wafer 100 in which a cleaning process is completed to remove impurities formed on a surface of the wafer when the wafer is cut, perform a texturing process, and remove impurities.

As shown in FIG. 2B, a thermal oxidation process is performed on the front, rear, and side surfaces of the silicon wafer 100 to form a thermal oxide film 102.

When the thermal oxide film 102 is formed, the etching paste 104 is patterned and etched only at the portion where the base region (n + BSF layer) is to be formed, as shown in FIG. 2C.

The etching paste 104 is removed when etching is complete. Then, as illustrated in FIG. 2D, only the patterned portion of the etching paste 104 is removed. In addition, the thermal oxide film formed on the entire surface of the silicon wafer 100 is removed.

In this case, as shown in FIG. 2E, the silicon wafer 100 has a state in which the thermal oxide film is partially removed.

In this state, n + dopant is diffused only in the etched portion. The n + FSF layer 106 is formed on the front surface of the silicon wafer 100 and the n + BSF layer 108 is formed on the back surface of the silicon wafer 100. This state is as shown in FIG. 2F.

Thermal oxidation is performed on the front and rear surfaces of the silicon wafer 100. As a result, the thermal oxide film 104 is formed on the front, rear, and side surfaces of the silicon wafer 100 as shown in FIG. 2G. The thermal oxide film is denoted by reference numeral 104. For reference, the thermal oxide film formed on the surface of the silicon wafer 100 is repeatedly removed and formed, and the overall shape is formed differently every time. In this embodiment, the thermal oxide film is referred to as a thermal oxide film. I will explain.

Next, the etching paste 110 is patterned again to form an emitter region (p + emitter layer) 112 (see FIG. 2J). At this time, the etching paste is not applied to the entirety of the thermal oxide film formed on the rear surface, and only a portion of the etching paste is patterned as shown in FIG. 2H. That is, when the p + emitter layer 112 is formed in a subsequent process, the p + emitter layer 112 and the n + BSF layer 108 already formed according to the process of FIG. 2F are formed so as not to be in contact with each other. It is preferable.

Etching is performed while the etching paste 110 is formed as shown in FIG. 2H. Then, the etching paste 110 and the thermal oxide film corresponding thereto are removed. This state is shown in Fig. 2i.

The p + dopant is diffused to the region from which the thermal oxide film is removed to form the p + emitter layer 112. This is illustrated in FIG. 2J, whereby the n + BSF layer 108 and the p + emitter layer 112 are separated from each other by the etching paste 110.

When the n + BSF layer 108 and the p + emitter layer 112 are formed, a passivation layer is formed by plasma-enhanced chemical vapor deposition (PECVD) on the entire rear surface of the silicon wafer 100 as shown in FIG. 2K. (SiO ₂ ) 114 is deposited. The passivation layer 114 is to improve the recombination rate at the back surface as described.

Next, as shown in FIG. 2L, the etching paste 116 is patterned only under the passivation layer 114 having the p + emitter layer 112. The etching paste 116 is not formed on the emitter electrode portion formed in the subsequent electrode forming process. After etching in that state, the etching paste 116 is removed.

As the etching paste 116 is removed, the etching paste 116 is not formed as shown in FIG. 2M, leaving only the unetched passivation layer 114 ′.

In this state, as shown in FIG. 2N, when the n + dopant is diffused on the surface of the p + emitter layer 112, a part of the p + emitter layer 112 becomes the n + layer 118. This state is called floating junction. The floating junction allows the n + layer 118 to be formed thin using plasma doping techniques. In the floating bonding state, boron elements included in the p + emitter layer 112 are reduced. This can reduce the recombination at the interface. That is, since the n + dopant is diffused on the surface of the p + emitter layer 112 to form an n + floating junction, the passivation effect in the p + emitter layer 112 is increased.

When the floating junction is formed on the p + emitter layer 112, a passivation layer (SiO ₂ ) 114 is deposited on the portion from which the etching paste is removed for the floating junction by PECVD.

When the passivation layer 114 is deposited, the etching paste 120 is placed in an area that can be in contact with the n + BSF layer 108 and the p + emitter layer 112 to form a contact hole for forming an electrode. Form. This is shown in Figure 2p.

When the etching paste 120 is removed after the etching, the contact holes 120a and 120b are formed as shown in FIG. 2Q. The contact hole 120a is a contact hole for the base electrode, and 120b is a contact hole for the emitter electrode.

In the formed contact holes 120a and 120b, a base electrode 130a and an emitter electrode 130b are formed as shown in FIG. 2R.

3 is an energy band diagram of a floating junction in a back electrode solar cell manufactured according to the present invention.

Referring to FIG. 3A, as described above with reference to FIG. 2, it can be seen that the n + dopant is diffused under the p + emitter layer 112 to form the n + layer 118.

Then, as shown in (b) of FIG. 3, a barrier is formed due to the pn junction of the p + emitter layer 112 and the n + layer 118, thereby forming an n-type silicon substrate 100. Holes, the majority carriers collected into the p + emitter layer 112, are retracted by the barrier, preventing the recombination probability and eventually increasing the collection probability of the carriers.

In addition, when the p + emitter layer 112 is floating bonded due to the p-n junction of the n + layer 118, the boron dopant in the p + emitter layer 112 can be reduced, thereby reducing the recombination rate.

As described above, in the embodiment of the present invention, a floating junction in which another dopant is diffused to the emitter layer formed on the rear surface of the rear electrode solar cell reduces the loss due to recombination of carriers on the rear surface. have.

Although described with reference to the illustrated embodiment of the present invention as described above, this is merely exemplary, those skilled in the art to which the present invention pertains various modifications without departing from the spirit and scope of the present invention. It will be apparent that other embodiments may be modified and equivalent. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In other words, in the present embodiment, an n-type silicon wafer is described as an example, but the present invention is also applied to a p-type silicon wafer. In this case, since an n + emitter layer is formed on the rear surface, the p + type dopant is doped to form a floating junction.

1 is a cross-sectional view of a typical back electrode solar cell

2 is a cross-sectional view illustrating a method of manufacturing a back electrode solar cell using a floating junction according to an exemplary embodiment of the present invention.

3 is an energy band diagram of a floating junction in a back electrode solar cell manufactured according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: n-type silicon wafer 112: p + emitter layer

114: passivation layer 118: floating bonded n + layer

Claims (4)

Forming a first doped region doped with a first conductive dopant and a second doped region doped with a second conductive dopant opposite to the first conductive type on a back surface of the semiconductor substrate having the first conductive type ; And And forming a floating junction by doping with the dopant of the first conductivity type in the second doped region. The method of claim 1, The first conductive dopant is a method of manufacturing a back-electrode solar cell using a floating junction, characterized in that the doping with p + dopant or n + dopant. 3. The method of claim 2, The floating junction is a method of manufacturing a back-electrode solar cell using a floating junction, characterized in that the first conductive dopant is doped by plasma doping is formed. A semiconductor substrate of a first conductivity type; A first doped region doped with the first conductive type and a second doped region doped with a second conductive type opposite to the first conductive type formed on a rear surface of the semiconductor substrate to be spaced apart from each other; And And a third doped region formed by floating doping the second doped region with a dopant of the first conductivity type.

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