KR101102051B1 - Auto partial array self refresh device - Google Patents

Abstract

The present invention relates to an automatic partial array self refresh apparatus, and more particularly, to perform self refresh using an extended mode register set (hereinafter referred to as EMRS) as well as to select a bank or A technique for reducing current consumption by automatically self-refreshing a block is disclosed. To this end, the present invention provides a bank cell refresh signal generator for selectively outputting a bank latch signal using a bank activation signal and an EMRS cell refresh signal using an EMRS setting, selecting a bank and controlling a self refresh operation of the selected bank; And a bank area divider configured to selectively output an address latch signal using the bank address information of the selected bank and an area split signal using EMRS, to divide the area of the selected bank, and to control the selected area to be self-refreshed. It is characterized by.

Description

Auto partial array self refresh device

1 is a block diagram of an automatic partial array self refresh apparatus according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the active address latch unit of FIG. 1. FIG.

The present invention relates to an automatic partial array self refresh apparatus, and more particularly, to perform self refresh using an extended mode register set (hereinafter referred to as EMRS) as well as to select a bank or This technology reduces current consumption by automatically self-refreshing the block.

In general, self-refresh means that a semiconductor memory device, such as a dynamic random access memory (DRAM), has a predetermined period or a basic period internally to maintain data stored in a memory cell in a standby state. Means to do.                         

This self-refresh is a function of partial array self refresh (PASR) which performs only self-refresh of the memory cell array of the part where meaningful data exists and the output signal of the external temperature sensor to the temperature change. Therefore, it is divided into Temperature Compensated Self Refresh (TCSR) operation that adjusts the self refresh cycle.

In particular, the PASR mode can reduce the current consumption of the entire chip by accessing a specific bank only in the refresh mode, and is used in DRAMs used in mobile applications such as mobile phones or personal portable terminals, which are sensitive to current consumption. Is being applied.

In order to drive such a PASR mode, a bank to be driven is previously specified using EMRS.

Table 1 below is a conceptual diagram showing the specifications of the EMRS of the low-power 128M DRAM according to the prior art.

In order to use the PASR function, the memory area to be refreshed must be selected through at least one EMRS instruction before starting the self refresh. That is, the memory area should be selected by the combination of A <0: 2> among the EMRS commands.                         

However, when the desired bank and its region are selected through the EMRS setting, it is inconvenient to check the memory capacity to be used in advance in the PASR mode operation and then set the EMRS.

The present invention was created to solve the above problems, and more specifically, it is possible to perform cell refresh using an extended mode register set (EMRS), as well as using bank address information. The objective is to allow the user to select a specific bank or block to perform automatic partial array self refresh regardless of EMRS.

In addition, not only the area within the bank to perform cell refresh can be selected by using the EMRS, but also the area to be refreshed in the bank is driven by dividing the selected bank using the bank address information irrespective of the EMRS. The purpose is to reduce current consumption.

In order to achieve the above object, the partial array self refresh apparatus of the present invention selectively outputs a bank latch signal using a bank activation signal and an EMRS cell refresh signal using an EMRS setting to select a bank and perform a self refresh operation of the selected bank. Selectively outputs a bank cell refresh signal generation unit to control, an address latch signal using bank address information of the selected bank, and an area division signal using EMRS, to divide the selected bank area and to perform a self-refresh operation of the selected area. And a bank area divider.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

1 is a block diagram of an automatic partial array self refresh apparatus according to an embodiment of the present invention.

The partial array self refresh apparatus includes a bank cell refresh signal generator 100 and a bank region divider 200.

The bank cell refresh signal generation unit 100 includes a plurality of active address latch units 101, NOR gates NOR0 to NOR3, and inverters IV0 to IV3.

The plurality of active address latch units 101 receive bank activation signals BA0 to BA3, respectively, and output bank latch signals BA0_LAT to BA3_LAT. Here, the bank activation signals BA0 to BA3 are address information signals of the banks to be activated, and the bank latch signals BA0_LAT to BA3_LAT are signals for controlling the cell refresh of the bank selected according to the bank activation signals BA0 to BA3.

The NOR gates NOR0 to NOR3 perform a phantom operation on the bank latch signals BA0_LAT to BA3_LAT and the EMRS cell refresh signals BA0_SR to BA3_SR. Here, the EMRS cell refresh signals BA0_SR to BA3_SR are signals for controlling bank selection and cell refresh using an extended mode register set (hereinafter, referred to as EMRS).

The inverters IV0 to IV3 invert the output signals of the NOR gates NOR0 to NOR3, respectively, and output the bank cell refresh signals BA0_SR_D to BA3_SR_D. Here, the bank cell refresh signals BA0_SR_D to BA3_SR_D are signals for controlling to refresh the selected bank.

The bank area divider 200 includes a bank double cycle signal generator 300 and a bank quadruple signal generator 400.

The bank double cycle signal generation unit 300 includes an active address latch unit 301, a NOR gate NOR4 and NOR5, and inverters IV4 and IV5.

The inverter IV4 inverts the bank upper address signal BX12, and the NOR gate NOR4 performs a nil operation on the output signal bank upper address signal BX11 of the inverter IV4.

The active address latch unit 301 latches the output signal of the NOR gate NOR4 to output the address latch signal BX12_LAT. The NOA gate NOR5 performs a NO operation on the address latch signal BX12_LAT and the double cycle signal double_Period, and the inverter IV5 inverts the output signal of the NOGATE NOR5 to output the bank double cycle signal double_Period_D. In this case, the double period signal double_Period is a signal for dividing the bank area into half using the setting of EMRS and controlling the self refresh of the selected area.

The bank four cycle signal generation unit 400 includes an active address latch unit 401, a noor gate NOR6, a NOR7, and an inverter IV6.

The NOR gate NOR6 performs a no operation on the bank upper address signals BX11 and BX12, and the active address latch unit 401 latches the output signal of the NOR gate NOR6 to output the address latch signal BX11_LAT. The NOR gate NOR7 performs a NO operation on the address latch signal BX11_LAT and the quadruple cycle signal Quadruple_Period, and the inverter IV6 inverts the output signal of the NOR gate NOR7 to output the bank quadruple signal Quadruple_Period_D. In this case, the quadruple_period quadruple_period is a signal for dividing the bank area into quarters using the EMRS setting and controlling the self refresh of the selected area.

As such, the bank cell refresh signal generator 100 selectively selects a bank by using the bank latch signal BA_LAT using the bank activation signal and the EMRS cell refresh signal BA_SR using the EMRS, and controls the cell bank to be refreshed.

That is, it is possible to control not only to select a bank and to perform cell refresh using EMRS, but also to directly select a bank and perform cell refresh using a bank activation signal regardless of EMRS.

In addition, the bank area divider 200 divides a bank area using EMRS and performs cell refresh only for a corresponding area to perform a cell refresh. In addition to performing the cell refresh control, only the desired area in the selected bank is performed using the bank address information regardless of the EMRS.

 FIG. 2 is a detailed circuit diagram of the active address latch unit 101 of FIG. 1.

The active address latch unit 101 includes a bank activation signal applying unit 410, an initialization unit 420, a latch unit 430, and a logic combination unit 440.

The bank activation signal applying unit 410 includes a pulse generator 411, an inverter IV7, and a PMOS transistor PM.

The pulse generator 411 receives the bank activation signal BA to generate a pulse signal, the inverter IV7 inverts the output signal of the pulse generator 411, and the PMOS transistor PM is connected between the power supply voltage terminal VDD and the node N1. Is controlled by the output of inverter IV7 to apply the supply voltage level to node N1.

The initialization unit 420 includes NMOS transistors NM1 and NM2 between the node N1 and the ground voltage terminal VSS. The NMOS transistor NM1 is controlled by the power-up signal PWRUP and the NMOS transistor NM2 is controlled by the power-down mode signal PD to initialize the ground voltage level to the node N1 in the power-up mode and the power-down mode, respectively.

The latch unit 430 includes inverters IV8 and IV9 having a feedback structure to maintain the potential of the node N1 at a constant level.

The logic combination unit 440 includes an inverter IV10 and a no-gate NOR7.

The inverter IV10 inverts the cell refresh mode signal SRF, and the NOA gate NOR7 performs a NO operation on the output signal of the latch unit 430 and the output signal of the inverter IV10 to output the bank latch signal BA_LAT. In this case, the cell refresh mode signal SRF is a signal for controlling the internal circuit to enter the cell refresh mode.

Meanwhile, detailed configurations of the active address latch unit 301 of the bank double cycle signal generator 300 and the active address latch unit 401 of the bank quadruple signal generator 400 are the same as those of FIG. 2.

 Hereinafter, the operation of the partial array self refresh apparatus will be described with reference to Tables 2 and 3.

Noah gates NOR0 to NOR3 of the bank cell refresh signal generator 100 output high bank cell refresh signals BA0_SR_D to BA3_SR_D when the bank latch signals BA0_LAT to BA3_LAT are high level, regardless of the cell refresh signals BA0_SR to BA3_SR. If the signals BA0_LAT to BA3_LAT are at the low level, the bank cell refresh signals BA0_SR_D to BA3_SR_D are output in accordance with the cell refresh signals BA0_SR to BA3_SR.

In other words, when the bank is selected using the EMRS setting and the self refresh is performed, the bank latch signals BA0_LAT to BA3_LAT are disabled at a low level, and the bank cell refresh signals BA0_SR_D to BA3_SR_D are output according to the cell refresh signals BA0_SR to BA3_SR. When the bank is selected and the self refresh is performed without the EMRS setting, the bank cell refresh signals BA0_SR_D to BA3_SR_D are output according to the bank latch signals BA0_LAT to BA3_LAT.

Table 2 is an operation truth table of the input / output signals when the bank 0 is selected using the bank activation signal BA without using the cell refresh signal BA_SR due to the EMRS setting of the bank cell refresh signal generator 100 in the self refresh mode. .

First, to self-refresh bank 0, bank enable signal BA0 is enabled at high level and the remaining bank enable signals BA1 to BA3 are disabled at low level. Accordingly, the active address latch unit 101 enables the bank latch signal BA0_LAT to the high level and disables the bank latch signals BA1_LAT to BA3_LAT to the low level, so that only the bank cell refresh signal BA0_SR_D is enabled to the high level. The remaining bank cell refresh signals BA1_SR_D to BA3_SR_D are disabled at a low level so that only bank 0 is selected and cell refresh is performed.

On the other hand, although not shown in Table 2, when cell refresh by EMRS setting is to be performed, the bank latch signal BA_LAT is disabled to a low level, and the bank cell refresh signal BA_SR_D is output using the cell refresh signal BA_SR.

Subsequently, the bank doubling signal generator 300 and the bank doubling signal generator 400 divide the area within the bank into half or quarter by using the EMRS setting or without the EMRS setting. To perform.

In other words, when the self-refresh is performed by selecting the area to be refreshed in the bank using the EMRS setting, the address latch signals BX12_LAT and BX11_LAT are disabled at a low level, and bank 2 according to the double cycle signals double_Period and quadruple cycle Quadruple_Period. When outputting double cycle signal double_Period_D and bank 4-fold signal Quadruple_Period_D, and performing self-refresh by selecting the area to be refreshed in the bank without setting EMRS, address latch signal is independent of double cycle signal double_Period and quadruple signal Quadruple_Period. The bank double cycle signal double_Period_D and the bank quadruple signal Quadruple_Period_D are output according to BX12_LAT and BX11_LAT.                     

Table 3 is an operation truth table of signals of the bank double cycle signal generator 200 and the bank quadruple signal generator 300.

First, when the area within the bank is divided into halves, the bank upper address signal BX12 becomes low level and BX11 becomes high level, and the active address latch unit 301 outputs the address latch signal BX12_LAT of high level. Accordingly, the bank double cycle signal generator 300 outputs the high level bank double cycle signal double_Period_D, while the bank double cycle signal generator 400 outputs the low level bank quadruple signal Quadruple_Period_D. do.

In this way, the bank double cycle signal generator 300 divides the bank into halves through the bank double cycle signal double_Period_D and self-refreshs an area above or below the half area.

On the other hand, when the area in the bank is divided into quarters, the bank upper address signals BX11 and BX12 are all at the low level, and the active address latch unit 301 outputs the high level address latch signal BX11_LAT. Accordingly, the bank quadruple signal generator 400 outputs a high level bank quadruple signal Quadruple_Period_D, while the bank quadruple signal generator 300 outputs a low level bank double cycle signal double_Period_D. do.

As such, the bank quadruple signal generation unit 400 divides the bank into quarters through the bank quadruple signal Quadruple_Period_D and performs self-refreshing of a portion of the quarter area.

As described above, the present invention selects a bank to perform cell refresh through the bank cell refresh signal generator 100, and uses the bank double cycle signal generator 300 and the bank quadruple signal generator 400. Cell refresh is performed by dividing the region into half or quarter.

In addition, the present invention may not only perform a self refresh by selecting a bank by the EMRS setting, but also enable a user to perform a self refresh by selecting a bank without the EMRS setting by using a bank activation signal.

As described above, the present invention can not only perform cell refresh using an extended mode register set (EMRS), but also use a bank activation signal regardless of EMRS using bank address information. This has the effect of selecting a specific bank or block and performing automatic partial array self refresh.

In addition, an area within a bank to perform cell refresh can be divided and selected using EMRS. In addition, the user can divide a selected bank using bank address information and drive only an area to be refreshed in the bank regardless of EMRS. As a result, current consumption is reduced.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, various modifications, changes, substitutions and additions will be possible to those skilled in the art through the spirit and scope of the appended claims, such modifications and modifications are as follows It should be regarded as belonging to the claims.

Claims (14)

A bank latch signal using a bank activation signal and an EMRS cell refresh signal using EMRS settings are selectively output, and when the bank latch signal is activated, the bank latch signal is selected regardless of the EMRS cell refresh signal based on the activated bank latch signal. A bank cell refresh signal generator configured to control a self refresh operation of a selected bank based on the EMRS cell refresh signal when a bank and the bank latch signal are deactivated; And A bank area divider configured to selectively output an address latch signal using the bank address information of the selected bank and an area split signal using EMRS, to divide the area of the selected bank and to perform a self refresh operation of the selected area; Partial array self-refresh device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, wherein the bank cell refresh signal generation unit, An active address latch unit for selecting the bank using the bank activation signal and the cell refresh mode signal and outputting the bank latch signal for controlling the cell refresh of the selected bank; And A logic operation unit selectively outputting the bank latch signal and the EMRS cell refresh signal Partial array self-refresh device comprising a. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 2, wherein the logic operation unit, A partial array self refresh device comprising a noah gate. Claim 4 was abandoned when the registration fee was paid. The method of claim 2, wherein the active address latch unit, A bank activation signal applying unit applying a power supply voltage level to an output node according to the bank activation signal; An initialization unit for applying a ground voltage level to the output node during initialization; A latch unit for maintaining the potential of the output node at a constant level; And A logic combination unit for logically combining the output signal of the latch unit and the cell refresh mode signal; Partial array self-refresh device comprising a. Claim 5 was abandoned upon payment of a set-up fee.  The method of claim 4, wherein the bank activation signal applying unit, A pulse generator for outputting a signal having a predetermined pulse using the bank activation signal; And A switching element controlled by an output signal of the pulse generator to apply the power supply voltage level to the output node; Partial array self-refresh device comprising a. Claim 6 was abandoned when the registration fee was paid. 6. The partial array self refresh apparatus according to claim 5, wherein the switching element is a PMOS transistor. Claim 7 was abandoned upon payment of a set-up fee.  The method of claim 4, wherein the initialization unit, A first switching element controlled by a power-up signal to apply the ground voltage level to the output node; And A second switching element controlled by a power down signal to apply the ground voltage level to the output node Partial array self-refresh device comprising a. Claim 8 was abandoned when the registration fee was paid.  8. The partial array self refresh device of claim 7, wherein the first and second switching elements are NMOS transistors. Claim 9 was abandoned upon payment of a set-up fee.  The method of claim 4, wherein the logical combination portion, Partial array self refresh device, characterized in that it is a noah gate. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, wherein the bank area division unit, Bank 2 which selectively divides the bank into half regions by selectively outputting a double period signal among the address latch signal and the region division signal, and selects a region to perform cell refresh among the half regions to perform the cell refresh. A cycle signal generator; And A bank for dividing the bank into a quarter region by selectively outputting a quadruple period signal among the address latch signal and the region division signal, and selecting a region to perform the cell refresh from the quarter region to perform the cell refresh. A quadruple cycle signal generator; Partial array self-refresh device comprising a. Claim 11 was abandoned upon payment of a setup registration fee.  The method of claim 10, wherein the bank double cycle signal generation unit, A first logical operation unit for logically combining the address information; An active address latch unit for selecting an area within the bank and outputting the address latch signal for controlling the cell refresh of the selected bank area by using an output signal of the first logic operation unit and a cell refresh mode signal; And A second logic operation unit selectively outputting the address latch signal and the double period signal; Partial array self-refresh device comprising a. Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, wherein the active address latch unit, A bank activation signal applying unit for applying a power supply voltage level to an output node according to the bank address information; An initialization unit for applying a ground voltage level to the output node during initialization; A latch unit for maintaining the potential of the output node at a constant level; And A logic combination unit for logically combining the output signal of the latch unit and the cell refresh mode signal; Partial array self-refresh device comprising a. Claim 13 was abandoned upon payment of a registration fee.  The method of claim 10, wherein the bank four cycle signal generation unit, An active address latch unit for selecting an area within the bank using the bank address information and a cell refresh mode signal and outputting the address latch signal for controlling cell refresh of the selected bank area; And A logic operation unit selectively outputting the address latch signal and the quadruple cycle signal Partial array self-refresh device comprising a. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, wherein the active address latch unit, A bank activation signal applying unit for applying a power supply voltage level to an output node according to the bank address information; An initialization unit for applying a ground voltage level to the output node during initialization; A latch unit for maintaining the potential of the output node at a constant level; And A logic combination unit for logically combining the output signal of the latch unit and the cell refresh mode signal; Partial array self-refresh device comprising a.

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