KR101096692B1 - A display device - Google Patents

Abstract

The present invention relates to a display device capable of improving charging characteristics of a pixel cell, and includes a data line and a plurality of gate lines crossing each other; A plurality of pixel cells connected to the gate lines individually and commonly connected to the data lines; A data driver for supplying data signals having different polarities to the data lines; And a gate driver for supplying at least two scan pulses to each gate line and driving each gate line at least twice in a period where the polarities of the data signals supplied to the data lines are the same.

Liquid Crystal Display, Scan Pulse for Precharge, Scan Pulse for Main Charge, Pixel Voltage, Charge, Dot Inversion, Line Inversion

Description

Display device {A display device}

1 is a view schematically showing a conventional liquid crystal display device

FIG. 2 is a diagram illustrating various input signals supplied to the gate lines and the data lines of FIG. 1.

3A to 3C are diagrams for describing a driving method of a conventional liquid crystal display device.

4 is a diagram for describing a change in pixel voltage according to a change in polarity of the data voltage of FIG. 2.

5 illustrates a display device according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a scan pulse supplied to each gate line of FIG. 5 and a data signal supplied to a first data line.

FIG. 7 illustrates first and second shift registers included in the gate driver of FIG. 5. FIG.

8A through 8F are diagrams for describing an operation of pixel cells included in a portion C of FIG. 5 for each horizontal period.

9 is a view illustrating waveforms of another scan pulse supplied to each gate line of FIG. 5;

FIG. 10 is a view illustrating waveforms of another scan pulse supplied to each gate line of FIG. 5.

FIG. 11 is a diagram for describing a change in pixel voltage according to a change in polarity of the data voltage of FIG. 6.

* Explanation of symbols on the main parts of the drawings

GL1 to GLn: Gate lines Vpre1 to Vpren: Scan pulses for precharge

Vtg1 to Vtgn: main pulse scan pulse DL1: first data line

Vdata1 to Vdatam: data signal

The present invention relates to a display device, and more particularly, to a display device capable of improving charging characteristics of a pixel cell.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a gate on voltage applied to the gate terminal via the gate line, so that the data signal of the data line is charged to the pixel electrode.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a data signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the data signal for each liquid crystal cell.

Here, the gate driver includes a shift register to sequentially output the scan pulses as described above.

The shift register sequentially outputs the scan pulses and sequentially supplies the scan pulses to the gate lines, thereby sequentially driving the gate lines.

On the other hand, as the liquid crystal display becomes larger, the length of the gate line also becomes longer. As the length of the gate line increases, the resistance and capacitance components of the gate line also increase. Then, the scan pulse supplied to the gate line by the resistance and capacitance components may be distorted. If the scan pulse is distorted by the resistance and capacitance components, the rise time of the scan pulse is increased and the waveform thereof is distorted. Since the distorted scan pulse has a longer rise time than the ideal scan pulse, the effective charge time maintained at the target voltage is relatively short. When the scan pulse whose waveform is distorted is applied to the gate electrode of the thin film transistor, the turn-on time of the thin film transistor is shortened, so that the turned-on thin film transistor receives the data voltage from the data line. The switching time is also shortened.

Therefore, in order to solve this problem, a technique has been proposed to relatively increase the effective charge time by simultaneously driving the gate lines adjacent to each other for a certain period of time.

Hereinafter, a driving method of a conventional gate line will be described with reference to the accompanying drawings.

FIG. 1 is a diagram schematically illustrating a conventional liquid crystal display, and FIG. 2 is a diagram illustrating various input signals supplied to the gate lines and the data line DLm of FIG. 1.

In the conventional liquid crystal display, as shown in FIG. 1, a plurality of gate lines GLn-1 to GLn + 1 and a data line DLm intersecting with each other are connected to the corresponding gate line and the data line A plurality of pixel cells PXLn-1 to PXLn + 1 commonly connected to the DLm.

In this case, scan pulses Voutn-1 to Voutn + 1 are sequentially supplied to the gate lines GLn-1 to GLn + 1, and each gate line is supplied by the scan pulses Voutn-1 to Voutn + 1. (GLn-1 to GLn + 1) are driven sequentially. The data line DLm is charged with each gate line GLn-1 through GLn + 1.

Accordingly, the pixel cell connected to each of the corresponding gate lines and the data lines DLm receives an data signal charged in the data line DLm when the corresponding gate line is driven to display an image.

On the other hand, as shown in Figure 2, the section corresponding to the pulse width of the n-1 to n th scan pulses (Voutn-1 to Voutn + 1) is a precharge section (A) and the effective charge section (B). The preliminary charging section A of each scan pulse Voutn-1 to Voutn + 1 overlaps the effective charging section B of the previous scan pulse. Further, the effective charging section B of each scan pulse Voutn-1 to Voutn + 1 overlaps the preliminary charging section A of the next scan pulse Voutn-1 to Voutn + 1.

Therefore, each scan pulse Voutn-1 to Voutn + 1 starts to be output in the effective charging section B of the previous scan pulse and reaches the target voltage in its effective charging section B. In other words, each scan pulse Voutn-1 to Voutn + 1 gradually increases toward the target voltage in its preliminary charging section A, and then remains completely at the target voltage in its effective charging section B. .

Since the pulse widths between the scan pulses supplied to the adjacent gate lines overlap each other, the gate lines adjacent to each other are simultaneously driven in the period in which the scan pulses overlap. Therefore, two pixel cells adjacent to each other are simultaneously driven in the overlapping period, and the same data signal is supplied to each pixel cell. At this time, the two pixel cells receive their data signals in a period corresponding to the effective charging period of the scan pulses Voutn-1 to Voutn + 1 supplied to them.

2, the polarity of the data signal is reversed every horizontal period. Therefore, each adjacent pixel cell is supplied with a data signal having a different polarity. That is, the liquid crystal display shown in FIG. 1 is a liquid crystal display driven by a dot inversion method.

Referring to the driving method of the conventional liquid crystal display device configured as described above in detail.

3A to 3C are diagrams for describing a driving method of a conventional liquid crystal display device.

First, in the first period T1, as shown in FIG. 2, the n−1 th scan pulse Voutn−1 and the n th scan pulse Voutn are simultaneously output. Accordingly, as shown in FIG. 3A, the n-th gate line GLn-1 and the n-th gate line GLn are simultaneously driven. At this time, the first data signal Vdata1 having a negative polarity is supplied to the data line DLm. This first data signal Vdata1 is a data signal corresponding to the n-th pixel cell PXLn-1.

Accordingly, the first data signal Vdata1 is connected to the n-th pixel cell PXLn-1 and the n-th gate line GLn connected to the driven n-th gate line GLn-1. To the nth pixel cell PXLn. In this case, the n-th pixel cell PXLn-1 is precharged in a period corresponding to an effective charging period of the n-th scan pulse supplied to the n-th gate line. Accordingly, the n-th pixel cell PXLn-1 is applied in response to the first data signal Vdata1 supplied in a period corresponding to the effective charging period B of the n-th scan pulse Voutn-1. Fully charged to the target voltage, an image according to the first data signal Vdata1 is displayed.

Meanwhile, the n th pixel cell PXLn is precharged by the first data signal Vdata1.

In the second period T2, as shown in FIG. 2, the n−1 th scan pulse Voutn−1 and the n th scan pulse Voutn are simultaneously output. Thus, as shown in FIG. 3B, the n-th gate line GLn and the n-th +1 th gate line GLn + 1 are simultaneously driven. At this time, the second data signal Vdata2 having a positive polarity is supplied to the data line DLm. This second data signal Vdata2 is a data signal corresponding to the nth pixel cell PXLn.

Accordingly, the second data signal Vdata2 is connected to the n th pixel cell PXLn connected to the n th gate line GLn and the n th + connected to the n + 1 th gate line GLn + 1. It is simultaneously supplied to one pixel cell PXLn + 1. In this case, the n-th pixel cell PXLn is precharged in a period corresponding to the effective charging period B of the n-th scan pulse Voutn-1 supplied to the n-th gate line GLn-1. It is in a state. Accordingly, the n-th pixel cell PXLn is completely charged to a target voltage according to the second data signal Vdata2 supplied in the period corresponding to the effective charge period B of the n-th scan pulse Voutn. An image according to the second data signal Vdata2 is displayed.

The n + 1 th pixel cell PXLn + 1 is precharged by the second data signal Vdata2.

In the third period T3, as illustrated in FIG. 2, the n + 1th scan pulse Voutn + 1 and the nth + 2th scan pulse (not shown) are simultaneously output. Accordingly, as shown in FIG. 3C, the n + 1 th gate line GLn + 1 and the n + 2 th gate line are simultaneously driven. At this time, the third data signal Vdata3 having a negative polarity is supplied to the data line DLm. The third data signal Vdata3 is a data signal corresponding to the n + 1th pixel cell PXLn + 1.

Accordingly, the third data signal Vdata3 is connected to the n + 1 th pixel cell PXLn + 1 and the n + 2 th gate line connected to the driven n + 1 gate line GLn + 1. It is supplied to the n + 2th pixel cell simultaneously. In this case, the n + 1 th pixel cell PXLn + 1 is precharged in a period corresponding to the effective charging period B of the n th scan pulse Voutn supplied to the n th gate line GLn. Accordingly, the n + 1 th pixel cell PXLn + 1 is applied to the third data signal Vdata3 supplied in a period corresponding to the effective charging period of the n + 1 th scan pulses Voutn-1 to Voutn + 1. Accordingly, the battery is fully charged to the target voltage to display an image according to the third data signal Vdata3.

The n + 2 th pixel cell PXLn + 2 is precharged by the third data signal Vdata3.

As described above, each pixel cell PXLn-1 to PXLn + 1 is precharged according to the data signal supplied to the previous pixel cell, and then fully charged to the target voltage according to the corresponding data signal to display an image. However, since the data signal supplied during the precharge and the data signal supplied during the main charge have different polarities (that is, the data signal supplied during the precharge and the data signal supplied during the main charge are different from each other based on a common voltage. Since the pixel cells PXLn-1 to PXLn + 1 are charged with a voltage (pixel voltage; the difference voltage between the common voltage and the data signal) corresponding to the data signal, a large amount of time elapses. Accordingly, it is difficult for the pixel voltages of the pixel cells PXLn-1 to PXLn + 1 to be maintained at the target voltage within the effective charging period B. FIG. As a result, the image quality of the display device deteriorates.

For example, the n-th pixel cell PXLn is precharged according to the first polarity data signal Vdata1 and mainly charged according to the second polarity data signal Vdata2. In this case, the n-th pixel cell PXLn is finally charged with a positive voltage, and the n-th pixel cell PXLn is already charged with a negative voltage by the negative first data signal Vdata1. to be. Therefore, a long time is elapsed before the n-th pixel cell PXLn is charged with the positive voltage according to the second data signal Vdata2. Accordingly, it is difficult for the pixel voltage of the nth pixel cell PXLn to be maintained at the target voltage within the effective charging period B. FIG.

FIG. 4 is a diagram for describing a change in pixel voltage according to a change in polarity of the data voltage of FIG. 2. As shown in FIG. 4, a precharge period A of the nth scan pulse Voutn is shown. The data signal supplied in the period and the data signal supplied in the period corresponding to the effective charging section B have different polarities. As a result, it is difficult for the pixel voltages of the pixel cells PXLn-1 to PXLn + 1 to be maintained at the target voltage within the effective charging period B. FIG.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the period in which a data signal of the same polarity is supplied to the data line, at least two scan pulses are supplied to each gate line so that each pixel cell has the same polarity pixel. It is an object of the present invention to provide a display device that can be charged with a voltage.

According to an aspect of the present invention, a display device includes: a data line and a plurality of gate lines crossing each other; A plurality of pixel cells connected to the gate lines individually and commonly connected to the data lines; A data driver for supplying data signals having different polarities to the data lines; And a gate driver for supplying at least two scan pulses to each gate line to drive each gate line at least twice in a period where the polarities of the data signals supplied to the data lines are the same. It is done.

Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 5, a display device according to an exemplary embodiment of the present invention includes a display unit 500 for displaying an image, a data driver 502 for supplying a data signal to the display unit 500, and And a gate driver 501 for supplying at least two scan pulses to the display unit 500.

The display unit 500 may include a plurality of gate lines GL1 to GLn arranged in one direction and a plurality of data lines DL1 to DLm arranged to vertically cross the gate lines GL1 to GLn. And pixel cells PXL formed in each pixel region defined by each of the gate lines GL1 to GLn and each of the data lines DL1 to DLm. Hereinafter, the configuration of each pixel cell PXL will be described in more detail.

Although not shown in the drawings, each pixel cell PXL is a thin film transistor that receives a scan pulse from a corresponding gate line and switches a data signal from the corresponding data line, and a pixel electrode that receives a switched data signal from the thin film transistor. And a liquid crystal cell formed between the common electrode supplied with the common voltage and the pixel electrode and the common electrode to adjust the light transmittance according to the difference voltage (pixel voltage) between the data voltage and the common voltage.

On the other hand, at least two scan pulses output from the gate driver 501 are supplied to the respective gate lines. The data signal output from the data driver 502 is supplied to each data line.

Here, the scan pulse and the data signal will be described in more detail as follows.

FIG. 6 is a diagram illustrating a scan pulse supplied to each gate line of FIG. 5 and a data signal supplied to a first data line DL1.

As shown in FIG. 6, two types of scan pulses, namely, precharge scan pulses Vpre1 to Vpren and main charge scan pulses Vtg1 to Vtgn are supplied to each gate line GL1 to GLn. .

Each of the pre-charge scan pulses Vpre1 to Vpren is a signal for driving each gate line GL1 to GLn to precharge each pixel cell PXL connected to the gate lines GL1 to GLn. The scan pulse for the main charge is a signal for driving the gate lines GL1 to GLn to charge the pixel cells PXL connected to the gate lines GL1 to GLn to a target voltage.

 Here, the scan pulses Vpre1 to Vpren for each precharge are sequentially output, so that the gate lines GL1 to GLn are driven in turn.

That is, the second preliminary charging scan pulse Vpre2 is output by being delayed by a time corresponding to one horizontal period than the first preliminary charging scan pulse Vpre1, and the third preliminary charging scan pulse Vpre3 is outputted to the third preliminary charging scan pulse Vpre3. 2 The output pulse is delayed by a time corresponding to one horizontal period from the precharge scan pulse Vpre2, and the n-1 precharge scan pulse VPren-1 is scanned in the n-2 precharge scan. Output is delayed by one time period than pulse.

In addition, since the scan pulses Vtg1 to Vtgn for each main charge are also output in turn, each gate line GL1 to GLn is driven in turn.

That is, the second main charging scan pulse Vtg2 is output by being delayed by a time corresponding to one horizontal period than the first main charging scan pulse Vtg1, and the third main charging scan pulse Vtg3 is outputted as the second main charging scan pulse Vtg3. 2 is delayed by a time corresponding to one horizontal period than the scan pulse for the main charge (Vtg2), ..., the n-1 main charge scan pulse (Vtgn-1) is the scan for the n-2 main charge Output is delayed by one time period than pulse.

Here, each of the main charging scan pulses Vtg1 to Vtgn supplied to each of the gate lines GL1 to GLn is delayed by two horizontal periods than the preliminary charging scan pulses Vpre1 to Vpren.

That is, the first main charging scan pulse Vtg1 is output by being delayed by a time corresponding to two horizontal periods than the first preliminary charging scan pulse Vpre1, and the second main charging scan pulse Vtg2 is output. The second preliminary charging scan pulse Vpre2 is output by being delayed by a time corresponding to two horizontal periods, and the third main charging scan pulse Vtg3 is two horizontal periods longer than the third preliminary charging scan pulse Vpre3. The output is delayed by a time corresponding to ..., and the n-1 main charging scan pulse Vtgn-1 corresponds to two horizontal periods than the n-1 preliminary charging scan pulse Vpren-1. The n-th main charge scan pulse Vtgn is output by being delayed by a time corresponding to two horizontal periods than the n-th preliminary charge scan pulse Vpren.

Therefore, the kth (k is a natural number) gate line and the k + 2th gate line are simultaneously driven with each other. Specifically, one of the kth gate line and the k + 2th gate line is driven by the precharge scan pulse, and the other gate line is driven by the main charge scan pulse in the same period.

For example, in the third horizontal period T3, the first gate line GL1 and the third gate line GL3 are simultaneously driven. In this case, the first gate line GL1 is driven by the first main scan scan pulse Vtg1, and the third gate line GL3 is driven by the third preliminary scan pulse Vpre3.

In the fourth horizontal period T4, the second gate line GL2 and the fourth gate line GL4 are simultaneously driven. In this case, the second gate line GL2 is driven by the second main charging scan pulse Vtg2, and the fourth gate line GL4 is driven by the fourth preliminary charging scan pulse Vpre4.

The above-described scan pulse is output from the gate driver 501. For this operation, the gate driver 501 includes a shift register.

The shift register includes a plurality of stages (not shown) connected dependently to each other. Each stage is connected one to one to each gate line GL1 to GLn.

Each stage receives the precharge scan pulse and the main charge scan pulse from the previous stage, and outputs the delayed precharge scan pulse and the main charge scan pulse by a time corresponding to one horizontal period.

Here, since no stage exists in front of the first of the stages, the first stage is supplied with the first start pulse Vst1 and the second start pulse Vst2 from the outside, and the first stage is supplied with the first stage. The start pulse Vst1 and the second start pulse Vst2 are shifted and output so as to be delayed by a time corresponding to one horizontal period.

Here, the operation of the shift register in more detail as follows.

First, the first start pulse Vst1 is output from the timing controller in a period preceding the first horizontal period T1 by one horizontal time, that is, in the initial period. This first start pulse Vst1 is a start signal for outputting the scan pulse for the precharge.

This first start pulse Vst1 is supplied to the first stage. Then, the first stage shifts the first start pulse Vst1 and outputs the first pre-charge scan pulse Vpre1. That is, the first stage receives the first start pulse Vst1 in the initial period and outputs the first preliminary scan pulse Vpre1 in the first horizontal period T1. Then, the first preliminary charging scan pulse Vpre1 is supplied to the first gate line GL1 and the second stage in the first horizontal period T1.

Subsequently, the second stage receives the first preliminary charge scan pulse Vpre1 from the first stage, shifts it, and outputs the second preliminary charge scan pulse Vpre2. That is, the second stage receives the first preliminary charging scan pulse Vpre1 in the first horizontal period T1 and outputs the second preliminary charging scan pulse Vpre2 in the second horizontal period T2. In the second horizontal period T2, the second precharge scan pulse Vpre2 is supplied to the second gate line GL2 and the third stage.

Next, the third stage receives the second precharge scan pulse Vpre2 from the second stage, shifts it, and outputs the third precharge scan pulse Vpre3. That is, the third stage receives the second preliminary charging scan pulse Vpre2 in the second horizontal period T2 and outputs the third preliminary charging scan pulse Vpre3 in the third horizontal period T3. In the third horizontal period T3, the third precharge scan pulse Vpre3 is supplied to the third gate line GL3 and the fourth stage.

In this way, the remaining stages in turn output the precharge scan pulses.

Meanwhile, in the second horizontal period T2, the second start pulse Vst2 is output from the timing controller. This second start pulse Vst2 is a start signal for outputting the main pulse scan pulse. This second start pulse Vst2 is supplied to the first stage. Then, the first stage shifts the second start pulse Vst2 and outputs the first main scan scan pulse Vtg1. That is, the first stage receives the second start pulse Vst2 in the second horizontal period T2 and outputs the first main scan scan pulse Vtg1 in the third horizontal period T3. The first main charge scan pulse Vtg1 is supplied to the first gate line GL1 and the second stage in the third horizontal period T3.

Subsequently, the second stage receives the first main charging scan pulse Vtg1 from the first stage, shifts it, and outputs the second main charging scan pulse Vtg2. That is, the second stage receives the first main charging scan pulse Vtg1 in the third horizontal period T3 and outputs the second main scanning scan pulse Vtg2 in the fourth horizontal period T4. . In the fourth horizontal period T4, the second main charge scan pulse Vtg2 is supplied to the second gate line GL2 and the third stage.

Next, the third stage receives the second main charge scan pulse Vtg2 from the second stage, shifts it, and outputs the third main charge scan pulse Vtg3. That is, the third stage receives the second main charge scan pulse Vtg2 in the fourth horizontal period T4 and outputs the third main charge scan pulse Vtg3 in the fifth horizontal period T5. The third main charge scan pulse Vtg3 is supplied to the third gate line GL3 and the fourth stage in the fifth horizontal period T5.

In this manner, the remaining stages sequentially output the main pulse scan pulses.

That is, each stage sequentially outputs the pre-charge scan pulse and the main-charge scan pulse by the first start pulse Vst1 and the second start pulse Vst2 supplied in different periods.

Meanwhile, for this operation, the gate driver 501 may have two shift registers.

FIG. 7 is a diagram illustrating first and second shift registers included in the gate driver of FIG. 5.

That is, as shown in FIG. 7, the gate driver 501 sequentially outputs the first to nth pre-scan scan pulses Vpren in response to the first start pulse Vst1. ) And a second shift register 701b which sequentially outputs the first to nth main scan scan pulses Vtgn in response to the second start pulse Vst2.

Here, the first shift register 701a has stages as described above, and the second shift register 701b also has stages as described above. The first stage of the first shift register 701a is supplied with the first start pulse Vst1, and the first stage of the second shift register 701b is supplied with the second start pulse Vst2.

As described above, since the first start pulse Vst1 is output in the initial period and the second start pulse Vst2 is output in the second horizontal period T2, the first shift register 701a is It operates first and second shift register 701b operates later.

On the other hand, the polarity of the data signal is reversed every horizontal period. That is, as shown in FIG. 6, the data signals Vdata1, Vdata3, Vdata5, Vdata7, Vdata9, ..., Vdatam-1 exhibit positive polarity in the odd horizontal period, and the data in the even horizontal period. The signals Vdata2, Vdata4, Vdata6, Vdata8, ..., and Vdatam exhibit negative polarity.

Here, the data signals Vdata1 to Vdatam are output from the data driver 502, and the data driver 502 may have either a dot inversion method or a line inversion method.

First, the operation of the dot inversion type data driver 502 will be described.

The dot inversion data driver 502 supplies one horizontal line of data signals Vdata1 to Vdatam to all data lines every horizontal period, and the data driver 502 is provided between adjacent data lines. Supply data signals of different polarities. In addition, the data driver 502 outputs the data signal group supplied in the odd-numbered horizontal period and the data signal group supplied in the even-numbered horizontal period to have different polar patterns.

For example, the data driver 502 supplies a positive data signal to each odd data line and a negative data signal to an even data line in a first horizontal period T1 which is an odd horizontal period. . The data driver 502 supplies a negative data signal to each odd-numbered data line and a positive data signal to each even-numbered data line in the second horizontal period T2 which is the even-numbered horizontal period.

Accordingly, the pixel cells PXL adjacent in the vertical direction, the pixel cells PXL adjacent in the left and right directions, and the pixel cells PXL adjacent in the diagonal direction all exhibit different polarities.

Next, the operation of the line inversion type data driver 502 will be described.

The data driver 502 of the line inversion method divides one horizontal line of data signals Vdata1 to Vdatam into all data lines every horizontal period, and the data driver 502 is identical to all data lines. Supply a polarity data signal. In addition, the data driver 502 outputs the data signal group supplied in the odd-numbered horizontal period and the data signal group supplied in the even-numbered horizontal period to have different polar patterns.

For example, the data driver 502 supplies a positive data signal to all data lines in the first horizontal period T1, which is the odd horizontal period. The data driver 502 supplies a negative data signal to all data lines in the second horizontal period T2 which is the even-numbered horizontal period.

Accordingly, the pixel cells PXL adjacent to each other in the vertical direction have different polarities.

In the present invention, any one of the above-described dot inversion data driver 502 and line inversion data driver 502 can be used.

The operation of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above is as follows.

8A to 8F are diagrams for describing operations of the pixel cells PXL included in the portion C of FIG. 5 for each horizontal period.

In the first horizontal period T1, as illustrated in FIG. 6, the first preliminary charge scan pulse Vpre1 and the first polarity first data signal Vdata1 are output.

As shown in FIG. 8A, the first preliminary charge scan pulse Vpre1 is supplied to the first gate line GL1, and the positive first data signal Vdata1 is applied to the first data line DL1. Supplied.

Then, the first pixel cell PXL1 connected to the first gate line GL1 and the first data line DL1 may receive the first data having the positive polarity in response to the first preliminary charge scan pulse Vpre1. The signal Vdata1 is supplied. Therefore, the first pixel cell PXL1 is precharged with a positive voltage in the first horizontal period T1.

The first data signal Vdata1 having a positive polarity is a dummy data signal, and precharges the first pixel cell PXL1 with a positive voltage.

Subsequently, in the second horizontal period T2, as shown in FIG. 6, the second preliminary charge scan pulse Vpre2 and the negative second data signal Vdata2 are output.

As shown in FIG. 8B, the second precharge scan pulse Vpre2 is supplied to the second gate line GL2, and the negative second data signal Vdata2 is connected to the first data line DL1. Is supplied.

Then, the second pixel cell PXL2 connected to the second gate line GL2 and the first data line DL1 has the second data of the negative polarity in response to the first preliminary scan pulse Vpre1. The signal Vdata2 is supplied. Therefore, the second pixel cell PXL2 is precharged with a negative voltage in the second horizontal period T2.

Here, the negative second data signal Vdata2 is a dummy data signal, and precharges the second pixel cell PXL2 with a negative voltage.

Next, in the third horizontal period T3, as shown in FIG. 6, the third preliminary charge scan pulse Vpre3, the first main charge scan pulse Vtg1, and the positive third data signal ( Vdata3) is output. The positive third data signal Vdata3 is a signal for displaying an image in the first pixel cell PXL1.

As shown in FIG. 8C, the third precharge scan pulse Vpre3 is supplied to the third gate line GL3, and the first main scan scan pulse Vtg1 is the first gate line GL1. The third data signal Vdata3 having the positive polarity is supplied to the first data line DL1.

Accordingly, the third gate line GL3 and the first gate line GL1 are simultaneously driven in the third horizontal period T3.

Then, the third pixel cell PXL3 connected to the third gate line GL3 and the first data line DL1 may receive the third data signal having the positive polarity in response to the third preliminary scan pulse Vpre3. It is supplied with (Vdata3). Therefore, in the third horizontal period T3, the third pixel cell PXL3 is precharged with a positive voltage.

In addition, the first pixel cell PXL1 connected to the first gate line GL1 and the first data line DL1 may respond to the third data signal Vdata3 in response to the first main scan scan pulse Vtg1. Is supplied). Therefore, in the third horizontal period T3, the first pixel cell PXL1 is fully charged with a positive voltage and displays an image according to the third data signal Vdata3.

Next, in the fourth horizontal period T4, as shown in FIG. 6, the fourth preliminary charge scan pulse Vpre4, the second main charge scan pulse Vtg2, and the negative fourth data signal. (Vdata4) is output. The negative fourth data signal Vdata4 is a signal for displaying an image in the second pixel cell PXL2.

As shown in FIG. 8D, the fourth preliminary charging scan pulse Vpre4 is supplied to the fourth gate line GL4, and the second main charging scan pulse Vtg2 is the second gate line GL2. The fourth data signal Vdata4 of the negative polarity is supplied to the first data line DL1.

Accordingly, the fourth gate line GL4 and the second gate line GL2 are simultaneously driven in the fourth horizontal period T4.

Then, the fourth pixel cell PXL4 connected to the fourth gate line GL4 and the first data line DL1 has the fourth data having the negative polarity in response to the fourth precharge scan pulse Vpre4. The signal Vdata4 is supplied. Therefore, in the fourth horizontal period T4, the fourth pixel cell PXL4 is precharged with a negative voltage.

In addition, the second pixel cell PXL2 connected to the second gate line GL2 and the first data line DL1 has a negative fourth data signal in response to the second main scan scan pulse Vtg2. It is supplied with (Vdata4). Therefore, in the fourth horizontal period T4, the second pixel cell PXL2 is fully charged with a negative voltage and displays an image according to the fourth data signal Vdata4.

Next, in the fifth horizontal period T5, as illustrated in FIG. 6, the fifth preliminary charge scan pulse Vpre5, the third main charge scan pulse Vtg3, and the fifth polarity fifth data signal ( Vdata5) is output. The fifth data signal Vdata5 having the positive polarity is a signal for displaying an image in the third pixel cell PXL3.

As shown in FIG. 8E, the fifth precharge scan pulse Vpre5 is supplied to the fifth gate line GL5, and the third main scan scan pulse Vtg3 is the third gate line GL3. The fifth data signal Vdata5 is supplied to the first data line DL1.

Accordingly, the fifth gate line GL5 and the third gate line GL3 are simultaneously driven in the fifth horizontal period T5.

Then, the fifth pixel cell PXL5 connected to the fifth gate line GL5 and the first data line DL1 may receive the fifth data signal having the positive polarity in response to the fifth precharge scan pulse Vpre5. It is supplied with (Vdata5). Therefore, in the fifth horizontal period T5, the fifth pixel cell PXL5 is precharged with a positive voltage.

In addition, the third pixel cell PXL3 connected to the third gate line GL3 and the first data line DL1 may have a positive fifth data signal in response to the third main scan scan pulse Vtg3. Vdata5). Therefore, in the fifth horizontal period T5, the third pixel cell PXL3 is fully charged with a positive voltage and displays an image according to the fifth data signal Vdata5.

Next, in the sixth horizontal period T6, as shown in FIG. 6, the sixth precharge scan pulse Vpre6, the fourth main scan scan pulse Vtg4, and the negative sixth data signal. (Vdata6) is output. Herein, the negative sixth data signal Vdata6 is a signal for displaying an image in the fourth pixel cell PXL4 (PXL).

As shown in FIG. 8F, the sixth precharge scan pulse Vpre6 is supplied to the sixth gate line GL6, and the fourth main scan scan pulse Vtg4 is the fourth gate line GL4. The sixth data signal Vdata6 is supplied to the first data line DL1.

Accordingly, the sixth gate line GL6 and the fourth gate line GL4 are simultaneously driven in the sixth horizontal period T6.

Then, the sixth pixel cell PXL6 connected to the sixth gate line GL6 and the first data line DL1 receives the sixth data of the negative polarity in response to the sixth preliminary scan pulse Vpre6. The signal Vdata6 is supplied. Therefore, in the sixth horizontal period T6, the sixth pixel cell PXL6 is precharged with a negative voltage.

In addition, the fourth pixel cell PXL4 connected to the fourth gate line GL4 and the first data line DL1 has a negative sixth data signal in response to the fourth main scan scan pulse Vtg4. It is supplied with (Vdata6). Therefore, in the sixth horizontal period T6, the fourth pixel cell PXL4 is fully charged with a negative voltage and displays an image according to the sixth data signal Vdata6.

In this manner, the remaining gate lines GL7 to GLn are sequentially driven, and each pixel cell PXL connected to the gate lines GL7 to GLn is charged.

As can be seen from the above description, each pixel cell PXL is precharged and fully charged with the voltage of the same polarity. Therefore, the charging time of each pixel cell PXL is shortened, whereby the pixel voltage of each pixel cell PXL can be maintained at the target voltage within the effective charging period.

Meanwhile, the precharge scan pulses supplied to the same gate line may be output with a delay of four horizontal periods than the main charge scan pulses.

FIG. 9 is a diagram illustrating waveforms of another scan pulse supplied to each gate line of FIG. 5.

As shown in FIG. 9, the first main charging scan pulse Vtg1 is delayed by a time corresponding to four horizontal periods than the first preliminary charging scan pulse Vpre1, and the second main charging scan The pulse Vtg2 is output by being delayed by a time corresponding to four horizontal periods than the second preliminary charging scan pulse Vpre2, and the third main charging scan pulse Vtg3 is output by the third preliminary charging scan pulse Vpre3. Is delayed by a time corresponding to four horizontal periods, and the n-th main charging scan pulse Vtgn-1 is greater than the n-th preliminary charging scan pulse Vpren-1. The output pulse is delayed by a time corresponding to two horizontal periods, and the n-th main charge scan pulse Vtgn is output by being delayed by a time corresponding to four horizontal periods by the n th precharge scan pulse Vpren.

Therefore, the kth (k is a natural number) gate line and the k + 4th gate line are simultaneously driven with each other. Specifically, during the same period, one of the kth gate line and the k + 4th gate line is driven by the precharge scan pulse, and the other gate line is driven by the main charge scan pulse.

For example, in the fifth horizontal period T5, the first gate line GL1 and the fifth gate line GL5 are simultaneously driven. In this case, the first gate line GL1 is driven by the first main scan scan pulse Vtg1, and the fifth gate line GL5 is driven by the fifth precharge scan pulse Vpre5.

In the sixth horizontal period T6, the second gate line GL2 and the sixth gate line GL6 are simultaneously driven. In this case, the second gate line GL2 is driven by the second main charge scan pulse Vtg2, and the sixth gate line GL6 is driven by the sixth preliminary charge scan pulse Vpre6.

Here, as the difference between the time point at which the preliminary charge scan pulse is output and the time point at which the main charge scan pulse is output, the image according to the data signal supplied to the front end pixel instead of the data signal corresponding to each pixel cell ( The wrong display time becomes longer.

Therefore, it is preferable to make the difference between the output time of the precharge scan pulse and the output time of the main charge scan pulse less than four horizontal periods.

On the other hand, two or more pre-charge scan pulses supplied to one gate line may be used.

FIG. 10 is a view illustrating waveforms of another scan pulse supplied to each gate line of FIG. 5.

As shown in FIG. 10, each of the gate lines GL1 to GLn is supplied with a scan pulse for primary precharge, a scan pulse for secondary precharge, and a scan pulse for main charge.

At this time, the scan pulses Vpre1 to Vpren for each primary precharge are sequentially output. That is, the second primary precharge scan pulse Vpre2 is output by being delayed by a time corresponding to one horizontal period than the first primary precharge scan pulse Vpre1, and the third primary precharge scan pulse Vpre3. Is delayed by a time corresponding to one horizontal period than the second primary precharge scan pulse Vpre2, and is output. The n-1 primary precharge scan pulse Vpren-1 is nth. -2 The delay time is output by one horizontal period than the primary precharge scan pulse.

In addition, scan pulses Vpre1 'to Vpren' for each secondary precharge are sequentially output. That is, the second secondary precharge scan pulse Vpre2` is output by being delayed by a time corresponding to one horizontal period than the first secondary precharge scan pulse Vpre1`, and the third secondary precharge scan pulse ( Vpre3`) is output by being delayed by a time corresponding to one horizontal period than the second secondary precharge scan pulse Vpre2`, and ..., n-1 secondary precharge scan pulse Vpren-1`. ) Is delayed by the time corresponding to one horizontal period than the n-2 secondary precharge scan pulse and is output.

In addition, scan pulses Vtg1 to Vtgn for each main charging are output in turn. That is, the second main charging scan pulse Vtg2 is output by being delayed by a time corresponding to one horizontal period than the first main charging scan pulse Vtg1, and the third main charging scan pulse Vtg3 is outputted as the second main charging scan pulse Vtg3. 2 is delayed by a time corresponding to one horizontal period than the scan pulse for the main charge (Vtg2), ..., the n-1 main charge scan pulse (Vtgn-1) is the scan for the n-2 main charge Output is delayed by one time period than pulse.

Here, each of the main charging scan pulses Vtg1 to Vtgn supplied to each of the gate lines GL1 to GLn is delayed by a time corresponding to two horizontal periods than the second preliminary charging scanning pulses Vpre1 to Vpren. Is output. That is, the first main charging scan pulse Vtg1 is output by being delayed by a time corresponding to two horizontal periods than the first secondary preliminary scanning pulse Vpre1 ′, and the second main charging scan pulse Vtg1 is outputted. Vtg2 is output by being delayed by a time corresponding to two horizontal periods than the second secondary precharge scan pulse Vpre2 ', and the third main charge scan pulse Vtg3 is outputted as a third secondary precharge scan pulse (Vtg3). Vpre3`) is output by being delayed by a time corresponding to two horizontal periods, and ..., the n-1th main charging scan pulse Vtgn-1 is the n-1th secondary preliminary scanning pulse Vpren- 1 ') is delayed and output for two horizontal periods, and the scan pulse Vtgn for the nth main charge has a time corresponding to two horizontal periods for the scan pulse Vpren` for the nth secondary precharge. The output is delayed.

In addition, each of the secondary precharge scan pulses Vpre1` to Vpren` supplied to each gate line GL1 to GLn is delayed by a time corresponding to two horizontal periods than the scan pulses Vpre1 to Vpren each primary precharge. And output. That is, the first secondary precharge scan pulse Vpre1 ′ is output after being delayed by a time corresponding to two horizontal periods than the first primary precharge scan pulse Vpre1, and the second secondary precharge scan pulse Vpre1 ′. Vpre2` is output by being delayed by a time corresponding to two horizontal periods than the second primary precharge scan pulse Vpre2, and the third secondary precharge scan pulse Vpre3` is output to the third primary precharge. The output pulse is delayed by a time corresponding to two horizontal periods from the scan pulse Vpre3, and the scan pulse Vpren-1 ′ of the n-th secondary precharge is scanned in the n-1 primary precharge. The output pulse is delayed by a time corresponding to two horizontal periods than the pulse VPren-1, and the scan pulse Vpren` for the nth second preliminary charging is performed in two horizontal periods than the scan pulse Vpren for the nth primary precharge. The output is delayed by the corresponding time.

Therefore, the kth (k is a natural number) gate line and the k + 2th gate line are simultaneously driven with each other. Specifically, one of the k th gate line and the k + 2 th gate line is driven by the secondary precharge scan pulse and the other gate line is driven by the primary precharge scan pulse. In the second same period, one of the k th gate line and the k + 2 th gate line is driven by the first preliminary charging scan pulse, and the other one is driven by the main charging scan pulse.

For example, in the third horizontal period T3, the first gate line GL1 and the third gate line GL3 are simultaneously driven. In this case, the first gate line GL1 is driven by the scan pulse Vpre1 ′ for the first secondary precharge, and the third gate line GL3 is driven by the scan pulse Vpre3 for the third primary precharge. do.

The first gate line GL1 and the third gate line GL3 are simultaneously driven in the fifth horizontal period T5. In this case, the first gate line GL1 is driven by the first main scan scan pulse Vtg1, and the third gate line GL3 is driven by the third secondary preliminary scan pulse Vpre3 ′. .

Similarly, in the fourth horizontal period T4, the second gate line GL2 and the fourth gate line GL4 are simultaneously driven. In this case, the second gate line GL2 is driven by the scan pulse Vpre2 ′ for the second secondary precharge, and the fourth gate line GL4 is driven by the scan pulse Vpre4 for the fourth primary precharge. do.

The second gate line GL2 and the fourth gate line GL4 are simultaneously driven in the sixth horizontal period T6. In this case, the second gate line GL2 is driven by the second main charging scan pulse Vtg2, and the fourth gate line GL4 is driven by the fourth secondary preliminary scanning pulse Vpre4 ′. .

Accordingly, each pixel cell PXL is stably charged through two precharges.

Of course, each pixel cell PXL may be precharged three or more times by increasing the number of scan pulses for precharging supplied to the gate lines GL1 to GLn.

FIG. 11 is a diagram illustrating a change in pixel voltage according to a change in polarity of the data voltage of FIG. 6. As shown in FIG. 6, the data signal supplied to the nth pixel cell PXLn during the preliminary charging period is illustrated in FIG. The polarity of the data signal supplied to the nth pixel cell PXLn is the same between the polarity and the main charging period. That is, the data signals supplied to the preliminary charging section and the main charging section are both positive voltages.

Therefore, the pixel voltage of the nth pixel cell PXLn sufficiently reaches the target voltage within the effective charging period.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the display device according to the present invention has the following effects.

The display device according to the present invention supplies at least two types of scan pulses (a precharge scan pulse and a main charge scan pulse) to each gate line. At this time, the two types of scan pulses are supplied to the respective gate lines when a data signal of the same polarity is supplied to the data lines. Therefore, each pixel cell is charged at least twice with a data signal of the same polarity. Accordingly, the display device of the present invention can reach the pixel voltage of each pixel cell to the target voltage within the effective charging period.

Claims (15)

A data line and a plurality of gate lines crossing each other; A plurality of pixel cells connected to the gate lines individually and commonly connected to the data lines; A data driver for supplying data signals having different polarities to the data lines; And, And a gate driver for supplying at least two scan pulses to each gate line to drive each gate line at least twice in a period where the polarities of the data signals supplied to the data lines are the same. Device. The method of claim 1, The data driver, And a positive data signal is supplied to the data line in an odd period of successive periods, and a negative data signal is supplied to the data line in an even period. The method of claim 2, Each scan pulse output from the gate driver is of two types, each of which A pre-charge scan pulse for precharging pixel cells connected to the gate lines by driving the gate lines; And, And a scan pulse for main charging for driving the respective gate lines to charge pixel cells connected to the gate lines to a target voltage. The method of claim 3, wherein The gate driver, Supplying the pre-charge scan pulses to the respective gate lines sequentially from the first period, and sequentially supplying the main charge scan pulses to the respective gate lines from the second k-1 period (k is a natural number greater than 1). Display device characterized in that. The method of claim 4, wherein And a pre-charge scan pulse supplied to each gate line is delayed by a time corresponding to a period longer than the pre-charge scan pulse supplied to the previous gate line. The method of claim 4, wherein A display device for main charge scanning pulses supplied to each gate line is delayed by a time corresponding to a period longer than the main charge scanning pulse supplied to the previous gate line. The method of claim 4, wherein And the gate driver sequentially supplies the main charge scan pulse to each gate line from the third period. The method of claim 7, wherein The main charging scan pulse supplied to the same gate line is delayed by a time corresponding to two periods than the preliminary charging scan pulse supplied to the same gate line and output. The method of claim 4, wherein And the gate driver sequentially supplies the main charge scan pulse to each gate line from the fifth period. The method of claim 9, And the main charging scan pulses supplied to the same gate line are delayed by a time period corresponding to four periods from the preliminary charging scan pulses supplied to the same gate line. The method of claim 2, Each scan pulse output from the gate driver is of three types, each of which Primary precharge scan pulses for driving each gate line to precharge the pixel cells connected to the gate lines; A secondary precharge scan pulse for driving the respective gate lines to secondary precharge the pixel cells connected to the gate lines; And, And a scan pulse for main charging for driving the respective gate lines to charge pixel cells connected to the gate lines to a target voltage. The method of claim 11, The gate driver, The first preliminary charge scan pulses are sequentially supplied to each gate line from the first period, and the second preliminary charge scan pulses are sequentially supplied to each gate line from the second k-1 (k is a natural number greater than 1). And sequentially supplying the main charging scan pulses to the respective gate lines from the second p-1 (p is a natural number greater than 2) period. 13. The method of claim 12, And a primary precharge scan pulse supplied to each gate line is delayed for a period of time longer than the primary precharge scan pulse supplied to the previous gate line. 13. The method of claim 12, And a secondary precharge scan pulse supplied to each gate line is delayed for a period of time longer than the second precharge scan pulse supplied to the previous gate line. 13. The method of claim 12, A display device for main charge scanning pulses supplied to each gate line is delayed by a time corresponding to a period longer than the main charge scanning pulse supplied to the previous gate line.

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