KR101096088B1 - Digital-Analog Converter using resistor-string - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter using a resistor row. In particular, the resistor row of the digital-to-analog converter is designed by dividing the resistor row into a coarse resistor row and a fine resistor row, thereby reducing chip size and power consumption. There is a purpose. In order to achieve the above object, the present invention provides a decoder (221) (231) for decoding the most significant bit (MSB) and the least significant bit (LSB), respectively, and an analog signal corresponding to the output signal of the decoder (221). A coarse resistor row 222, a fine resistor row 232 for generating an analog signal corresponding to the output signal of the decoder 231, and the first and second resistor rows 222 ( And a reference current generator 210 for applying a bias current Iref to 232 and an output buffer 240 for outputting an analog signal generated by the first and second resistor lines 222 and 232. It is characterized by.

Resistive Column, Reference Current, Digital-to-Analog Converter

Description

Digital-Analog Converter using resistor-string}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuit design, and more particularly, to a digital-to-analog converter using resistance trains.

Digital-to-analog converters are devices that convert digital signals to analog signals and are widely used in almost all electronic devices.

1 is a block diagram of a conventional resistor-string digital-to-analog converter (DAC).

Existing digital thermal resistance of the FIG. 1-a to-analog converter is a single resistance heating structure, if designed to be applied to the input of N- bits, and is configured to include a 2 ^N resistors and, 2 ^N switches and, N- bit decoder.

Thus, conventional resistive digital-to-analog converters have increased input bits.

The need for more resistors, switches and decoders not only takes up a lot of chip area, but also increases power consumption during circuit operation.

In addition, the conventional resistance-to-digital digital-to-analog converter has a problem that it is difficult to configure a high-speed and high-resolution circuit because the time to stabilize the voltage in a large number of resistance trains becomes long.

Recently, the digital-to-analog converter has been applied to many applications because of its simple configuration, high accuracy and linearity, and the high integration has made the chip size smaller, so that the overall size of the digital-to-analog converter has to be reduced for efficient area utilization. There is a need.

Accordingly, in order to solve the above problems, the present invention is designed by dividing the resistance column of the digital-analog converter into a coarse resistor string and a fine resistor string to reduce the number of components to reduce chip size and power consumption. Its purpose is to provide a digital-to-analog converter.

According to an aspect of the present invention, a first resistor string for generating an analog signal corresponding to an input of a most significant bit, a second resistor string for generating an analog signal corresponding to an input of a least significant bit, and the first And a reference current generator for applying a bias current to the second resistor row, and an output buffer for outputting an analog signal corresponding to the voltage generated in the first and second resistor rows.

The resistors provided in the first and second resistor columns are 2 ^M and 2 ^L , where N = M + L, respectively, assuming an N-bit digital-to-analog converter.

The reference current generator is a current source, characterized in that configured to generate a bias current by the mirror circuit.

The digital-to-analog converter of the present invention configured as described above has the effect of reducing the circuit area and improving the operation speed by reducing the number of resistors, switches and decoders by employing a coarse-fine resistive string structure.

In addition, the present invention is to shorten the time to stabilize the voltage in the resistance train than conventional to facilitate the construction of a high-speed and high-resolution digital-to-analog converter as well as to reduce the power consumption.

Therefore, the digital-to-analog converter proposed in the present invention can be applied to many applications to reduce the mounting area of the device and to enable high-speed operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Specific details, such as process flow, are set forth in the following description and drawings to aid a more general understanding of the invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

2 is a block diagram of a DAC using a coarse resistance string and a fine resistance string proposed as an embodiment of the present invention. As shown therein, decoders 221 and 231 for decoding the most significant bit and the least significant bit, respectively, are shown. ), A coarse resistance column 222 for generating an analog signal corresponding to the output signal of the decoder 221, and a fine for generating an analog signal corresponding to the output signal of the decoder 231. A reference current generator 210 for applying a bias current Iref to the resistor lines 232, the first and second resistor lines 222 and 232, and the first and second resistor lines 222. And an output buffer 240 for outputting an analog signal corresponding to the voltages Vc and Vf generated at 232.

The coarse-fine resistive string structure as shown in FIG. 2 has a smaller structure than the single resistive string structure of FIG. 1. Assuming that this is a N-bit digital-to-analog converter, a single resistor string uses 2 ^N resistors, but a coarse resistor string requires 2 ^M resistors and a fine resistor string requires 2 ^L resistors. . Here, 'N = M + L'.

A switch is connected in parallel to each of the resistors provided in the resistor rows 222 and 232. Therefore, the switch needs as many as the number of resistors provided. In other words, the number of resistors and switches is 2 ^{N in the} single resistor string structure, and the number of resistors and switches is 2 ^M +2 ^{L in the} coarse-fine resistor string structure.

As shown in FIG. 2, the N-bit decoder is used in the single resistor string structure, but the M-bit decoder 221 and the L-bit decoder 231 are used in the embodiment of the present invention in which the coarse-fine resistor string structure is applied. Doing.

At this time, the coarse resistance string 222 generates an analog signal Vc corresponding to the output signal of the decoder 221 receiving the most significant bit MSB, and the fine resistance string 232 inputs the least significant bit LSB. An analog signal Vf corresponding to the output signal of the receiving decoder 231 is generated.

In addition, since the analog signal generated by the resistor rows 222 and 232 is a voltage, the reference current generated by the reference current generator 210 is applied to the resistor rows 222 and 232.

Accordingly, when the voltages Vc and Vf generated by the resistor lines 222 and 232 are applied to the output buffer 240, the output buffer 240 is added to the sum of the voltages Vc and Vf. It will output the corresponding analog signal.

Meanwhile, the operation of the reference current generator 210 proposed in the embodiment of the present invention will be described with reference to FIG. 3.

FIG. 3 is a circuit diagram of the reference current generating unit 210. As shown therein, a PMOS transistor MP1 (MP2), an NMOS transistor NM1, and a resistor Rd between the voltage terminal Vdd and the ground terminal. Are sequentially connected, the PMOS transistors MP3 and MP4 are sequentially connected to the voltage terminal Vdd, and are connected to the resistor lines 222, and the gate terminals of the PMOS transistors MP1 and MP3 are connected. It is connected to the connection point of the PMOS transistor MP2 and the NMOS transistor NM1, the bias voltage Vbias1 is applied to the gate terminal of the PMOS transistor MP2 (MP4), and the input signal Vin is positive ( The output terminal of the amplifier OP1, which is applied to the input terminal of +) and whose negative input terminal is connected to the connection point of the resistor Rd and the NMOS transistor NM1, has a gate terminal of the NMOS transistor NM1. Connect to and configure.

The bias current I _BIAS , which is a reference current generated by the reference current generator 210 of the configuration and applied to the resistor row 222, is generated by a mirror circuit composed of PMOS transistors MP1 to MP3. At this time, in order to reduce the magnitude of the bias current, the PMOS transistors MP1 and MP3 are formed at a ratio of 1: β, so that the currents in each of the PMOS transistors MP1 and MP3 are also generated at a ratio of 1: β. do.

In addition, in order to increase the accuracy of the reference current generator 210, the resistor R _D uses the same resistor as that used in the resistor columns 222 and 232.

In addition, the effect of the process, voltage, and temperature change of the resistors used in the resistor rows 222 and 232 is equalized to the reference current, and the same resistor is used in the reference current generator 210, thereby suggesting an embodiment of the present invention. It ensures that the output voltage of the digital-to-analog converter is not affected by process, voltage and temperature changes.

On the other hand, the resistor lines 222 and 232 divide and generate output voltages corresponding to the output signals of the reference current Ibias and the decoders 221 and 231.

That is, the conventional single resistor string structure generates an output voltage by dividing the reference voltage V _REF by the number of resistors, but the coarse-fine resistor string structure proposed in the embodiment of the present invention uses the reference current I _REF . Generate the output voltage.

At this time, the output voltage (V _F ) of the resistor string 232 is V _F = I _REF × R _F × i (i = 0 ~ 2 ^L-1 ), and the output voltage (V _C ) of the resistor string 222 is V _C = I _REF x R _C xj (j = 0-2 ^M-1 ).

Therefore, the final output voltage which is output from the output buffer (240) (V _OUT) is output voltage (V _C of the output voltage (V _F) and the resistance heat 222 of the resistance heat 232 as shown in Equation 1 below ) Is the sum of

V_OUT = V_F+ V_C

= I _REF × R _F × i + I _REF × R _C × j

= I _REF × (R _F × i + 2 ^L × R _F × j)

= I _REF × R _F × (i + 2 ^L × j)

= I _REF × R _F × k (for k = 0 ~ 2 ^N -1)

Referring to Equation 1, it can be seen that the final output voltage V _OUT by the resistor rows 222 and 232 is the same as the final output of the conventional single resistor string structure of FIG. 1.

In addition, if the number of bits of the digital-to-analog converter proposed in the embodiment of the present invention is selected as 'N', the number of M-bits of the coarse resistor string 222 and the number of L-bits of the fine resistor string 232 are correspondingly selected. Should be. 4 illustrates the number of resistors required for the digital-to-analog converter proposed in the embodiment of the present invention according to the bit number selection of the fine resistor string 232 in the embodiment of the present invention.

1 is a block diagram of a digital-analog converter using a conventional resistance string.

Figure 2 is a block diagram of a DAC using a coarse resistance heat and fine resistance heat proposed in an embodiment of the present invention.

3 is a circuit diagram of a reference current generator of FIG. 2.

FIG. 4 is a graph showing the number of resistors required for the DAC according to the number of bits of the fine resistor string in FIG. 2. FIG.

* Explanation of Signs of Major Parts of Drawings *

210: reference current generator 221, 231: decoder

222,232: Resistance column 240: Output buffer

MP1 to MP4: PMOS transistor NM1: NMOS transistor

OP1: Amplifier

Claims (6)

A first resistor string generating an analog signal corresponding to an input of a most significant bit (MSB); A second resistor string for generating an analog signal corresponding to an input of a least significant bit (LSB); A reference current generator for applying a bias current to the first and second resistor rows; An output buffer configured to output an analog signal corresponding to the voltage generated in the first and second resistor columns; The reference current generating unit, A first PMOS transistor having a source connected to the voltage terminal Vdd; A second PMOS transistor having a source connected to a drain of the first PMOS transistor and having a bias voltage Vbias1 applied to a gate thereof; An NMOS transistor whose drain is connected to the drain of the second PMOS transistor; A resistor (Rd) having one side connected to a source of the NMOS transistor and the other side connected to a ground terminal; A third PMOS transistor having a source connected to the voltage terminal Vdd and a gate connected to the gate of the first PMOS transistor; A fourth PMOS transistor having a source connected to the drain of the third PMOS transistor and having a bias voltage Vbias1 applied to a gate; And An input signal Vin is applied to a positive input terminal, a negative input terminal is connected between the NMOS transistor and a resistor Rd, and an output terminal is connected to a gate of the NMOS transistor. And an amplifier, wherein a connection node connected to the second PMOS transistor and the NMOS transistor is connected to a connection node connected to a gate of the first PMOS transistor and a gate of the third PMOS transistor. Digital-to-analog converter using a resistor row. The method of claim 1, Assuming that the first and second resistor columns are N-bit digital-to-analog converters, the resistors are composed of 2 ^M and 2 ^L resistors, where N = M + L, respectively. Analog converter. delete delete delete The method of claim 1, wherein the resistor Rd is A resistor configured as the resistor employed in the first and second resistor rows, so as to generate a reference current irrespective of the processor, voltage and temperature changes, digital-to-analog converter using a resistor row.

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