KR101038355B1 - Flash memory device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a flash memory device and a method of manufacturing the same, which can improve the interference phenomenon even if the gap between the cells is narrowed and to secure the distance between the tunnel insulating film and the control gate.

The present invention forms a groove in the dielectric film formed on the device isolation layer to form a control gate to the trench of the device isolation layer exposed through the groove, thereby lowering the parasitic capacitance between the floating gates to reduce the interference effect between adjacent cells. The present invention relates to a flash memory device capable of securing a distance between a tunnel insulating film and a control gate by improving an interference effect and forming a relatively high effective field oxide height (EFH), and a method of manufacturing the same.

Flash Memory, Dielectric Separation, Interference, Cycling Threshold Voltage Shift

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same. In particular, the present invention relates to a flash memory device and a method for manufacturing the same, which can improve the interference phenomenon even when the gap between the cells is narrowed and to secure the distance between the tunnel insulating film and the control gate. It is about.

The cell array of NAND flash memory devices includes a string structure. The string structure includes a drain select transistor having a drain connected to a bit line, a source select transistor having a source connected to a common source line, a plurality of memory cells connected in series between the drain select transistor and the source select transistor. These string structures are formed in parallel, and electrically separated from each other by the boundary of the device isolation layer to form a plurality of string structures. In string structures formed in parallel, the gates of the drain select transistors are connected to become a drain select line, the gates of the source select transistors are connected to be a source select line, and the gates of the memory cells are connected in parallel to each other, so that word lines do. The gate connected by the drain select line, the word line and the source select line is formed in a stack-type structure in which a floating gate, a dielectric film, and a control gate are stacked. The stacked gate is formed on the semiconductor substrate with a tunnel insulating film interposed therebetween. The drain select line, the word line, and the source select line are formed by connecting control gates among stacked gates.

The spacing between the string structures described above is narrowing along with high integration of flash devices. Accordingly, since the intervals of cells included in different strings are narrowed, an interference phenomenon occurs in which a state of a cell adjacent thereto changes due to an operation of an arbitrary cell. That is, the interference effect means that when the second cell adjacent to the first cell to be read is programmed, the threshold voltage of the first cell when the first cell is read due to a capacitance effect caused by the charge change of the floating gate of the second cell. It refers to a phenomenon in which a threshold voltage higher than the threshold voltage (Vt) is read, and the charge of the floating gate of the read cell does not change, but the state of the actual cell is distorted due to the change of the state of the adjacent cell. This interference effect causes the state of the cell to change, which results in an increase in the defective rate resulting in a lower yield. Therefore, minimizing the interference effect may be effective to keep the state of the cell constant.

Recently, in order to improve interference between cells, a method of forming a device isolation layer 17 having wing spacers W formed on sidewalls of the tunnel insulation layer 13 has been proposed, as shown in FIG. 1. . The wing spacer W is formed by lowering the effective field height (EFH) at the center portion of the surface of the device isolation film 17 than the device isolation film 17 formed on the sidewall of the tunnel insulating film 13. Due to the formation of the wing spacers W, the surface of the device isolation layer 17 is formed in a “U” shape. Accordingly, the surface of the dielectric film 19 formed on the device isolation layer 17 may also be formed in a “U” shape, and the control gate 21 formed on the surface of the “U” shaped dielectric film 19. ) May be deeply formed between the floating gates 15. As such, the control gate 21 formed between the floating gates 15 may improve inter-cell interference.

However, as described above, when the effective field height of the surface center portion of the device isolation layer 17 is lowered, the distance between the tunnel insulation layer 13 and the control gate 21 becomes shorter, and thus the cycling threshold voltage shifting of the tunnel insulation layer 13 is performed. Vt shift) may increase to deteriorate the characteristics of the tunnel insulating layer 13.

On the other hand, when the spacing between the floating gates 15 becomes narrow due to the high integration of the devices, and thus the spacing between the wing spacers W of the device isolation layer 17 becomes narrow, the dielectric film 19 fills the gaps between the wing spacers W. can do. As a result, the bottom of the control gate 21 cannot be lowered so that the control gate 21 can be deeply formed between the floating gates 15, thereby limiting the improvement of inter-cell interference.

The present invention provides a flash memory device and a method of manufacturing the same, which can improve the interference phenomenon even when the gap between the cells is narrowed and to secure the distance between the tunnel insulating film and the control gate.

Flash memory device according to an embodiment of the present invention, A device isolation film formed in the device isolation region of the semiconductor substrate, a tunnel insulation film formed in the active region of the semiconductor substrate, a first conductive film formed on the tunnel insulation film, a first conductive film, and a groove formed on the device isolation film, and having a groove exposing the device isolation film. And a second conductive layer formed on the dielectric layer, the trench formed in the device isolation layer and the trench formed in the device isolation layer.

In the above, the device isolation film is formed higher than the surface of the active region of the semiconductor substrate and lower than the surface of the first conductive film.

Grooves of the dielectric film are formed in the upper center of the device isolation film.

The trench is formed in the center of the device isolation film. The trench is formed at least to a depth corresponding to the height of the surface of the active region of the semiconductor substrate.

A capping film for exposing the groove is further formed on the dielectric film.

The dielectric film is formed of a stacked structure of an oxide film, a nitride film, and an oxide film, and the nitride film exposed through the grooves is formed to protrude more than the oxide film exposed through the grooves.

In the method for manufacturing a flash memory device according to the first embodiment of the present invention, the device isolation layer is formed in the device isolation region, the active region is provided with a semiconductor substrate formed with a laminated film of the tunnel insulating film and the first conductive film, the device isolation film and Forming a dielectric film on the first conductive film, etching the dielectric film on the device isolation film to form a groove, etching the device isolation film exposed through the groove to form a trench in the device isolation film, and filling the trench and the groove Forming a second conductive film on the dielectric film.

In the above, The device isolation film is formed higher than the surface of the active region of the semiconductor substrate and lower than the surface of the first conductive film.

Grooves of the dielectric film are formed in the upper center of the device isolation film.

The trench is formed in the center of the device isolation film. The trench is formed at least to a depth corresponding to the height of the surface of the active region of the semiconductor substrate.

The forming of the grooves may include forming an etch barrier layer thicker on the first conductive layer than on the device isolation layer on the dielectric layer, and between the etch barrier layer and the dielectric between the vertical portions of the etch barrier layer to separate the dielectric layer between the cells. Etching the film further.

Etch barrier films include amorphous carbon, carbon-based materials, silicon nitride (SixNy) (x and y are each positive integers), silicon oxynitride (SiON), oxide and boron nitride (BN) films. It is formed of either.

The etching barrier layer is formed by a plasma enhanced chemical vapor deposition (PECVD) method or a spin coating method.

The groove is formed by a first etching process that performs the dry etching process alone or by a second etching process that combines the dry etching process and the wet etching process.

The second etching process is a dry etching process to etch the etching barrier layer between the vertical portions of the etching barrier layer, and then to expose the dielectric layer exposed by the wet etching process using the remaining etching barrier layer as a mask.

In the step of forming the trench, the etch barrier film is removed.

The forming of the groove further includes forming a capping layer between forming the etch barrier film and etching the dielectric film.

The capping film is formed by plasma chemical vapor deposition (PECVD). The capping film is formed of a polysilicon film.

The capping layer is etched by a wet etching process using a remaining etching barrier layer as a mask after the etching barrier layer between the vertical portions of the etching barrier layer is etched by a dry etching process.

The method may further include forming a photoresist pattern on the etching barrier layer to expose the etching barrier layer between the vertical portions of the etching barrier layer between forming the etching barrier layer and etching the dielectric layer.

The method may further include performing a cleaning process or a plasma process to remove the carbon component remaining on the semiconductor substrate between forming the trench and forming the second conductive film.

As another example, the forming of the groove may include forming an etching barrier layer on the dielectric layer, and etching formed on the sidewall of the first conductive layer and the upper portion of the isolation layer so that the etching barrier layer remains on the top of the first conductive layer. Removing the barrier film, and etching the exposed dielectric film at the portion from which the etch barrier film is removed.

Before the etching barrier layer is formed, a capping layer is formed on the dielectric layer using a polysilicon layer.

The capping layer formed on the upper portion of the isolation layer is exposed in the step of removing the etch barrier layer formed on the sidewall of the first conductive layer and the upper portion of the isolation layer, and the exposed capping layer is removed before etching the dielectric layer.

The step of removing the exposed capping film may be performed by mixing any one of a mixed gas of SF ₆ gas and O ₂ gas, a mixed gas of Cl ₂ gas and O ₂ gas, and a mixed gas of SF ₆ gas, Cl ₂ gas and O ₂ gas. It is carried out using gas.

The etch barrier film is formed thicker on the top of the first conductive film than on the sidewall of the first conductive film and the top of the device isolation layer.

The etching barrier film is formed of a PE oxide film.

In the step of forming the groove, the remaining etching barrier film is etched.

After forming the grooves, the step of widening the width of the bottom of the grooves is carried out.

The step of widening the bottom of the groove is performed simultaneously with the step of forming the trench in the device isolation film.

The step of widening the bottom of the groove is performed by using a wet etching process.

In the step of widening the bottom of the groove, the etch barrier film is completely removed.

The present invention has the following effects.

First, since the bottom of the control gate can be lowered up to the thickness of the dielectric film and the trench of the device isolation layer, the interference phenomenon between the floating gates can be improved even if the gap between the cells is narrowed. As a result, the present invention can improve the operation speed of the device.

Second, the present invention is to improve the interference phenomenon by forming a trench in the device isolation layer through the groove formed after the dielectric film formation even if the effective field oxide height (EFH) of the device isolation layer is formed before the dielectric film formation. The height I _EFH of the effective field oxide layer may be adjusted.

Third, the present invention can secure the distance (C _EFH ) between the tunnel insulating film and the control gate related to the cycling characteristics through the device isolation film formed before the dielectric film formation, thereby reducing the cycling threshold voltage shift (cycling Vt shift). The deterioration characteristic can be improved.

Fourth, the present invention forms a trench in the device isolation layer through the groove formed in the dielectric film, so as to repeat the deposition, etching, deposition, etc. of the device isolation layer having wing spacers using two or more device isolation material forming materials as before. Since the process can be omitted, the manufacturing process can be simplified.

As described above, the present invention can lower the bottom of the control gate formed between the floating gates in a simplified and stabilized manner, and improve the reliability and mass productivity of the flash device by securing the distance between the tunnel insulating film and the control gate. .

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a flash memory device according to a first embodiment of the present invention.

Referring to FIG. 2A, a tunnel insulating layer 102 and a first conductive layer 104 are stacked in an active region A by a conventional method of manufacturing a flash memory device, and a first trench between the active regions A is formed. 106 is provided with a semiconductor substrate 100 on which an isolation layer 108 is formed.

The tunnel insulating layer 102 may be formed of a silicon oxide layer (SiO ₂ ), and in this case, may be formed by an oxidation process. The first conductive layer 104 is used as a floating gate of the flash memory device and may be formed of a polysilicon layer. In this case, the first conductive film 104 is patterned in a direction parallel to the device isolation film 108 (bit line direction). The first trench 106 sequentially laminates the tunnel insulating layer 102, the first conductive layer 104, and the device isolation mask (not shown) on the semiconductor substrate 100, and then etches the photoresist pattern (not shown). Self Align-Shallow Trench to etch a device isolation mask, a first conductive film 104, a tunnel insulating film 102, and a semiconductor substrate 100 to a predetermined depth by an etching process used as a mask. Isolation (SA-STI) process.

The device isolation layer 108 is formed of an oxide-based material, for example High Temperature Oxide (HTO) Film, High Density Plasma (HDP) Oxide, TEOS (Tetra Ethyl Ortho Silicate), BPSG (Boron-Phosphorus Silicate Glass) or USG (Undoped Silicate Galss) Can be formed. The device isolation layer 108 may deposit an insulating film on the device isolation mask including the first trench 106 so that the first trench 106 is filled, and then planarize the surface of the insulating film, and then etch to lower the height of the device isolation layer. It can form by performing a process. The planarization process is preferably performed by a chemical mechanical polishing (CMP) process using a nitride film for device isolation of the device isolation mask as a polishing stop film. In this case, the surface of the device isolation layer 108 is formed so as not to be lower than the surface of the active region A of the semiconductor substrate 100 in consideration of cycling characteristics. For example, the surface of the device isolation layer 108 may be formed higher than the bottom surface of the first conductive layer 104 to expose the upper sidewall of the first conductive layer 104. After the device isolation film 108 is formed, the nitride film for device isolation remaining is removed. Meanwhile, the nitride film for device isolation remaining after the planarization may be removed first, and then an etching process may be performed to lower the thickness of the device isolation film. The formation of the first trench 106 and the isolation layer 108 defines the active region A. FIG.

Although not shown, a sidewall oxide layer is further formed on the sidewalls and the bottom of the first trench 106 to heal the etch damage generated during the etching process for forming the first trench 106. The oxide film may be formed by an oxidation process after forming the first trench 106.

Subsequently, the dielectric film 110 is formed on the surface of the device isolation film 108 and the exposed first conductive film 104. The dielectric film 110 may be formed as a stacked film of a first oxide film, a nitride film, and a second oxide film (Oxide-Nitride-Oxide (ONO)). In this case, the dielectric film 110 is formed by depositing by a plasma enhanced chemical vapor deposition (PECVD) method.

In this case, the step coverage is low due to the deposition characteristic, so that the dielectric film 110 is thicker at the top of the first conductive film 104 than at the sidewall of the first conductive film 104 and the top of the device isolation film 108. And thicker at the sidewalls of the first conductive film 104 than at the top of the device isolation film 108.

Referring to FIG. 2B, a capping layer 112 having a liner shape is further formed on the dielectric layer 110 along the surface of the dielectric layer 110. The capping film 112 serves as a protective film of the dielectric film 110 so that the dielectric film 110 is not directly exposed in a subsequent etching process, a cleaning process, and a strip process. It is preferable to form a polysilicon film so as to be used as a lower conductive film for the control gate of the flash memory device. In particular, the capping film 112 may be formed of a laminated film of an undoped polysilicon film and a doped polysilicon film in order to improve a phenomenon in which impurities injected into the film diffuse downward.

The capping layer 112 is deposited by PECVD, and in this case, the step coverage is low due to the deposition property, so the capping layer 112 is formed on the upper side of the dielectric layer 110 than on the sidewall of the dielectric layer 110 and the upper portion of the device isolation layer 108. It is formed thicker than in, and formed thicker on the sidewall of the dielectric film 110 than on top of the device isolation film 108.

Subsequently, an etching barrier layer 114 for separating the inter-cell capping layer 112 is formed on the capping layer 112 in a subsequent process. The etching barrier layer 114 is an etching process using a thickness difference between the etching barrier layer 114 on the upper portion of the first conductive layer 104 and the upper portion of the isolation layer 108 in the subsequent etchback process. In order to effectively separate the capping layer 112 and the dielectric layer 110, the carbon may be formed by PECVD or spin coating using amorphous carbon.

The etching barrier layer 114 may be formed by spin coating using a carbon-based material, for example, a carbon polymer, using carbon as a main component instead of amorphous carbon. In addition, the etching barrier film 114 may be a silicon nitride film (SixNy) (x and y each have a positive integer), a silicon oxynitride film (SiON), an oxide film, or a boron nitride (BN) film instead of a carbon-based material. It can also be formed using a PECVD method as a thin film of. As a result, the etch barrier layer 114 is formed thicker on the upper portion of the first conductive layer 104 than on the upper side of the device isolation layer 108 and the sidewalls of the capping layer 112. It is formed thicker on the sidewall of the capping film 112.

Referring to FIG. 2C, the etching barrier layer 114, the capping layer 112, and the dielectric layer 110 are etched to separate the inter-cell capping layer 112 and the dielectric layer 110. A groove 115 is formed to expose. Here, the etching process may be performed as a first process for performing a dry etching process alone or as a second process for combining a dry etching process and a wet etching process.

In the etching process, the etching barrier layer 114, the capping layer 112, and the dielectric layer 110 are sequentially etched by a dry etchback process. In this case, the dry etchback process sets an etch target to a thickness capable of separating the inter-cell dielectric film 110 by forming the groove 115.

As a result, the etching barrier layer 114, the capping layer 112, and the dielectric layer 110 are sequentially etched between the vertical portions of the etching barrier layer 114 by a dry etchback process to form grooves 115. The inter dielectric film 110 is separated, and the surface of the device isolation film 108 is exposed through the groove 115. This is because the horizontal portions of the etch barrier film 114, the capping film 112, and the dielectric film 110 are thick on the first conductive film 104, and relatively on the device isolation film 108 to which the dielectric film 110 is to be separated. This is possible because it is thinly deposited. In this case, the groove 115 of the dielectric film 110 is formed on the center of the device isolation layer 108.

However, the vertical portion of the etch barrier film 114 deposited thicker than the horizontal portion after the dry etch back process remains on the sidewall of the capping film 112. Meanwhile, a part of the etch barrier film 114 deposited thicker on the first conductive film 104 than on the device isolation film 108 after the dry etchback process may remain on the first conductive film 104. The capping layer 112 on the first conductive layer 104 may be partially etched.

When an etching process is performed as a 2nd process, it is as follows. First, the grooves 115 are formed by etching the etching barrier layer 114 by a dry etching process, preferably a dry etchback process. In this case, the dry etch back process may be performed by using the horizontal portion of the etch barrier layer 114 formed on the device isolation layer 108 as an etch target. As a result, a horizontal portion of the etch barrier layer 114 formed on the device isolation layer 108 is etched by a dry etchback process to form a groove 115 in the etch barrier layer 114, and a cap through the groove 115. The surface of the ping film 112 is exposed. In this case, the groove 115 of the etch barrier layer 114 is formed on the center of the device isolation layer 108.

However, after the dry etchback process, the vertical portion of the etch barrier layer 114 deposited thicker than the horizontal portion remains on the sidewall of the capping layer 112, and the upper portion of the first conductive layer 104 is formed on the device isolation layer 108. A portion of the etch barrier film 114 deposited thicker at the top remains on the first conductive film 104.

Subsequently, the capping film 112 exposed through the grooves 115 and the dielectric film 110 under the wet etching process using the remaining etching barrier film 114 as a mask, preferably a wet etch back process, may be used. Etch it. As a result, the capping film 112 exposed through the groove 115 and the dielectric film 110 under the etching by the wet etch back process are etched to form the groove 115 to separate the inter-cell dielectric film 110. The surface of the device isolation layer 108 is exposed through the groove 115. This is because the horizontal portions of the etch barrier film 114, the capping film 112, and the dielectric film 110 are thick on the first conductive film 104 and relatively thin on the device isolation film 108 to separate the dielectric film 110. This is possible because it is deposited. In this case, the groove 115 of the dielectric film 110 is formed on the center of the device isolation layer 108.

On the other hand, the etching process for separating the inter-cell dielectric film 110 further forms a photoresist pattern (not shown) that exposes between the vertical portions of the etching barrier film 114 on the etching barrier film 114 and then the photoresist film It can also be implemented using a pattern as a mask.

Referring to FIG. 2D, a second trench 116 is formed in the device isolation layer 108 by etching the device isolation layer 108 exposed through the groove 115. The etching process may be performed by a dry etching process or a wet etching process. In consideration of the cycling characteristics of the tunnel insulating layer 102, the second trench 116 may have a depth corresponding to at least the height of the surface of the active region of the semiconductor substrate 100. It is preferable to form up to depth. As a result, the device isolation layer 108 exposed through the groove 115 is etched to form a concave second trench 116 in the upper portion of the center of the device isolation layer 108.

In addition, a wing spacer is formed on the sidewall of the tunnel insulating layer 102 by the second trench 116. Therefore, as in the related art, in order to form the wing spacers on the sidewalls of the tunnel insulation layer, a repeating process such as deposition, etching, and deposition using two or more device isolation layer forming materials may be omitted, thereby simplifying the manufacturing process.

In the process of forming the second trench 116, the remaining etch barrier film (114 of FIG. 2C) is removed together to completely expose the surface of the remaining capping film 112. However, the surface of the dielectric film 110 remaining in the etching process is protected by the capping film 112 without being directly exposed.

Meanwhile, when the carbon component remains on the semiconductor substrate 100 after the etching barrier layer 114 is removed, the carbon component remaining on the semiconductor substrate 100 may be completely removed by using a cleaning process or a plasma process. Remove

Referring to FIG. 2E, a second conductive layer 118 is formed on the capping layer 112 including the second trench 116. The second conductive film 118 is used as a control gate of a flash memory device, and may be formed of a polysilicon film, a metal layer, or a laminated film thereof. The metal layer may include a metal silicide layer. The second conductive film 118 may be preferably formed of a polysilicon film, in which case it is formed of a doped polysilicon film.

Thereafter, a direction in which the second conductive film 118, the capping film 112, the dielectric film 110, and the first conductive film 104 intersect the device isolation film 108 by a conventional etching process (word line direction) Pattern with. As a result, a floating gate made of the first conductive film 104 and a control gate 120 made of the capping film 112 and the second conductive film 118 are formed to form the floating gate 104, the dielectric film 110, And a gate pattern in which the control gate 120 is stacked.

According to the first exemplary embodiment of the present invention, since the second conductive layer 118 is formed lower than the dielectric layer 110 between the floating gates 104, the dielectric corresponding to the horizontal portion of the upper portion of the device isolation layer 108 as compared with the related art. The bottom of the control gate 120 may be lowered by the height of the thickness of the layer 110 and the thickness of the etched device isolation layer 108 in the second trench 116. Therefore, the area occupied by the control gate 120 may be increased by the portion protruding below the capping layer 112 between the floating gates 104.

In general, when a trench is formed in the device isolation film, or when the top of the device isolation film is formed in a concave concave shape to form a dielectric film and a conductive film for a control gate, the trench (or concave portion) is a dielectric material. Since the film is filled with a film, a control gate conductive film may not be formed in the trench, or a small amount of the control gate conductive film may be formed in the trench. However, in the present invention, the second trench 116 may be formed by etching the device isolation layer 108 exposed through the groove formed in the dielectric layer 110. Since the second conductive layer 118 is formed in the groove and the second trench 116 of the dielectric layer 110, the dielectric constant value between the floating gates 104 may be lowered than when the dielectric layer is formed in the trench of the isolation layer. Can be. That is, since the bottom surface of the second conductive layer 118 can be lowered than in the related art, the parasitic capacitance between the floating gates 104 can be lowered to minimize interference between adjacent cells.

In addition, in order to secure the distance C _EFH between the tunnel insulating film 102 and the control _gate 120 related to the cycling characteristics, the height of the device isolation film 108 is increased before the dielectric film 110 is formed. However, by etching the device isolation layer 108 exposed through the groove formed in the dielectric layer 110 in a subsequent process, the height I _EFH of the effective field oxide layer related to the interference phenomenon may be lowered. Accordingly, the present invention improves the interference phenomenon and secures the distance C _EFH between the tunnel insulating film 102 and the control gate 120 to increase the cycling threshold voltage when the tunnel insulating film 102 is close to the control gate 120. Decreasing characteristics of the tunnel insulating layer 102 may be improved by reducing a cycling Vt shift.

3A to 3G are cross-sectional views illustrating a method of manufacturing a flash memory device according to a second embodiment of the present invention.

Referring to FIG. 3A, a tunnel insulating film 203 and a first conductive film 205 are stacked on an active region A by a conventional method of manufacturing a flash memory device, and device isolation between the active regions A is performed. In the region, a semiconductor substrate 201 in which the device isolation film 207 is formed is provided. A detailed description of the method of stacking the tunnel insulating film 203 and the first conductive film 205 on the active region A and forming the device isolation film 207 in the device isolation region is the same as in FIG. 2A.

As described above, after the tunnel insulating film 203 and the first conductive film 205 are stacked on the active region A, and the semiconductor substrate 201 in which the device isolation film 207 is formed in the device isolation region is provided, the device isolation film ( 207 and a dielectric film 209 are formed on the surfaces of the first conductive film 205. The dielectric film 209 may have a structure in which a first oxide film 209a, a nitride film 209b, and a second oxide film 209c (Oxide-Nitride-Oxide; ONO) are stacked.

Referring to FIG. 3B, a capping film 211 is further formed on the surface of the dielectric film 209. The capping layer 211 protects the dielectric layer 209 so that the dielectric layer 209 is not directly exposed in a subsequent etching process, a cleaning process, and a strip process. In addition, the capping film 211 is preferably formed of a conductive film so that the capping film 211 can be used as a lower conductive film for the control gate. The capping film 211 may be formed using polysilicon. The polysilicon film constituting the capping film 211 is preferably a doped polysilicon film containing a dopant such as phosphorous. At this time, the doped polysilicon film contains a dopant of 1.0E20 atoms / cm ³ to 3.0E20 atoms / cm ³ , and is preferably formed to a thickness of 50 kPa to 200 kPa.

Thereafter, an etching barrier film 213 is deposited on the capping film 211. The etching barrier layer 213 exposes the capping layer 209 formed on the upper side of the device isolation layer 207 and the sidewalls of the first conductive layer 205 after the subsequent etching process, and is formed on the first conductive layer 205. In order to protect the capping film 205, it is preferable to deposit the method with low step coverage characteristics. That is, the etching barrier layer 213 may be formed thicker on the top of the first conductive layer 205 than on the top of the device isolation layer 207 and the sidewall of the first conductive layer 205. To this end, the etching barrier film 213 may be deposited by a plasma method. In addition, the etching barrier layer 213 is preferably formed using a material that is easy to remove using a subsequent process without a separate removal process. To this end, the etching barrier film 213 is preferably formed of an oxide film, and more preferably, formed of a PE (Plasma Enhanced) -oxide film.

The PE-oxide film may be formed by mixing SiH ₄ gas and O ₂ gas at a temperature of 350 ° C. to 450 ° C. and injecting it into a chamber, using plasma having He or Ar as a carrier gas.

Referring to FIG. 3C, the etching barrier layer 213 is etched to expose the capping layer 209 formed on the device isolation layer 207 and the capping layer 209 formed on the sidewall of the first conductive layer 205. Since the etch barrier layer 213 formed on the top of the first conductive layer 205 is formed relatively thicker than the etch barrier layer 213 formed on the sidewall of the first conductive layer 205 and the device isolation layer 207. Not removed. The etching barrier layer 213 may be etched using hydrofluoric acid (HF) or buffer oxide etchant (BOE).

Referring to FIG. 3D, the capping film 211 on the device isolation film 207 exposed in FIG. 3C is etched to expose the dielectric film 209 on the device isolation film 207. When the capping layer 211 is etched, the capping layer 211 below the remaining etching barrier layer 213 is protected by the etching barrier layer 213 and thus is not removed. Accordingly, after the capping layer 211 is etched, the dielectric layer 209 on the device isolation layer 207 is exposed, and the dielectric layer 209 under the capping layer 211 protected by the etching barrier layer 213 is exposed. It doesn't work. That is, the dielectric film 209 formed on the top of the first conductive film 205 and on the sidewalls of the first conductive film 205 is not exposed. The capping film 211 formed of polysilicon may be any one of a mixed gas of SF ₆ gas and O ₂ gas, a mixed gas of Cl ₂ gas and O ₂ gas, and a mixed gas of SF ₆ gas, Cl ₂ gas and O ₂ gas. It can be etched using a mixed gas of.

Referring to FIG. 3E, the groove 210 is formed in the dielectric layer 209 by etching the dielectric layer 209 on the exposed device isolation layer 207 after the capping layer 211 etching process described above with reference to FIG. 3D. An etching process for forming the groove 210 may be performed by dry etching. In this case, part or all of the dielectric film 209 formed on the device isolation layer 207 may be etched. The groove 210 for exposing the first oxide layer 209a of the dielectric layer 209 or through the dielectric layer 209 to expose the device isolation layer 207 by etching the dielectric layer 209 is defined. In addition, when the dielectric film 209 is etched, the remaining etch barrier film 213 is etched. During the etching process for forming the groove 210, the capping layer 211 made of a polysilicon layer protects the dielectric layer 209 formed on the top and sidewalls of the first conductive layer 205 from being etched.

Referring to FIG. 3F, a wet etching process is further performed to widen the bottom of the groove 210. As a result, not only the first oxide film 209a of the dielectric film 209 is etched, but also the second oxide film 209c is etched. As a result, the nitride film 209b is formed to protrude from the first and second oxide films 209a and 209c on the sidewall of the groove 210. That is, unevenness is formed in the sidewall of the groove 210. By widening the width of the bottom surface of the groove 210 as described above, it is possible to prevent the occurrence of a peak on the bottom surface of the second conductive film to be formed inside the groove 210 in a subsequent process. As a result, the present invention can prevent a phenomenon in which electric charge is concentrated by accumulating charges on the dots formed in the second conductive layer when the flash memory device is driven. In addition, by performing the wet etching process, the etching barrier film 213 that may remain on the capping film 211 is completely removed. The capping layer 211 protects the dielectric layer 209 formed on the top and sidewalls of the first conductive layer 205 from being etched during the etching process for increasing the width of the bottom surface of the groove 210. In addition, by performing a wet etching process, the device isolation layer 207 under the groove 210 may be etched to form a second trench 213 in the device isolation layer 207.

Referring to FIG. 3G, a second conductive layer 215 filling the groove 210 and the second trench 213 is formed on the capping layer 211. The second conductive film 215 is a control gate conductive film, and is preferably formed to a sufficient thickness so as to fill the space between the groove 210 and the first conductive film 205. In addition, the second conductive layer 215 may be formed of a doped polysilicon layer. At this time, the doped polysilicon film may contain a dopant of 1.0E20 atoms / cm ³ to 3.0E20 atoms / cm ³ . The bottom surface of the second conductive layer 215 formed between the first conductive layer 205 may be formed to be lower through the groove 210 and the second trench 213 formed in the dielectric layer 209.

Thereafter, the second conductive layer 215, the capping layer 211, the dielectric layer 209, and the first conductive layer 205 are patterned in a direction crossing the device isolation layer 207 by a conventional etching process. As a result, the first conductive film 205 connected in parallel with the device isolation film 207 is separated into a plurality of patterns. As a result, a floating gate composed of the first conductive layer 205 and a control gate composed of the capping layer 211 and the second conductive layer 215 are formed to form the floating gate 205, the dielectric layer 209, and the control gate ( A gate pattern in which 211 and 215 are stacked is formed.

As described above, in the second embodiment of the present invention, as in the first embodiment of the present invention, the second conductive film 215 is formed by the sum of the heights of the grooves 210 and the second trenches 213 of the dielectric film 209. Since the bottom surface may be lowered, the dielectric constant value between the first conductive layers 205 may be lowered. As a result, parasitic capacitance between the first conductive layer 205 may be lowered to minimize interference between adjacent cells.

In addition, in the second embodiment of the present invention, the element isolation film 207 before forming the dielectric film 209 to secure the distance C _EFH between the tunnel insulating film 203 and the second conductive film 215 related to the cycling characteristics. Even if the height of the () is increased, the height I _EFH of the effective field oxide film related to the interference phenomenon may be lowered by etching the device isolation film 207 exposed through the groove formed in the dielectric film 209 in a subsequent process. Therefore, the present invention improves the interference phenomenon and secures the distance C _EFH between the tunnel insulating film 203 and the second conductive film 215, and thus becomes worse when the tunnel insulating film 203 is close to the second conductive film 215. By reducing the cycling threshold voltage shift (cycling Vt shift) can improve the degradation characteristics of the tunnel insulating film 203.

In addition, in the second embodiment of the present invention, in order to form the grooves 210 in the dielectric film 209, the etching barrier film 213 is left only at the top of the first conductive film 205. It is not necessary to remove the etching barrier film 213 remaining on the sidewall of the first conductive film 205. Accordingly, since the device isolation layer 209 may not be etched after the groove 210 is formed, height adjustment of the device isolation layer 207 may be easily performed. In more detail, the device isolation layer 207 may be exposed through the groove 210 formed in the dielectric layer 209. When the etch barrier layer 213 remains on the sidewall of the first conductive layer 205, the etch remaining on the sidewall of the first conductive layer 205 while the device isolation layer 207 is exposed through the groove 21. Barrier film 213 should be removed. In this case, since the device isolation layer 207 exposed through the groove 210 may be etched, it is difficult to adjust the height of the device isolation layer 207. However, in the present invention, since the etch barrier layer 213 may be removed through a series of processes up to the formation of the groove 210, height adjustment of the device isolation layer 207 is easy.

In addition, according to the present invention, after the groove 210 is formed in the dielectric film 209, an etching process is performed to increase the width of the bottom surface of the groove 210. This can improve the concentration of the electric field.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1 is a cross-sectional view showing a flash memory device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a flash memory device according to a first embodiment of the present invention.

3A to 3G are cross-sectional views illustrating a method of manufacturing a flash device according to a second embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 201: semiconductor substrate 102, 203: tunnel insulating film

104, 205: first conductive film 106: first trench

108, 207: device isolation film 110, 209: dielectric film

115, 210: Groove 112, 211: Capping film

114,213: etching barrier film 116,213: second trench

118, 215: second conductive film

Claims (36)

An isolation layer formed in the isolation region of the semiconductor substrate; A tunnel insulating film formed in an active region of the semiconductor substrate; A first conductive film formed on the tunnel insulating film; A dielectric film formed along surfaces of the first conductive film and the device isolation film; A capping film formed along a surface of the dielectric film; A groove formed in the upper portion of the device isolation layer through the capping layer and the dielectric layer; A trench formed in the device isolation layer below the groove; And A second conductive layer filling the trench and the groove and formed on the dielectric layer, And a width of a portion of the groove penetrating the dielectric film is wider than a width of the portion of the groove penetrating the capping film. The method of claim 1, And the device isolation layer is formed higher than the surface of the active region of the semiconductor substrate and lower than the surface of the first conductive layer. The method of claim 1, And the groove is formed on the center of the device isolation layer. The method of claim 1, The trench is a flash memory device formed in the center of the isolation layer. The method of claim 1, And the trench is formed to a depth corresponding to at least a height of a surface of an active region of the semiconductor substrate. delete The method of claim 1, The dielectric film is formed of a laminated structure of a first oxide film, a nitride film and a second oxide film, And the nitride film exposed through the groove is formed to protrude relative to the first and second oxide films exposed through the groove. Providing a semiconductor substrate having a device isolation film formed in the device isolation region, and a stacked film of a tunnel insulating film and a first conductive film formed in the active region; Forming a dielectric film along surfaces of the device isolation film and the first conductive film; Forming a capping film on an upper surface of the dielectric film; Etching the capping layer and the dielectric layer on the device isolation layer to form a groove; Etching the dielectric film exposed through the groove to widen the width of the bottom of the groove; Etching the device isolation layer exposed through the groove to form a trench in the device isolation layer; And And forming a second conductive layer on the dielectric layer to fill the trench and the groove. The method of claim 8, And the device isolation layer is formed higher than the surface of the active region of the semiconductor substrate and lower than the surface of the first conductive layer. The method of claim 8, And the groove is formed on the center of the device isolation layer. The method of claim 8, And the trench is formed in the center of the device isolation layer. The method of claim 8, And the trench is formed to a depth corresponding to at least a height of a surface of an active region of the semiconductor substrate. delete delete delete delete delete delete The method of claim 8, The dielectric film is formed by a plasma chemical vapor deposition (PECVD) method of manufacturing a flash memory device. delete The method of claim 8, The capping film is a method of manufacturing a flash memory device formed by a plasma chemical vapor deposition (PECVD) method. The method of claim 8, And the capping film is formed of a polysilicon film. delete delete The method of claim 8, And performing a cleaning process or a plasma process to remove the carbon component remaining on the semiconductor substrate between the trench forming step and the second conductive film forming step. . The method of claim 8, Forming the grooves Forming an etching barrier layer on the capping layer; Removing the etch barrier layer formed on the sidewall of the first conductive layer and the device isolation layer so that the etch barrier layer remains on the top of the first conductive layer; Removing the capping layer on the device isolation layer to expose the dielectric layer; And Removing the exposed region of the dielectric film. delete delete The method of claim 26, The capping film may be removed by mixing a mixture gas of SF ₆ gas and O ₂ gas, a mixed gas of Cl ₂ gas and O ₂ gas, and a mixed gas of SF ₆ gas, Cl ₂ gas and O ₂ gas. Method for manufacturing a flash memory device carried out using. The method of claim 26, The etching barrier layer may be formed thicker at an upper portion of the first conductive layer than at a sidewall of the first conductive layer and an upper portion of the device isolation layer. The method of claim 26, The etching barrier film is a method of manufacturing a flash memory device formed of a PE-oxide film. The method of claim 26, The method of claim 1, wherein the remaining etching barrier layer is etched by removing the dielectric layer. delete The method of claim 8, The widening of the bottom surface of the groove is performed simultaneously with the step of forming a trench in the device isolation layer. The method of claim 8, The step of widening the width of the bottom of the groove is a method of manufacturing a flash memory device using a wet etching process. The method of claim 8, The method of claim 1, wherein the etching barrier layer is completely removed in the step of widening the bottom of the groove.

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