KR101037321B1 - Structure of capacitor in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor structure of a semiconductor device, and selects a wiring layer to be used for a capacitor configuration in a single layer or multilayer metallization process to form unit electrodes of a capacitor of a desired shape. Is used as a flat plate type, and when using mutual capacitance between adjacent wirings, it is formed as a comb type, and the formed unit electrodes are connected in parallel to each other so as to efficiently perform capacitance, and finally, two electrodes for capacitors are configured to have a capacitor structure. Because of this, it is possible to implement a large capacity capacitor without the additional process or cost for fabricating in-chip capacitors.

Capacitor, Metallization, Flat Type, Comb Type, Large Capacity

Description

Structure of capacitor in semiconductor device             

1 is a cross-sectional view of a capacitor of a semiconductor device according to a first embodiment of the present invention;

2 is a cross-sectional view of a capacitor of a semiconductor device according to a second embodiment of the present invention;

3 is a cross-sectional view of a capacitor of a semiconductor device according to a third embodiment of the present invention; And

4 is a cross-sectional view of a capacitor of a semiconductor device according to a fourth exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200, 300, 400: semiconductor substrate 102, 202, 302, 402: field oxide film

104, 204, 304, 404: polysilicon layer 106, 206, 306, 406: interlayer insulating layer

110, 210, 310, 410: first metal wiring 115, 215, 315, 415: first interlayer insulating layer

120, 220, 320, 420: second metal wiring 125, 225, 325, 425: second interlayer insulating layer

130, 330, 430: third metal wiring 135, 335, 435: third interlayer insulating layer

140, 340, 440: fourth metal wiring 145, 345, 445: fourth interlayer insulating layer

150, 350, 450: fifth metal wiring 155, 355, 455: fifth interlayer insulating layer

160, 360 and 460: sixth metal wiring 165, 365 and 465: sixth interlayer insulating layer                 

170, 370, 470: seventh metal wiring 175, 375, 475: seventh interlayer insulating layer

180, 380, 480: 8th metal wiring 185, 385, 485: 8th interlayer insulation layer

190, 290, 390, 490: first connection wiring 192, 292, 392, 492: second connection wiring

194, 294, 394, 494: first electrode 196, 296, 396, 496: second electrode

498: via contact 499A, 499B, 499C, 499D, 499E: unit electrode line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor structure of a semiconductor device, and more particularly, to a capacitor structure of a semiconductor device capable of realizing a large capacity capacitor without an additional process or cost by using a wiring selected during a wiring process.

In order to achieve thin, small, high performance, and low power of a system using a semiconductor device, a MRAM is a memory device such as a DRAM and a logic suitable for the memory device. It refers to a system on chip (SOC) that is implemented on a chip. With the development of SOC technology, manufacturing technology and design technology that can simultaneously implement passive devices in existing semiconductor manufacturing technology are required. Passive devices such as resistors and capacitors are essential for the manufacture of mixed signal chips. Currently, capacitors in a chip use PIP (Poly-Insulator-Poly) or MIM (Metal-Insulator-Metal) structures, but additional masks and manufacturing processes are inevitable to manufacture capacitors having such structures. The cost increases, and there is a limit to implementing a large capacity capacitor. Accordingly, researches are being conducted to simplify the process and reduce the manufacturing cost while implementing a large capacity capacitor.

Accordingly, an object of the present invention is to provide a capacitor structure of a semiconductor device capable of realizing a large capacity capacitor without additional processes or costs by using the selected wiring during the wiring process.

Capacitor structure of a semiconductor device according to an aspect of the present invention for achieving this object is a polysilicon layer formed on a semiconductor substrate; Multi-layered metal wires formed on each of the interlayer insulating layers by a metal wire process; And selecting a portion of each of the polysilicon layer and the multi-layered metal wirings to form capacitor unit electrodes, and alternately displace the capacitor unit electrodes from each other so as to efficiently allow capacitance. It consists of a 1st electrode and a 2nd electrode formed by connecting in parallel by 2 connection wiring.

In the above description, the first electrode is connected and grounded to the semiconductor substrate by the first connection wiring, and the capacitor unit electrode of the polysilicon layer among the capacitor unit electrodes and the unit electrode for the capacitor of the uppermost metal wiring of the metal wiring of the multilayer structure. Include at least.

A capacitor structure of a semiconductor device according to another aspect of the present invention is a polysilicon layer formed on a semiconductor substrate; Multi-layered metal wires formed on each of the interlayer insulating layers by a metal wire process; And forming a unit electrode for a capacitor by densifying a portion of the metal wiring of any one of the metal wires in a plurality of fine patterns, and alternately displacing the unit electrode for the capacitor so as to efficiently perform capacitance. The first electrode and the second electrode formed by connecting in parallel with the connection wiring and the second connection wiring.

In the above description, the first electrode is connected and grounded to the semiconductor substrate by the first connection line, and includes at least capacitor unit electrodes disposed at the outermost sides of the capacitor unit electrodes.

Capacitor structure of a semiconductor device according to another aspect of the present invention is a polysilicon layer formed on a semiconductor substrate; Multi-layered metal wires formed on each of the interlayer insulating layers by a metal wire process; And forming a unit electrode for a capacitor by densifying a portion of each of the polysilicon layer and the metal wires in a plurality of fine patterns, and alternately displacing the unit electrode for the capacitor so as to efficiently perform capacitance. The first electrode and the second electrode formed by connecting in parallel with the wiring and the second connection wiring.

In the above, the first electrode is connected to the semiconductor substrate by the first connection wiring and grounded, and the uppermost metal of the capacitor unit electrodes arranged in the outermost of the capacitor unit electrodes formed in each layer and the metal wiring of the multilayer structure It includes at least unit electrodes for all capacitors in the wiring.

Capacitor structure of a semiconductor device according to another aspect of the present invention is a polysilicon layer formed on a semiconductor substrate; Multi-layered metal wires formed on each of the interlayer insulating layers by a metal wire process; And a portion of each of the polysilicon layer and the metallization lines are concentrated in a plurality of fine patterns to form unit electrodes for the capacitor, the unit electrodes for the capacitor are arranged in a matrix, and the vertically aligned unit electrodes for the capacitor to the via contact. A plurality of capacitor unit electrode lines connected to each other, and a first electrode formed by connecting the capacitor unit electrode lines for capacitors alternately with each other in parallel to the first connection line and the second connection line so as to efficiently allow capacitance. And a second electrode.

In the above description, the first electrode is connected to the semiconductor substrate by the first connection line and is grounded, and includes at least capacitor unit electrodes disposed at the outermost sides of the unit electrode lines for the capacitor.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In addition, the thickness or size of each layer in the drawings may be exaggerated for convenience and clarity of description. In the drawings, like numerals refer to like elements.

1 is a cross-sectional view of a capacitor of a semiconductor device according to a first embodiment of the present invention.

A semiconductor substrate 100 having a field oxide film 102 formed thereon is provided, and a polysilicon layer 104 is formed by a photo process and an etching process. An interlayer insulating layer 106 is formed on the polysilicon layer 104. Subsequently, a metal wiring process is performed to apply the first to eighth metal wires 110, 120, 130, 140, to the first to eighth interlayer insulating layers 115, 125, 135, 145, 155, 165, 175, and 185, respectively. 150, 160, 170 and 180, respectively. The semiconductor device to be applied here describes a single-layer polysilicon layer and an eight-layer metal wiring structure. By selecting the wiring layer to be used for the capacitor configuration to form the unit electrodes for the capacitor of the desired type, in the first embodiment the polysilicon layer 104 and all metal wiring (110, 120, 130, 140, 150, 160, 170 and 180) The portions of the polysilicon layer 104 and the metallization lines 110, 120, 130, 140, 150, 160, 170 and 180 are used as unit electrodes for the capacitors. The form of the electrode is a plate type using the capacitance between the wiring layers. The interlayer insulating layers 115, 125, 135, 145, 155, 165, 175, and 185 existing between the unit electrodes serve as dielectric layers of the capacitor. By connecting the unit electrodes for the capacitors in parallel with each other alternately in order to efficiently enable the capacitance, two electrodes for the capacitor can be finally obtained, which will be described in detail as follows.

The unit electrodes for the capacitors of the polysilicon layer 104, the second metal interconnection 120, the fourth metal interconnection 140, the sixth metal interconnection 160, and the eighth metal interconnection 180 may include a first connection interconnection ( 190 is connected to form a first electrode 194, the capacitor for each of the first metal wiring 110, the third metal wiring 130, the fifth metal wiring 150 and the seventh metal wiring (170) The unit electrodes are connected to the second connection line 192 to form the second electrode 196. Typically, one of the two electrodes of the capacitor is grounded, where the first electrode 194 is connected to the semiconductor substrate 100 by the first connection wiring 190. In order to obtain stable capacitance by preventing interference of external conductors or leakage of own electric force lines, it is preferable that the grounded electrode surrounds the conductor of the counter electrode, and thus the unit electrodes for the capacitor forming the first electrode 194. The polysilicon layer 104 and the eighth metal interconnection 180 are formed to surround other capacitor unit electrodes.

The capacitor according to the first embodiment of the present invention is a flat plate type structure using area capacitance between wiring layers, which can be easily designed, and has the advantage of obtaining a relatively stable capacitance against process variation. .

2 is a cross-sectional view of a capacitor of a semiconductor device according to a second exemplary embodiment of the present invention.

A semiconductor substrate 200 on which a field oxide film 202 is formed is provided, and the polysilicon layer 204 is formed by a photo process and an etching process. An interlayer insulating layer 206 is formed on the polysilicon layer 204. Thereafter, a metal wiring process is performed to form a first metal wiring 210 on the first interlayer insulating layer 215, and a second metal wiring 220 on the second interlayer insulating layer 225. By selecting the wiring layer to be used in the capacitor configuration to form a unit electrode for the capacitor of the desired type, in the second embodiment a portion of the second metal wiring 220 is selected, a portion of the selected second metal wiring 220 By forming a fine pattern to form the unit electrodes for the capacitor, or a plurality of second metal wires 220 are arranged so as to be concentrated in this portion to form the unit electrodes for the capacitor. Accordingly, the unit electrodes have a comb type that uses mutual capacitance between adjacent wirings. The second interlayer insulating layer 225 existing between the unit electrodes serves as a dielectric film of the capacitor. By connecting the unit electrodes for the capacitors in parallel with each other alternately in order to efficiently enable the capacitance, it is possible to finally obtain two electrodes for the capacitor, which will be described in detail as follows.

The first connection line 290 and the second connection line 292 are alternately connected to the unit electrodes of the second metal line 220, and the unit electrodes connected to the first connection line 290 are first electrodes. 294, unit electrodes connected to the second connection line 292 form the second electrode 296. Typically, the capacitor is grounded to one of the two electrodes, where the first electrode 294 is connected to the semiconductor substrate 200 by the first connection wiring 290 is grounded. In order to obtain stable capacitance by preventing interference of external conductors or leakage of own electric lines, it is preferable that the grounded electrode surrounds the conductor of the counter electrode. Accordingly, the unit electrodes for the capacitor forming the first electrode 294 are provided. Each of the capacitor unit electrodes disposed at the outermost part of the capacitor is configured to surround other capacitor unit electrodes disposed therein.

The capacitor according to the second embodiment of the present invention is a comb-type structure using mutual capacitance between adjacent wirings. Since the mutual capacitance is used in the same wiring layer, the capacitor can be easily configured in a semiconductor device having a single wiring layer. have. At this time, in order to maximize the capacitance, apply the minimum rules of the wiring design to design the structure as dense as possible. The capacitor according to the second embodiment has an advantage in that the capacitance relative to the design area becomes larger toward the fine process.

3 is a cross-sectional view of a capacitor of a semiconductor device according to a third exemplary embodiment of the present invention.

A semiconductor substrate 300 on which a field oxide film 302 is formed is provided, and a polysilicon layer 304 is formed by a photo process and an etching process. An interlayer insulating layer 306 is formed on the polysilicon layer 304. Thereafter, a metal wiring process is performed to first and eighth metal wirings 310, 320, 330, 340, respectively, to the first to eighth interlayer insulating layers 315, 325, 335, 345, 355, 365, 375, and 385. 350, 360, 370 and 380, respectively. The semiconductor device to be applied here describes a single-layer polysilicon layer and an eight-layer metal wiring structure. By selecting the wiring layer to be used for the capacitor configuration to form a unit electrode for the capacitor of the desired type, in the third embodiment the polysilicon layer 304 and all metal wiring (310, 320, 330, 340, 350, 360, 370 and 380) ), The selected portions are formed into a plurality of fine patterns to form the unit electrodes for the capacitor, or the polysilicon layer 304 and the metal wires 310, 320, 330, 340, 350, 360, and 370 And 380, each of which is arranged so as to cross this portion in the same layer so as to form unit electrodes for the capacitor. The interlayer insulating layers 315, 325, 335, 345, 355, 365, 375, and 385 existing between the unit electrodes serve as dielectric layers of the capacitor. When the capacitor unit electrodes are connected in parallel to each other so that the capacitance can be efficiently obtained, two electrodes for the capacitor can be finally obtained.

A portion of each of the polysilicon layer 304 and all of the metal wires 310, 320, 330, 340, 350, 360, 370, and 380 forms a unit electrode for a plurality of capacitors, and a first connection wiring to these unit electrodes. The unit electrodes 390 and the second connection line 392 are alternately connected, and the unit electrodes connected to the first connection line 390 form the first electrode 394, and the unit electrode connected to the second connection line 392. To form the second electrode 396. Typically, one of the two electrodes of the capacitor is grounded, where the first electrode 394 is connected to the semiconductor substrate 300 by the first connection line 390. In order to obtain stable capacitance values by preventing interference of external conductors or leakage of own electric force lines, it is preferable that the grounded electrode surrounds the conductor of the counter electrode. Accordingly, all capacitor unit electrodes forming the first electrode 394 are provided. Among the unit electrodes of the eighth metal wiring 385, which is the uppermost layer, and the unit electrodes for the capacitors formed in the outermost of the unit capacitors formed in each layer, the unit electrodes for the other capacitors disposed in each layer therein. To wrap them around.

The capacitor according to the third embodiment of the present invention is a shielding structure that can obtain a large capacity by using two or more composite wiring layers. Since the capacitor according to the third embodiment of the present invention uses all the wiring layers, a large capacity can be obtained, and there is an advantage of taking various structures corresponding to the design intention from a simple structure to a complex structure. In addition, since the structure of the electrode connected to the ground completely surrounds the counter electrode, it is possible to shield leakage of an external electric field or an electric field leaking out as much as possible.

4 is a cross-sectional view of a capacitor of a semiconductor device according to a fourth exemplary embodiment of the present invention.

A semiconductor substrate 400 on which a field oxide film 402 is formed is provided, and a polysilicon layer 404 is formed by a photo process and an etching process. An interlayer insulating layer 406 is formed on the polysilicon layer 404. Subsequently, a metal wiring process is performed to first to eighth metal wires 410, 420, 430, 440, respectively, to the first to eighth interlayer insulating layers 415, 425, 435, 445, 455, 465, 475, and 485. 450, 460, 470 and 480, respectively. The semiconductor device to be applied here describes a single-layer polysilicon layer and an eight-layer metal wiring structure. By selecting the wiring layer to be used for the capacitor configuration to form a unit electrode for the capacitor of the desired type, in the fourth embodiment the polysilicon layer 404 and all metal wiring (410, 420, 430, 440, 450, 460, 470 and 480) ), The selected portions are formed into a plurality of fine patterns to form unit electrodes for a capacitor, or the polysilicon layer 404 and the metal wires 410, 420, 430, 440, 450, 460, and 470 And 480) each of which is arranged so as to cross this portion in the same layer so as to form unit electrodes for the capacitor. All capacitor unit electrodes are arranged in a matrix, and the vertically aligned unit electrodes for the capacitors are connected to the via contact 498 to form a plurality of unit electrode lines (not shown). The interlayer insulating layers 415, 425, 435, 445, 455, 465, 475, and 485 existing between the unit electrode lines (not shown) serve as a dielectric film of the capacitor. When the unit electrode lines (not shown) for capacitors are connected in parallel to each other so as to efficiently perform capacitance, two electrodes for the capacitor can be finally obtained.

First, third and fifth connected alternately to the first connection line 490 and the second connection line 492 to the unit electrode lines (not shown) for the capacitor, and to the first connection line 490 The unit electrode lines (not shown) for the capacitor constitute the first electrode 494, and the unit electrode lines (not shown) for the second and fourth capacitors connected to the second connection line 392 are the second electrodes 396. ) Is achieved. Typically, the capacitor is grounded to one of two electrodes, where the first electrode 494 is connected to the semiconductor substrate 400 by the first connection line 490. In order to obtain stable capacitance values by preventing interference of external conductors or leakage of own electric lines, it is preferable that the grounded electrode surrounds the conductor of the counter electrode. Accordingly, all capacitor unit electrodes constituting the first electrode 494 are provided. The capacitor unit electrode lines (not shown) disposed at the outermost of the lines (not shown) are configured to surround other capacitor unit electrode lines (not shown).

The capacitor according to the fourth embodiment of the present invention has a structure of increasing capacitance by using a via contact.

As described above, the present invention is to select the wiring layer to be used for the capacitor configuration in the single-layer or multi-layer metal wiring process to form the unit electrodes of the capacitor of the desired form, the final unit by connecting the formed unit electrodes in parallel with each other to enable efficient capacitance By forming two capacitors for the capacitor to form a capacitor structure, it is possible to implement a large-capacity capacitor without the additional process or cost for the production of in-chip capacitors.

Claims (12)

A polysilicon layer formed on the semiconductor substrate; A plurality of interlayer insulating layers stacked on the semiconductor substrate including the polysilicon layer; Multi-layered metal wires formed on each of the plurality of interlayer insulating layers; Capacitor unit electrodes formed on a portion of each of the polysilicon layer and the metal wires of the multilayer structure; A first connection line connected in parallel to unit electrodes of metal lines of an odd layer among the metal lines of the multilayer structure, and a second connection line connected in parallel to unit electrodes of metal lines of an even layer; And A first electrode connected to the first connection line connected in parallel with the unit electrodes of the metal lines of the odd layer, and a second electrode connected to the second connection line connected in parallel to the unit electrodes of the metal lines of the even layer. Capacitors in semiconductor devices. The capacitor of claim 1, wherein the first electrode is connected to the semiconductor substrate by the first connection line. The method of claim 1, wherein the first electrode comprises at least one of the capacitor unit electrode of the polysilicon layer of the capacitor unit electrode and the capacitor unit electrode of the uppermost metal wiring of the metal wiring of the multi-layer structure. Capacitor of a semiconductor device. A polysilicon layer formed on the semiconductor substrate; A plurality of interlayer insulating layers stacked on the semiconductor substrate including the polysilicon layer; A first metal wire formed on the lower interlayer insulating layer covering the polysilicon layer among the interlayer insulating layers; A plurality of second metal wires formed on the upper interlayer insulating layer covering the first metal wires; Capacitor unit electrodes formed on each of the plurality of second metal wires; A first connection line connected in parallel to unit electrodes for capacitors of odd-numbered metal lines among the plurality of second metal lines, and a second connection line connected in parallel to unit electrodes for capacitors of even-numbered second metal lines; And A first electrode connected to the first connection line connected in parallel with the unit electrodes of the odd-numbered second metal wires, and a second electrode connected to the second connection line connected in parallel to the unit electrodes of the even-numbered second metal wires A capacitor of a semiconductor element consisting of. The capacitor of claim 4, wherein the first electrode is connected to the semiconductor substrate and grounded by the first connection line. 6. The capacitor of claim 4 or 5, wherein the first electrode includes at least capacitor unit electrodes disposed at an outermost side of the capacitor unit electrodes. A plurality of polysilicon layers formed on the semiconductor substrate; A plurality of interlayer insulating layers stacked on the semiconductor substrate including the plurality of polysilicon layers; Metal wirings formed on each of the interlayer insulating layers, each of which has a multi-layer structure formed of a plurality of fine electrode patterns; Capacitor unit electrodes formed on each of the plurality of fine electrode patterns formed on the metal wires of the multilayer structure; First connection wirings connected in parallel to the capacitor unit electrodes of odd-numbered micro-electrode patterns among the plurality of micro-electrode patterns formed on the metal wires of the multilayer structure, and parallel to the unit electrodes for capacitors of the even-numbered micro-electrode patterns. A second connection wire connected to the second connection wire; And A first electrode connected to the first connection line connected in parallel with the unit electrodes of the odd-numbered fine electrode patterns, and a second electrode connected to the second connection line connected in parallel to the unit electrodes of the even-numbered fine electrode wirings. Capacitors in semiconductor devices. 8. The capacitor of claim 7, wherein the first electrode is connected to the semiconductor substrate by the first connection line. The method of claim 7, wherein the first electrode includes all of the capacitor unit electrodes disposed on the outermost sides of the capacitor unit electrodes formed in each layer and the uppermost metal wiring of the metal wiring of the multilayer structure. A capacitor of a semiconductor device, characterized in that it comprises at least unit electrodes for the capacitor. delete delete delete

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