KR101003451B1 - Charge trap flash memory using gst nanodot - Google Patents

Abstract

PURPOSE: A charge trap flash memory device with a GST nano dot is provided to improve the device property by increasing the trapped charge quantity and increasing trap density. CONSTITUTION: A semiconductor substrate(110) includes a source region and a drain region separated by a channel region. A tunneling insulating layer is formed on the channel region of the semiconductor substrate. A chalcogenide based compound nano dot is formed on the tunneling insulation layer. A blocking insulation layer(140) is formed on the tunneling insulation layer to cover the chalcogenide based compound nano dot.

Description

Charge trap flash memory using GST nanodot

The present invention relates to a flash memory device, and more particularly to a charge trap flash memory device.

Recently, due to the remarkable development of the information and communication industry, the demand for various memory devices is increasing. In particular, memory devices required for portable terminals, MP3 players and the like are required to be nonvolatile, in which recorded data is not erased even when the power is turned off. Such nonvolatile memory devices can be electrically stored and erased, and data can be stored even when power is not supplied. Therefore, their applications are increasing in various fields.

Exemplary nonvolatile memory devices are flash memory devices having electrically isolated floating gates. Flash memory devices are a type of nonvolatile memory device capable of erasing data in blocks of tens or hundreds of bits or more and writing data in bits or pages.

A floating gate type flash memory device has a structure in which a tunneling insulating film, a poly-Si floating gate, an inter-poly dielectric (IPD), and a control gate are sequentially stacked on a semiconductor substrate. . Such a floating gate type flash memory device is basically programmed and erased at a high voltage. Therefore, inevitably, unwanted leakage currents are generated in each of the tunneling insulating film and the inter-poly insulating film, and deterioration of the tunneling insulating film proceeds by repeated programming and erasing. Due to these characteristics, high level of reliability and low leakage current characteristics are required compared to other memory devices. Therefore, the thicknesses of the inter-poly insulating film and the tunneling insulating film, which play an important role in data storage and preservation, cannot be scaled but must be kept constant. As a result, due to such structural limitations, scaling down to the nanometer range shows a limit to device miniaturization.

As part of overcoming these limitations, a charge trap flash memory device using a semiconductor nanodot such as Si or Ge, a silicon nitride film, or a metal nanocrystal as a charge trap layer is used as a charge trap layer. trap flash memory (CTF) has been studied.

The technical problem to be solved by the present invention is to provide a new type of charge trap flash memory device.

In order to solve the above technical problem, a charge trap flash memory device according to the present invention comprises a semiconductor substrate having a source region and a drain region separated by a channel region; A tunneling insulating layer formed on the channel region of the semiconductor substrate; Chalcogenide-based compound nanodots formed on the tunneling insulating film; A blocking insulating film formed on the tunneling insulating film so that the chalcogenide-based compound nanopoints are covered; And a control gate formed on the blocking insulating layer.

In the charge trap flash memory device according to the present invention, a trap site in which charge is trapped may be formed at an interface between the nano dot and the blocking insulating film. In this case, in order to increase the density of the trap sites formed at the interface between the nano dot and the blocking insulating film, the blocking insulating film may be formed by a deposition method using plasma or at a temperature of 300 ° C. or less.

The chalcogenide-based compound may be GST (Ge ₂ Sb ₂ Te ₅ ), and the GST may be formed by cyclic plasma enhanced chemical vapor deposition (cyclic plasma enhanced chemical vapor deposition). The tunneling insulating film may be made of SiO ₂ , and the blocking insulating film may be made of Al ₂ O ₃ or HfO ₂ .

The charge trap flash memory device according to the present invention is programmed by trapping charge using a trap site formed at an interface between a chalcogenide-based compound nanopoint and a blocking insulating film. Therefore, the chalcogenide-based compound formed in the form of nano dots increases the trap density as compared to the case in which the continuous thin film is formed, and thus the device characteristics are excellent because the amount of trapped charge increases. In addition, the charge trap flash memory device according to the present invention has a very small leakage current of 10 ⁻⁷ A / cm ² or less, and has excellent charge retention characteristics.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the charge trap flash memory device using the GST nano-dot according to the present invention. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you.

1 is a view showing the structure of a preferred embodiment of a charge trap flash memory device according to the present invention.

Referring to FIG. 1, a charge trap flash memory device 100 according to an exemplary embodiment of the present invention may include a semiconductor substrate 110, a tunneling insulating layer 120, a chalcogenide-based compound nanodot 130, and a blocking ( A blocking insulating layer 140 and a control gate 150 are provided.

The semiconductor substrate 110 may be formed of silicon (Si), and is separated into a source region 111 and a drain region 112 by the channel region 113.

The tunneling insulating layer 120 is formed on the channel region 113 of the semiconductor substrate 110 and may be formed to a thickness of several nm. Depending on the material of the tunneling insulating layer 120, it is determined whether the chalcogenide-based compound nano dot 130 is grown in an island form or in a continuous layer form. The growth pattern of the chalcogenide-based compound nano dot 130 according to the type of the tunneling insulating film 120 is shown in FIGS. 2A and 2B, and the X-ray photoelectron spectroscopy (XPS) graphs are shown in FIGS. 3A and 3B. Indicated.

2A and 3A are cross-sectional transmission electron microscopy (TEM) images and XPS graphs when the tunneling insulating film 120 is a silicon oxide film (SiO ₂ ), respectively. 2B and 3B are cross-sectional transmission electron micrographs and XPS graphs when the tunneling insulating film 120 is formed of a silicon oxide film and a titanium oxide film (TiO ₂ ) double layer.

As shown in FIG. 2A, when the surface of the tunneling insulating film 120 is formed of a silicon oxide film, it can be seen that GST, which is a kind of chalcogenide-based compound, is grown in an island shape, as shown in FIG. 2B. If the surface of) is made of titanium oxide, it can be seen that the GST is grown in a continuous thin film form.

3A and 3B, it can be seen that the case where the surface of the tunneling insulating film 120 is made of silicon oxide film has more GeO ₂ formation than the case of titanium oxide film. This means that when the surface of the tunneling insulating film 120 is made of silicon oxide film, the exchange of charge is not easily performed by GeO ₂ , a reactant caused by the reaction between the GST and the silicon oxide film, so that generation of nucleation is suppressed. . If nucleation is suppressed, GST will grow in Ireland.

Accordingly, the tunneling insulating layer 120 is a material that reacts with the chalcogenide-based compound nanodots 130 to form a reactant such that the chalcogenide-based compound nanodots 130 are grown in an island form due to the suppression of nucleation. It is preferable to make. To this end, as described above, the tunneling insulating film 120 may be formed of a silicon oxide film. The tunneling insulating layer 120 made of a silicon oxide film may be easily implemented by oxidizing a silicon substrate.

The chalcogenide-based compound nano dot 130 is formed on the tunneling insulating layer 120. The chalcogenide-based compound nano dot 130 has a hemispherical shape and may be made of Ge ₂ Sb ₂ Te ₅ . As described above, since the chalcogenide-based compound such as GST grows in an island form on the silicon oxide film, hemispherical nanopoints can be easily obtained. GST can be formed by cyclic plasma enhanced chemical vapor deposition (cyclic PECVD). To this end, Ge (iC ₄ H ₉ ) ₄ , Sb (iC ₃ H ₇ ) ₃ , Te (iC ₃ H ₇ ) ₂ may be used as Ge precursors, Sb precursors, or Te precursors, respectively. A plan-view scanning electron microscopy (SEM) photograph of GST deposited by cyclic PECVD on a silicon oxide film is shown in FIG. 4.

As shown in FIG. 4, it can be seen that when GST is deposited by cyclic PECVD on a silicon oxide film, GST is deposited in an island form to form GST nanodots. As the number of cycles increases, the coverage covering the silicon oxide layer increases.

The freshly deposited (as-dep) GST is in an amorphous state, but becomes a crystalline state in a subsequent blocking process for depositing the insulating film 140. GST in this crystalline state is metastable and has a FCC (meta-stable face centered cubic) structure. This can be confirmed by cross-section transmission electron microscopy. A cross-sectional transmission electron micrograph of a laminated structure in which a GST nano dot is formed on an silicon oxide film and an aluminum oxide film (Al ₂ O ₃ ) is formed is shown in FIG. 5.

As shown in FIG. 5, it can be seen that a GST nanospot having a FCC structure is metastable between the silicon oxide film and the aluminum oxide film.

The blocking insulating layer 140 is formed on the tunneling insulating layer 120, and is formed to cover the chalcogenide-based compound nano dot 130. The blocking insulating layer 140 may be formed of a high-k material. For this purpose, the blocking insulating layer 140 may be formed of HfO ₂ or Al ₂ O ₃ . When the high dielectric constant thin film is used as the blocking insulating layer 140, the leakage current is reduced, thereby preventing the electron back-tunneling phenomenon that may occur in the erase operation, thereby reducing the erase operation time and the operating voltage. . The electron back-tunneling phenomenon is a phenomenon in which a trap site is filled by electrons from the control gate 150 when a negative voltage is applied to the control gate 150 to extract trapped electrons. Say.

A trap site is formed at the interface between the blocking insulating layer 140 and the chalcogenide-based compound nano dot 130 to trap charges. The charge trap flash memory device according to the present invention has a negative charge at the time of programming and a positive (+) at the trap site formed at the interface between the blocking insulating layer 140 and the chalcogenide compound nanopoint 130. The charge is trapped and operated. Therefore, it is necessary to increase the density of the trap site formed at the interface between the blocking insulating layer 140 and the chalcogenide-based compound nano dot 130. If the blocking insulating layer 140 is formed by a plasma deposition method or at a temperature of 300 ° C. or less, the density of the trap site is increased. Preferably, the blocking insulating layer 140 is formed by a deposition method using plasma at a temperature of 300 ° C. or less.

The control gate 150 may be formed on the blocking insulating layer 140, and may be formed of any one of a poly-Si thin film and a thin film having a larger work function than the poly-silicon thin film. The thin film having a higher work function than the polysilicon thin film may be at least one of TaN, HfN, ZrN, Pt, Ru, and Ir. As such, when the thin film including a material having a large work function is used as the control gate 150, the barrier height of the interface between the blocking insulating layer 140 and the control gate 150 increases, so that the above-described electronic back-tunneling The phenomenon can be prevented.

Production Example  1: aluminum Oxide (Al ₂ O ₃ )of  When used as a blocking insulating film

The n-type silicon substrate was oxidized to form a silicon oxide film of about 6 nm. At a temperature of about 150 ° C., Ge (iC ₄ H ₉ ) ₄ , Sb (iC ₃ H ₇ ) ₃ , and Te (iC ₃ H ₇ ) ₂ are used as Ge precursors, Sb precursors, and Te precursors, respectively. GST nanodots were formed on the silicon oxide film by click PECVD. At this time, the number of cycles was set to 10, 20, 30, 40, and 50 to form GST nanodots. Next, an aluminum oxide film was formed by plasma enhanced atomic layer deposition (PEALD) using TMA (Al (CH ₃ ) ₃ ) and an oxidizing agent at a temperature of about 250 ° C. At this time, the oxidizing agent was O ₂ , and the thickness of the formed aluminum oxide film was about 16 nm. And sputtering Pt on the aluminum oxide film, the disk-shaped having a diameter of 300 μm The control gate was formed.

Production Example  2: hafnium Oxide (HfO ₂ )of  When used as a blocking insulating film

The n-type silicon substrate was oxidized to form a silicon oxide film of about 6 nm. At a temperature of about 150 ° C., Ge (iC ₄ H ₉ ) ₄ , Sb (iC ₃ H ₇ ) ₃ , and Te (iC ₃ H ₇ ) ₂ are used as Ge precursors, Sb precursors, and Te precursors, respectively. GST nanodots were formed on the silicon oxide film by click PECVD. At this time, the number of cycles was set to 10, 20, 30, 40, and 50 to form GST nanodots. Next, a hafnium oxide film was formed by general atomic layer deposition (ALD) using HfO ^t (C ₄ H ₉ ) (NC ₂ H ₅ CH ₃ ) ₃ and an oxidizing agent at a temperature of about 300 ° C. At this time, the oxidizing agent was O ₃ , and the thickness of the formed hafnium oxide film was about 40 nm. Pt was sputtered on the hafnium oxide film to form a disc shaped control gate having a diameter of 300 μm.

In order to compare the characteristics of the charge trap flash memory storage devices manufactured in Preparation Examples 1 and 2, two comparative examples without GST nano-dots were prepared, and the charge trap flash memory storage devices prepared in Preparation Examples 1 and 2 were prepared. It is shown in Table 1 with.

TABLE 1

Sample 1-1

SiO ₂ (6 nm) / GST (cycle recovery: 10) / Al ₂ O ₃ (16 nm)
Sample 1-2

SiO ₂ (6 nm) / GST (cycles: 20 cycles) / Al ₂ O ₃ (16 nm)

Sample 1-3

SiO ₂ (6 nm) / GST (cycle recovery: 30 times) / Al ₂ O ₃ (16 nm)

Sample 1-4

SiO ₂ (6 nm) / GST (40 cycles) / Al ₂ O ₃ (16 nm)

Sample 1-5

SiO ₂ (6 nm) / GST (cycle recovery: 50 cycles) / Al ₂ O ₃ (16 nm)

Sample 2-1

SiO ₂ (6 nm) / GST (cycles: 10 cycles) / HfO ₂ (40 nm)

Sample 2-2

SiO ₂ (6 nm) / GST (20 cycles) / HfO ₂ (40 nm)

Sample 2-3

SiO ₂ (6 nm) / GST (cycle recovery: 30 times) / HfO ₂ (40 nm)

Sample 2-4

SiO ₂ (6 nm) / GST (40 cycles) / HfO ₂ (40 nm)

Sample 2-5

SiO ₂ (6 nm) / GST (cycles: 50 cycles) / HfO ₂ (40 nm)

Comparative Example 1

SiO ₂ (6 nm) / Al ₂ O ₃ (16 nm)

Comparative Example 2

SiO ₂ (6nm) / HfO ₂ (40nm)

6A is a graph showing the current density according to the gate voltage of Sample 1-1, and FIG. 6B is a graph showing the current density according to the gate voltage of Sample 2-1.

6A and 6B, when the gate voltage is -10 V to 10 V, since the leakage current is less than 10 ^-7 A / cm ² , both the case of using an aluminum oxide film and a hafnium oxide film as a blocking insulating film are programmed. It can be seen that the leakage current is not a big problem when performing or erasing.

7A and 7B are graphs showing capacitance according to voltage. FIG. 7A is a graph showing capacitance when the aluminum oxide film is used as the blocking insulating film, and the capacitance according to the voltages of Samples 1-1 to 1-5 and Comparative Example 1. FIG. 7B is a case where the hafnium oxide film is used as the blocking insulating film. , Graphs showing capacitances according to voltages of Samples 2-1 to 2-5 and Comparative Example 2. FIG.

As shown in FIGS. 7A and 7B, the samples 1-1 to GST nanopoints are present compared to the mobility (V _fb shift) of the flat band voltages V _fb of Comparative Examples 1 and 2 where the GST nanopoints do not exist. It can be seen that the mobility of the flat band voltages of Samples 1-5, Samples 2-1 to 2-5 is greater. Mobility of the flat-band voltage ΔV _fb is _fb = V _fb ⁺ ΔV - is represented by ^- V _fb. Where V _fb ⁺ is the _flatband voltage during the sweep of the voltage from negative to positive, and V _fb ^- is the _flatband voltage during the sweep of the voltage from positive to negative. ΔV _fb according to the number of GST deposition cycles is shown in FIG. 8.

Referring to FIGS. 7A, 7B, and 8, the reason why ΔV _fb increases when GST nanopoints are present is that charges are trapped by the interface between the GST nanopoints and the blocking insulating layer. Therefore, as the number of GST deposition cycles increases, the area of the interface between the GST nano-dots and the blocking insulating layer increases, and the amount of charge trapping increases. As the number of GST deposition cycles increases, the increase in ΔV _fb increases.

At this time, it can be seen that the case where the aluminum oxide film is used as the blocking insulating film is larger than the case where the hafnium oxide film is used, and the increase in ΔV _fb is greater. Since the blocking insulating film is deposited before the GST nanodots are deposited, it is irrelevant to the blocking insulating film. Thus, if the trap site where the charge is trapped is present inside the GST nanopoint or at the interface between the GST nanopoint and the silicon oxide film which is the tunneling insulating film, ΔV _fb will be the same regardless of the blocking insulating film. However, when the blocking insulating film is an aluminum oxide film, the ΔV _fb is larger than that of the hafnium oxide film, which means that the trap site exists at the interface between the GST nanopoint and the blocking insulating film. Therefore, as compared with forming the GST in the form of a continuous thin film, forming in the form of nano dots as in this embodiment can increase the interface area between the blocking insulating films, thereby increasing the trap site.

The coverage and volume of the GST nanodots according to the number of GST deposition cycles are shown in FIG. 9.

8 and 9, the change in ΔV _{fb and} the change in coverage according to the number of GST deposition cycles are similar. In contrast, the change in ΔV _fb and the volume change of the GST nanodots with the number of GST deposition cycles are not similar. This means that the coverage of GST nanodots, rather than the volume of GST nanodots, influences the change in ΔV _fb . That is, the trap site where the charge is trapped does not exist inside the GST nano dot but between the interface between the GST nano dot and the blocking insulating film. N _it representing the interface trap density present at the interface between the GST nanodots and the blocking insulating film can be derived by the following equation.

qN _it = C _BO ΔV _fb

Where q is the basic charge amount and C _BO is the capacitance value of the blocking insulating film. From the above formula, when the blocking insulating film is an aluminum oxide film, the interface trap density N _it is 1.85 × 10 ¹³ cm ⁻² , and when the blocking insulating film is a hafnium oxide film, the interface trap density N _it is 1.11 × 10 ¹³ cm ^{−. 2}

The reason why the interfacial trap density with the GST nanopoints differs depending on the blocking insulating film is not due to the material of the blocking insulating film, but is due to the different deposition methods of the aluminum oxide film and the hafnium oxide film. In this embodiment, the aluminum oxide film is formed using plasma, while the hafnium oxide film is formed without using plasma. In this embodiment, the aluminum oxide film is formed at a relatively lower temperature than the hafnium oxide film. Therefore, in order to increase the interfacial trap density between the GST nano dot and the blocking insulating film, the blocking insulating film is preferably formed using plasma or at a low temperature of 300 ° C. or lower.

10A and 10B are graphs showing ΔV _fb over time. FIG. 10A is a case where an aluminum oxide film is used as a blocking insulating film, and FIG. 10B is a case where a hafnium oxide film is used as a blocking insulating film.

Referring to FIGS. 10A and 10B, it can be seen that ΔV _fb is kept constant for 10 ⁴ seconds regardless of the material of the blocking insulating layer in both programming and erasing. This result means that the resistance trap flash memory device of this embodiment has excellent resistance retention characteristics.

Although the preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific preferred embodiments described above, and the present invention belongs to the present invention without departing from the gist of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such changes are within the scope of the claims.

1 is a view showing the structure of a preferred embodiment of a charge trap flash memory device according to the present invention.

FIG. 2A is a cross-sectional transmission electron microscopy (TEM) photograph when the tunneling insulating layer is a silicon oxide layer (SiO ₂ ).

FIG. 2B is a cross-sectional transmission electron micrograph when the tunneling insulating film is formed of a silicon oxide film and a titanium oxide film (TiO ₂ ) double layer.

3A is a diagram illustrating an XPS graph when the tunneling insulating film is a silicon oxide film (SiO ₂ ).

FIG. 3B is a diagram illustrating an XPS graph when the tunneling insulating film is formed of a silicon oxide film and a titanium oxide (TiO ₂ ) double layer.

4 is a plan-view scanning electron microscopy (SEM) photograph of GST deposited by cyclic plasma enhanced chemical vapor deposition on a silicon oxide film.

5 is a cross-sectional transmission electron micrograph of a laminated structure in which a GST nanodot is formed on an silicon oxide film and an aluminum oxide film (Al ₂ O ₃ ) is formed.

6A and 6B are graphs showing current densities according to gate voltages. FIG. 6A is a case where an aluminum oxide film is used as a blocking insulating film, and FIG. 6B is a case where a hafnium oxide film is used as a blocking insulating film.

7A and 7B are graphs showing capacitance according to voltage. FIG. 7A is a case where an aluminum oxide film is used as a blocking insulating film, and FIG. 7B is a case where a hafnium oxide film is used as a blocking insulating film.

8 is a graph showing ΔV _fb according to the number of GST deposition cycles.

9 is a graph showing the coverage and volume of the GST nanodots according to the number of GST deposition cycles.

10A and 10B are graphs showing ΔV _fb over time. FIG. 10A is a case where an aluminum oxide film is used as a blocking insulating film, and FIG. 10B is a case where a hafnium oxide film is used as a blocking insulating film.

Claims (9)

A semiconductor substrate having a source region and a drain region separated by a channel region; A tunneling insulating layer formed on the channel region of the semiconductor substrate; Chalcogenide-based compound nanodots formed on the tunneling insulating film; A blocking insulating film formed on the tunneling insulating film so that the chalcogenide-based compound nanopoints are covered; And And a control gate formed on the blocking insulating film. The method of claim 1, And a trap site for trapping charge at an interface between the nano dot and the blocking insulating film. The method of claim 2, And the blocking insulating film is formed by a deposition method using plasma in order to increase the density of the trap sites formed at the interface between the nano-dots and the blocking insulating film. The method of claim 2, And the blocking insulating film is formed at a temperature of 300 ° C. or less to increase the density of trap sites formed at the interface between the nano dot and the blocking insulating film. The method of claim 1, The tunneling insulating layer is made of a material that reacts with the nano-dots to form a reactant such that the nano-dots are grown in an island form on the tunneling insulating layer by suppressing nucleation on the surface of the tunneling insulating layer when the nano-dots are formed. Charge trap flash memory device. The method according to any one of claims 1, 2 and 5, The chalcogenide-based compound is GST (Ge ₂ Sb ₂ Te ₅ ), characterized in that the charge trap flash memory device. The method of claim 6, The GST is formed by cyclic plasma enhanced chemical vapor deposition (cyclic plasma enhanced chemical vapor deposition, cyclic PECVD), the charge trap flash memory device. The method according to any one of claims 1, 2 and 5, And the tunneling insulating layer is made of SiO ₂ . The method according to any one of claims 1, 2 and 5, And the blocking insulating layer is made of Al ₂ O ₃ or HfO ₂ .

Images