KR101002114B1 - Flash memory device and manufacturing method thereof - Google Patents

Abstract

A flash memory device according to an embodiment includes an ONO film pattern formed on a semiconductor substrate and a first polysilicon pattern formed on the ONO film pattern; An oxide film formed on the semiconductor substrate including the ONO film pattern and the first polysilicon pattern; A nitride film pattern disposed between the ONO film and the oxide film; And a second polysilicon pattern formed on the oxide layer in contact with a sidewall of the first polysilicon pattern.

A method of manufacturing a flash memory device according to an embodiment may include forming a stack of an ONO film pattern, a first polysilicon pattern, and a hard mask pattern on a semiconductor substrate; Forming a first nitride film pattern and an oxide film on the semiconductor substrate including the ONO film pattern, the first polysilicon pattern, and the hard mask pattern; Forming a second polysilicon pattern on one sidewall of the first polysilicon pattern on the first nitride film pattern and the oxide film; And removing a hard mask pattern on the semiconductor substrate on which the second polysilicon pattern is formed, wherein the first nitride layer pattern is disposed between the ONO layer pattern and the oxide layer.

Nonvolatile memory

Description

Flash memory device and manufacturing method {Flash memory device and Manufacturing method the same}

Embodiments relate to a flash memory device and a method of manufacturing the same.

The flash memory device is a nonvolatile storage medium in which stored data is not damaged even when the power is turned off. However, the flash memory device has a relatively high processing speed for writing, reading, and deleting data.

Accordingly, flash memory devices are widely used for data storage of bios, set-top boxes, printers, network servers, and the like of PCs, and are recently used in digital cameras and mobile phones.

In flash memory devices, semiconductor devices using a silicon-oxide-nitride-oxide-silicon (SONOS) structure are used.

A SONOS memory device is a charge trap type device that uses a mechanism in which charge tunnels a thin oxide film on silicon by a gate voltage, and uses a mechanism of injecting or relaxing from a trap in a silicon nitride film instead of a floating gate using conventional polycrystalline silicon. .

The flash memory device includes a select gate and a memory gate, and an oxide film is disposed between the select gate and the memory gate, so that the select gate and the memory gate cannot be simultaneously controlled.

In the case of forming a contact, if the oxide film formed between the select gate and the memory gate is ignored, the contact uniformity may be affected, thereby affecting the reliability of the flash memory.

The embodiment provides a flash memory device capable of increasing the reliability of a memory device by removing an oxide film present between the memory gate and the select gate, and a method of manufacturing the same.

A flash memory device according to an embodiment includes an ONO film pattern formed on a semiconductor substrate and a first polysilicon pattern formed on the ONO film pattern; An oxide film formed on the semiconductor substrate including the ONO film pattern and the first polysilicon pattern; A nitride film pattern disposed between the ONO film and the oxide film; And a second polysilicon pattern formed on the oxide layer in contact with a sidewall of the first polysilicon pattern.

A method of manufacturing a flash memory device according to an embodiment may include forming a stack of an ONO film pattern, a first polysilicon pattern, and a hard mask pattern on a semiconductor substrate; Forming a first nitride film pattern and an oxide film on the semiconductor substrate including the ONO film pattern, the first polysilicon pattern, and the hard mask pattern; Forming a second polysilicon pattern on one sidewall of the first polysilicon pattern on the first nitride film pattern and the oxide film; And removing a hard mask pattern on the semiconductor substrate on which the second polysilicon pattern is formed, wherein the first nitride layer pattern is disposed between the ONO layer pattern and the oxide layer.

In the flash memory device and the method of manufacturing the same according to the embodiment, the oxide film does not exist between the memory gate and the selection gate, and is formed to be in direct contact with each other, so that the selection gate and the memory gate may be simultaneously controlled during operation of the flash memory device. .

Hereinafter, embodiments will be described with reference to the accompanying drawings.

In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure may be "on" or "under" the substrate, each layer (film), region, pad or pattern. "On" and "under" include both "directly" or "indirectly" formed through another layer, as described in do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

1 to 8 are process cross-sectional views of a flash memory device according to an embodiment.

As shown in FIG. 1, an oxide-nitride-oxide (ONO) film pattern including a first oxide film pattern 21, a first nitride film pattern 22, and a third oxide film pattern 23 on a semiconductor substrate 10. 20, the first polysilicon pattern 31 and the hard mask pattern 40 are formed.

The ONO film pattern 20 and the first polysilicon pattern 31 may include an ONO film, a first polysilicon film, and a hard mask pattern 40 formed of a first oxide film, a first nitride film, and a second oxide film on the semiconductor substrate 10. ) Is formed by performing a first etching process using the hard mask pattern 40 as a mask.

The hard mask pattern 40 may be formed of an oxide layer, and the hard mask pattern 40 is not limited thereto and may be used as long as the material does not react with polysilicon.

In this case, the first polysilicon pattern 31 may be a memory gate.

As shown in FIG. 2, a second nitride film 45 is formed on the semiconductor substrate 10 including the ONO film pattern 20, the first polysilicon pattern 31, and the hard mask pattern 40. do.

Subsequently, as shown in FIG. 3, a second etching process is performed on the second nitride film 45 to form the second nitride film 45 on the sidewalls of the ONO film pattern 20, the first polysilicon pattern 31, and the hard mask pattern 40. The two nitride film pattern 50 is formed.

The second etching process may be an anisotropic etching process.

As shown in FIG. 4, a third oxide film 60 is formed on the semiconductor substrate 10.

The third oxide film 60 may be formed by a thermal oxidation process.

By forming the third oxide film 60, a portion of the second nitride film pattern 50 may be disposed between the ONO film pattern 20 and the third oxide film 60.

Next, as shown in FIG. 5, the exposed region of the second nitride film pattern 50 is removed to form a third nitride film pattern 55 formed between the ONO film pattern 20 and the third oxide film 60. do.

The third nitride layer pattern 55 may be formed by performing a third etching process on the semiconductor substrate 10, and the third etching process may be performed by a wet etching process using phosphoric acid.

The exposed region of the second nitride film pattern 50 is removed by a wet etching process as a third etching process, and a third nitride film pattern 55 is formed between the ONO film pattern 20 and the third oxide film 60.

In this case, the height of the third nitride film pattern 55 may be the same as the height of the third oxide film 60.

6, second polysilicon patterns 61 are formed on both sidewalls of the first polysilicon pattern 31.

The second polysilicon pattern 61 may be formed by forming a second polysilicon film on the entire surface of the semiconductor substrate 10 and then performing a fourth etching process.

In this case, a side of the second polysilicon pattern 61 is in contact with the first polysilicon pattern 31, and a lower surface of the second polysilicon pattern 61 is formed of the second nitride film pattern 55 and the third oxide film 60. It can be contacted.

The fourth etching process may be an anisotropic etching process, and the height of the second polysilicon pattern 61 may be adjusted during the fourth etching process.

However, the height of the second polysilicon pattern 61 may be formed to be the same as the height of the first polysilicon pattern 31 in consideration of a process such as a contact to be formed later, but is not limited thereto. It may be formed higher or lower than the height of the one polysilicon pattern 31.

The second polysilicon pattern 61 may be a select gate.

At this time, the third nitride film pattern 55 is formed by removing a portion of the second nitride film pattern 50 on the sidewalls of the ONO film pattern 20, the first polysilicon pattern 31, and the hard mask pattern 40. Since the second polysilicon film is formed immediately afterwards, no oxide film is formed between the first polysilicon pattern 31 and the second polysilicon pattern 61.

That is, since the first polysilicon pattern 31 and the second polysilicon pattern 61 are formed in direct contact with each other, the memory gate and the selection gate are formed in direct contact with each other, so that the selection gate and the memory gate are simultaneously controlled during operation of the flash memory device. can be controlled.

Subsequently, as shown in FIG. 7, a part of the second polysilicon pattern 61 formed on both sides of the first polysilicon pattern 31 is removed, so that only the second polysilicon pattern 31 is formed on only one side of the first polysilicon pattern 31. The silicon pattern 61 is left.

At this time, the photoresist pattern 1 is formed on the semiconductor substrate 10 so as to cover only one side of the second polysilicon pattern 61, and a fifth etching process is performed to one side of the first polysilicon pattern 31. Only the second polysilicon pattern 61 may be left.

As shown in FIG. 8, the photoresist pattern 1 and the hard mask pattern 40 may be removed.

Although not shown in the drawings, source and drain regions may be formed later, and an interlayer insulating film and a contact may be further formed.

8 is a cross-sectional view of a flash memory device according to an embodiment.

As shown in FIG. 8, the flash memory device according to the embodiment may include an ONO film pattern 20 formed on the semiconductor substrate 10 and a first polysilicon pattern 31 formed on the ONO film pattern 20; A third oxide film 60 formed on the semiconductor substrate 10 including the ONO film pattern 20 and the first polysilicon pattern 31; A third nitride film pattern 55 disposed between the ONO film pattern 20 and the third oxide film 60; And a second polysilicon pattern 61 formed on the third oxide layer 60 in contact with the sidewall of the first polysilicon pattern 31.

The second polysilicon pattern 61 is in contact with the side surface of the first polysilicon pattern 31, and the lower portion of the second polysilicon pattern 61 is in contact with the third nitride film pattern 55 and the third oxide film 60.

The height of the third nitride film pattern 55 may be formed to be the same as the height of the third oxide film 60.

The second polysilicon pattern 61 may be formed only on one side of the first polysilicon pattern 31.

The first polysilicon pattern 31 may be a memory gate, and the second polysilicon pattern 61 may be a selection gate.

As described above, the flash memory device and the method of manufacturing the same according to the embodiment do not have an oxide film between the memory gate and the selection gate, and are formed to be in direct contact, so that the selection gate and the memory gate are simultaneously controlled during operation of the flash memory device. can be controlled.

Although the above has been described with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should not be exemplified above unless they depart from the essential characteristics of the present embodiments. It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 8 are process cross-sectional views of a flash memory device according to an embodiment.

Claims (11)

An ONO film pattern formed on the semiconductor substrate and a first polysilicon pattern formed on the ONO film pattern; An oxide film formed on the semiconductor substrate including the ONO film pattern and the first polysilicon pattern; A nitride film pattern disposed between the ONO film and the oxide film; And And a second polysilicon pattern formed on the oxide layer in contact with a sidewall of the first polysilicon pattern. The method of claim 1, The second polysilicon pattern is in side contact with the first polysilicon pattern, And a lower portion of the second polysilicon pattern is in contact with the nitride layer pattern and the oxide layer. The method of claim 1, And a height of the nitride film pattern and a height of the oxide film are the same. The method of claim 1, And the second polysilicon pattern is formed only on one side of the first polysilicon pattern. Forming a stack of an ONO film pattern, a first polysilicon pattern, and a hard mask pattern on the semiconductor substrate; Forming a first nitride film pattern and an oxide film on the semiconductor substrate including the ONO film pattern, the first polysilicon pattern, and the hard mask pattern; Forming a second polysilicon pattern on one sidewall of the first polysilicon pattern on the first nitride film pattern and the oxide film; And Removing a hard mask pattern on the semiconductor substrate on which the second polysilicon pattern is formed; And the first nitride film pattern is disposed between the ONO film pattern and an oxide film. The method of claim 5, Forming a laminate of the ONO film pattern, the first polysilicon pattern and the hard mask pattern on the semiconductor substrate, Forming an ONO film and a first polysilicon film on the semiconductor substrate; Forming a hard mask pattern on the ONO layer and the first polysilicon layer; And And etching the hard mask pattern using a mask to form an ONO film pattern and a first polysilicon film pattern on the semiconductor substrate. The method of claim 5, Forming the first nitride film pattern and the oxide film on the semiconductor substrate including the ONO film pattern, the first polysilicon pattern and the hard mask pattern, Forming a second nitride film pattern on sidewalls of the ONO film pattern, the first polysilicon pattern, and the hard mask pattern; Forming an oxide film on the semiconductor substrate including the second nitride film pattern; And Performing a first etching process on the semiconductor substrate including the second nitride layer pattern and the oxide layer, removing the exposed second nitride layer pattern, and forming a first nitride layer pattern on a side surface of the ONO layer pattern Method of manufacturing a flash memory device. The method of claim 7, wherein Forming a second nitride film pattern on sidewalls of the ONO film pattern, the first polysilicon pattern, and the hard mask pattern may include: Forming a nitride film on an entire surface of the semiconductor substrate including the ONO film pattern, a first polysilicon pattern, and a hard mask pattern; And Performing a second etching process on the nitride film to form a second nitride film pattern on sidewalls of the ONO film pattern, the first polysilicon pattern, and the hard mask pattern. The method of claim 8, The first etching process is a wet etching process, And the second etching process is performed as an anisotropic etching process. The method of claim 5, The second polysilicon pattern is in side contact with the first polysilicon pattern, A lower portion of the second polysilicon pattern is in contact with the first nitride film pattern and the oxide film manufacturing method of a flash memory device comprising. The method of claim 5, And a height of the first nitride film pattern and a height of the oxide film are the same.

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