KR101008379B1 - Thin film transistor and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a thin film transistor, wherein the thin film transistor includes a gate electrode, a source electrode and a drain electrode formed on a layer different from the gate electrode, a gate insulating film formed between the gate electrode and the source electrode and the drain electrode, and the And a semiconductor formed at a position overlapping with the gate electrode through a gate insulating layer, wherein the gate electrode, the source electrode, and the drain electrode include the same soluble material. As a result, all the films of the thin film transistor are formed using an inkjet printing method performed in an air environment without a separate deposition process or an etching process, thereby reducing manufacturing time and manufacturing cost, and using the same organic material under the same conditions, Since source and drain electrodes are formed, manufacturing costs and manufacturing time are further reduced.

Inkjet, Inkjet Printing, Organic Thin Film Transistor, OTFT, Surface Treatment, PVP, OTFT, Solution Process

Description

Thin film transistor and its manufacturing method {THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a thin film transistor and a method of manufacturing the same.

The present invention is derived from the research conducted as part of the IT growth engine technology development project of the Ministry of Information and Communication and the Ministry of Information and Communication Research and Development (Task Management No .: 2006-S-023-02, Task name: RFID system advancement technology development).

Currently, most thin film transistors are inorganic thin film transistors manufactured using inorganic materials such as amorphous silicon or polycrystalline silicon. Since the inorganic thin film transistor has to be manufactured in an environment such as high vacuum, high temperature, and high clean state, high manufacturing cost is required.

On the other hand, an organic thin film transistor manufactured using an organic material has characteristics such as light weight and thin film, and low manufacturing cost due to a simple manufacturing process. In addition, since the organic thin film transistor may be manufactured in a low temperature environment, the organic thin film transistor may be formed using a flexible substrate such as plastic, and thus may be used in an RFID (radio frequency identification) tag called a electronic tag or a flexible display device. . Therefore, active research is being conducted as a next-generation device to replace the inorganic thin film transistor.

In general, the organic thin film transistor may be manufactured by vacuum deposition of a single molecule such as pentacene or a solution process.

The vacuum deposition method using a single molecule can produce an organic thin film transistor having properties similar to or better than those of an inorganic thin film transistor, but because of the use of expensive vacuum deposition equipment, the manufacturing cost increases and the manufacturing process is complicated. Become.

Meanwhile, the solution process uses a polymer material, and includes a self-assemble monolayer (SAM), a coating method, and a printing method. When manufacturing a thin film transistor using such a solution process, instead of forming all the layers of the thin film transistor through a solution process, some layers are formed using a solution process and some layers are formed using a vacuum deposition method. This is common.

As such, not all layers of the thin film transistor are formed in the solution process, which makes the manufacturing process complicated. In addition, since the environmental conditions of the solution process method and vacuum deposition method are different from each other, a lot of equipment investment costs are required.

The technical problem to be achieved by the present invention is to reduce the manufacturing cost of the thin film transistor, and to simplify the manufacturing process.

Another technical object of the present invention is to improve the operating characteristics of the thin film transistor.

A thin film transistor according to an aspect of the present invention may include a gate electrode, a source electrode and a drain electrode formed on a layer different from the gate electrode, a gate insulating film formed between the gate electrode and the source electrode and the drain electrode, and the gate insulating film. And a semiconductor formed at a position overlapping with the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode include the same soluble material.

According to an aspect of the present invention, a thin film transistor includes a gate electrode, a source electrode and a drain electrode formed on a layer different from the gate electrode, a gate insulating film formed between the gate electrode and the source electrode and the drain electrode, and a surface of the gate insulating film. And a semiconductor formed at a position overlapping with the gate electrode through the surface treatment film.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, using a first solution on a substrate, forming a gate electrode in a solution process under a first condition. Forming a source electrode and a drain electrode by the solution process under the first condition, and forming a gate insulating film by the solution process under the second condition by using a second solution between the gate electrode and the source electrode and the drain electrode And forming a semiconductor to overlap the gate electrode in a solution process under a third condition using a third solution, wherein the solution processes are all the same solution process.

According to another aspect of the present invention, a diode includes a gate electrode, a source electrode and a drain electrode formed on a layer different from the gate electrode, a gate insulating film formed between the gate electrode and the source electrode and the drain electrode, and the gate insulating film. And a semiconductor formed at a position overlapping with the gate electrode, wherein the gate insulating film is formed on a portion of the gate electrode, and a portion where the gate insulating film is not formed is directly connected to the drain electrode.

As such, since all the films of the organic thin film transistor are formed by using an inkjet printing method performed in an air environment without a separate deposition process or an etching process, manufacturing time and manufacturing cost are reduced, and the gate electrode is formed using the same organic material under the same conditions. By forming the source and drain electrodes, the manufacturing cost and manufacturing time are further reduced.

In addition, by treating the gate insulating film to reduce the contact angle of the gate insulating film to make the flatness of the solution applied thereon, the crystallinity of the organic semiconductor increases and the operating characteristics of the organic thin film transistor are improved.

In addition, since the gate insulating film is formed only on a desired portion of the gate electrode instead of the entire surface of the gate electrode through an inkjet printing method, a source or drain electrode formed on the gate electrode and another layer without a separate via hole through a separate etching process and the like. The direct connection of is possible, further reducing manufacturing time and manufacturing costs.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise. In addition, in order to clearly express the various layers and regions in the drawings, the thickness is shown enlarged. Like parts are designated by like reference numerals throughout the specification. Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, an organic thin film transistor according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a layout view of an organic thin film transistor according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the organic thin film transistor of FIG. 1 taken along line II-II.

1 and 2, the gate electrode 20 is formed on the substrate 10. The gate electrode 20 is connected to a gate line (not shown) extending in one direction of the substrate 10 and receives a gate signal.

In the present embodiment, the substrate 10 uses polyethylene-naphthelate (PEN) and polyethyleneterephehalate (PET), but may be made of plastic, glass, or the like, such as polyimide, polycarbonate, polyethersulphone, or the like. Silicon and the like can be used.

The gate insulating film 30 is formed in a desired portion of the gate electrode 20. The gate insulating layer 30 may be made of an organic insulating material, and may be made of polyvinyl phenol or a derivative thereof, a polyimide compound, a polyvinyl alcohol compound, or a polyfluorane compound. It is preferable to contain soluble high molecular compounds, such as a compound and parylene. An example of such an organic insulating material is PVP ink produced by mixing about 15wt% of poly 4-vinylphenol (PVP) in a propylene glycol monomethyl ether acetate (PGMEA) solvent. Can be.

The source electrode 40 and the drain electrode 50 are formed on the gate insulating film 30. The source electrode 40 and the drain electrode 50 face each other with a predetermined interval around the gate electrode 20.

The source electrode 40 is connected to a data line (not shown) formed in a direction crossing the gate line and receives a data signal. The drain electrode 50 is separated from the data line and may be island-shaped. A portion (hereinafter, referred to as a "channel region") between the source electrode 40 and the drain electrode 50, which are spaced apart from each other with respect to the gate electrode 20, some source electrode 40 and the drain electrode near the channel region ( The organic semiconductor 60 is formed on 50.

The organic semiconductor 60 may include a high molecular compound or a low molecular compound dissolved in an aqueous solution or an organic solvent. The organic semiconductor 60 may include a derivative including a substituent of pentacene. In this embodiment, the solution used to form the organic semiconductor 60 is 6,13-bis (triisopropylsilylethynyl) pentacene (6) in an organic solvent of chlorobensene and anisole. , 13-bis (triisopropylsilylethynyl) pentacene (hereinafter referred to as 'TIPS pentacene') is prepared by mixing at a ratio of about 1wt%, or P3HT (poly (3-hexylthoipene)) can be used.

In this embodiment, the gate electrode 10, the gate insulating film 20, the source electrode 40 and the drain electrode 50, and the organic semiconductor 60 is an inkjet printing method performed in a normal temperature and atmospheric pressure environment, that is, an atmospheric environment It is formed through the solution process of (inkjet printing). That is, the solution is added dropwise to the site to form a desired pattern. At this time, a bank for preventing the solution from flowing to other parts than the desired part is not necessary. Dropping conditions are ensured so that the droplets are maintained at about 50 pl or less, and the spreadability of the dropped ink solution can be reduced as much as possible by controlling the surface energy, so that a fine pattern of about 100 μm or less can be formed without forming a separate partition wall. Do.

The gate electrode 20, the source electrode 40, and the drain electrode 50 are all formed of the same organic material. An example of an organic material used to form the gate electrode 20, the source electrode 40, and the drain electrode 50 in this embodiment is a conductive nano silver ink, but other organic materials may be used.

However, unlike the present embodiment, at least one or all of the gate electrode 20, the source electrode 40, and the drain electrode 50 may be made of different conductive inks. For example, a conductive electronic ink such as PEDOT: PSS, Au ink, Cu ink, or the like may be used.

Next, the manufacturing method of the organic thin film transistor shown in FIG. 2 is demonstrated.

First, an organic material such as conductive nano silver ink is dropped on the substrate 10 by inkjet printing to form the gate electrode 20. That is, a conductive nano silver ink is dropped into the corresponding portion on the substrate 10 with a line width of about 20 μm to about 200 μm, preferably about 100 μm and a thickness of about 300 nm to about 500 nm, preferably about 360 nm. After that, the gate electrode 10 is formed by drying at about 120 ° C. to 150 ° C., preferably at about 140 ° C. for about 2 minutes to about 30 minutes, and preferably about 10 minutes. In this case, the sheet resistance of the gate electrode 20 may be about 1.4 Ω / sq to about 20 Ω / sq or less.

Next, an organic insulating material such as PVP ink is dropped on the gate electrode 20 by an inkjet printing method to form a PVP pattern for coating a portion of the gate electrode 20. In this case, the droplet of the PVP ink may have an average diameter of about 20 μm to about 200 μm, preferably about 44.26 μm, and a volume of about 20 pl to about 50 pl, preferably about 45.41 pl. The PVP pattern is then dried at about 100 ° C. to about 110 ° C., preferably at about 100 ° C. for about 2 minutes to about 15 minutes, preferably about 10 minutes to evaporate the solvent, and then again at about 180 ° C. to about The PVP pattern is cured at 220 ° C., preferably at about 200 ° C. for about 5 minutes to about 30 minutes, preferably about 20 minutes, to complete the gate insulating film 30.

Next, an organic material is dropped on the corresponding portion on the gate insulating layer 30 by inkjet printing to form the source electrode 40 and the drain electrode 50. At this time, the dropped organic material flows to the side surface and is applied to the side surface as well as the top of the gate insulating film 30. As described above, the source electrode 40 and the drain electrode 50 are spaced apart from each other by a predetermined distance with respect to the gate electrode 20 formed in the lower layer. In this case, the organic material used may be the same as the organic material for forming the gate electrode 20, and as an example, a conductive nano silver ink may be used.

Inkjet printing conditions and curing conditions for forming the source electrode 40 and the drain electrode 50 are the same as when the gate electrode 20 is formed. Therefore, the conductive nano silver ink is dropped on the gate insulating film 30 by ink jet printing at predetermined intervals, and then dried at about 140 ° C. for about 10 minutes to form the source electrode 40 and the drain electrode 50. At this time, the allowable drying temperature is about 130 ℃ to about 150 ℃, the allowable drying time may be about 10 minutes to about 60 minutes.

At this time, the line width and thickness of the source electrode 40 and the drain electrode 50 to be formed may also be the same as those of the gate electrode 20. Thus, the sheet resistance of each of the formed source electrode 40 and the drain electrode 50 may also be the same as the sheet resistance of the gate electrode 20.

Next, an organic semiconductor solution, such as an organic material, is dropped by an inkjet printing method so as to overlap the gate electrode 20 on the gate insulating film 20 exposed between the source electrode 40 and the drain electrode 50. In this case, the dropped organic semiconductor solution is applied not only to the exposed gate insulating film 30 but also to some of the source electrode 40 and the drain electrode 50 near the exposed gate insulating film 20.

In this case, the organic semiconductor solution may be prepared by mixing TIPS pentation with an organic solvent such as chlorobenzene and anisole in a ratio of about 1 wt% to 3 wt%, preferably about 1 wt%. At this time, the average diameter of the ink droplets may be about 25 μm to about 50 μm, preferably about 35.26 μm, and the average volume may be about 20 pl to about 50 pl, preferably about 21.94 pl.

Next, the organic semiconductor solution is dried at about 150 ° C. to about 170 ° C. to form the organic semiconductor 60. In this case, the thickness of the organic semiconductor 60 to be formed may be about 50nm to about 100nm.

Accordingly, one gate electrode 20, one source electrode 40, and one drain electrode 50 form one thin film transistor together with the organic semiconductor 60, and a channel of the thin film transistor is a source electrode. It is formed in the organic semiconductor 60 between the 40 and the drain electrode 50.

Although not shown in FIGS. 1 and 2, a desired PVP ink is dripped to electrically insulate the gate line formed on the same layer as the gate electrode 20 and the conductive film formed on the upper layer, for example, the data line. The gate insulating layer 30 may be partially formed. As a result, since the gate insulating film 30 is partially formed at the portion where the gate line and the data line cross each other, electrical insulation is performed between the two conductive layers crossing each other.

As such, when the gate electrode 20, the source electrode 40, and the drain electrode 50 are formed using the same organic material, such as nano silver ink, and the organic semiconductor 60 is formed using TIPS pentation, The operation characteristics of the organic thin film transistor will be described with reference to FIGS. 3A and 3B.

3A is a graph of transfer characteristics of an organic thin film transistor manufactured according to an exemplary embodiment of the present invention, and FIG. 3B is a graph of output characteristic of an organic thin film transistor manufactured according to an exemplary embodiment of the present invention.

The channel width of the organic thin film transistor (p-type transistor) having the operating characteristics of FIGS. 3A and 3B was about 145 μm, the channel length was about 5 μm, the charge carrier mobility was about 0.43 cm ² / Vsec and the current The flashing ratio (On / Off) was about 7.35 ^{10 10} and the amount of current in the off state was about 0.118 pA / µm. In addition, the threshold voltage slope SS and the threshold voltage Vth were about 0.51 V / dec and about 2.61 V, respectively.

In FIG. 3A, curves a1 and b1 are curves measuring the amount of current I _DS flowing between the drain electrode and the source electrode when the gate voltage is sequentially changed from about 10V to about -40V, and the curves a2 and b2 are gate voltages. Is a curve showing the amount of current flowing when is sequentially changed from about -40V to about 10V. In this case, a1 and a2 represent the measured current amounts on a linear scale, and b1 and b2 represent the measured current amounts on a log scale.

3B is a graph showing the amount of change of the current IDS flowing between the drain electrode and the source electrode when the gate voltage is maintained at a constant value, and curves c1-c6 respectively represent gate voltages of "0V", "-5V", " It is a graph showing the amount of change of the current IDS flowing between the drain electrode and the source electrode when changing to -10V "," -15V "," -20V "and" -25V ".

As such, the gate electrode 20, the gate insulating film 30, the source electrode 40 and the drain electrode 50 on the substrate using an inkjet printing method performed in an air environment without a separate deposition process or an etching process, and Since the organic semiconductor 60 is formed, manufacturing time and manufacturing cost are reduced, and desired patterns are formed on various substrates such as a flexible substrate.

In addition, since the gate electrode 20, the source electrode 40, and the drain electrode 50 are formed by using a soluble solution made of the same organic material under the same conditions, the manufacturing cost and manufacturing time are further reduced.

Next, an organic thin film transistor according to another exemplary embodiment of the present invention will be described with reference to FIGS. 4 and 5. 4 and 5, the same structural elements as those of the organic thin film transistors shown in FIGS. 1 and 2 and the same functions are denoted by the same reference numerals as those of FIGS. 1 and 2, and detailed descriptions thereof are omitted. do.

4 is a layout view of an organic thin film transistor according to another exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the organic thin film transistor of FIG. 4 taken along a line V-V.

4 and 5, the organic thin film transistor according to another embodiment of the present invention has a structure similar to the organic thin film transistor shown in FIG.

That is, the organic thin film transistor according to another exemplary embodiment of the present invention may include a gate electrode 20 formed on the substrate 10, a gate insulating film 30 formed on a corresponding portion of the gate electrode 20, and corresponding side surfaces thereof, and a gate insulating film 30. Source electrode 40, drain electrode 50, and gate insulating film 30, and some source electrode 40 and organic semiconductor 60 formed on drain electrode 50, respectively.

However, unlike the organic thin film transistor shown in FIG. 1, the organic thin film transistor according to the present exemplary embodiment further includes a surface treatment film 70 formed by treating the exposed surfaces of the substrate 10 and the gate insulating film 20. have.

The surface treatment film 70 may be formed by treating the surface of the exposed substrate 10 and the gate insulating film 20 formed of PVP ink using HMDS (hexamethylene disilazane). Accordingly, after the gate insulating layer 30 is formed, the spin coater is exposed by rotating the spin coater for about 10 seconds to about 60 seconds, preferably about 30 seconds at a rotational speed of about 2000 rpm to about 3000 rpm, preferably about 2500 rpm. After applying the HMDS to the entire surface of the substrate 10 and the gate insulating film 30, the surface treatment by drying for about 2 minutes to about 15 minutes, preferably about 10 minutes at about 100 ℃ to about 110 ℃, preferably about 100 ℃ The film 70 is formed. The thickness of the surface treatment film 70 formed through this process is very thin.

The contact angle of the gate insulating film 30 is reduced by the surface treatment film 70, and the surface of the gate insulating film 30 is hydrophilic. Accordingly, the spreading degree of the organic material, for example, the TIPS pentasion solution, which is dropped on the gate insulating film 30, that is, on the surface treatment film 70 increases, so that the flatness of the dropped solution becomes uniform. Sean's adhesion and crystallinity increase.

With reference to FIG. 6, the change of the contact angle with the solution dripped on the surface treatment film 70 before and after surface treatment of the gate insulating film 30 is looked at.

FIG. 6A illustrates a contact angle θ of the gate insulating film and the TIPS pentation solution dropped thereon when the gate insulating film is not surface-treated with HMDS, and FIG. 6B shows the HMDS of the gate insulating film. In the case of surface treatment with, the contact angle θ between the gate insulating film and the TIPS pentation solution dropped thereon is illustrated.

As shown in FIG. 6A, when the gate insulating film 30 was not surface treated with HMDS, the contact angle θ of the gate insulating film 30 and the TIPS pentation solution dropped thereon was about 73.93 °.

On the contrary, as shown in FIG. 6B, after the surface insulating film 70 is formed by surface treatment of the gate insulating film 30 with HMDS, the gate insulating film 30 and the TIPS pentation solution dropped thereon are formed. The contact angle is about 68.25 degrees, indicating that the contact angle is smaller than before the surface treatment of the gate insulating film 30 with HMDS.

As the contact angle decreases, the degree of spreading of the solution dropped on the gate insulating film 30 increases, thereby increasing the adhesion to the solution dropped on the gate insulating film 30, in particular, the TIPS pentalysis solution, and increasing the surface flatness. The surface is uniform.

In addition, with reference to FIG. 7, the change in crystallinity of the TIPS pentions deposited on the surface treatment film 70 before and after the surface treatment of the gate insulating film 30 using HMDS will be described.

FIG. 7 shows the results of analyzing the crystallinity change of the TIPS pentasion solution dropped on the gate insulating film by using an X-ray diffraction when the gate insulating film is not surface treated with HMDS or when the surface is treated. It is a graph shown.

In FIG. 7, the graph indicated by the dotted line is a graph showing the crystallinity change of the TIPS pentation when the surface of the gate insulating film 30 is treated with HMDS, and the graph indicated by the dotted line is the surface of the gate insulating film 30 by HMDS. It is a graph showing the crystallinity change of the TIPS pentasion when is processed. As can be seen from the two graphs shown in FIG. 7, since the intensity of the TIPS pentaline applied on the gate insulating film 30 after the surface treatment of the gate insulating film 30 with HMDS was greatly increased, the crystallinity of the TIPS pentaline was increased. This can be seen to be greatly improved.

Next, operation characteristics of the organic thin film transistor will be described with reference to FIGS. 8A and 8B.

8A is a graph illustrating transfer characteristics of an organic thin film transistor manufactured according to another exemplary embodiment of the present invention, and FIG. 8B is a graph of output characteristic of an organic thin film transistor manufactured according to another exemplary embodiment of the present invention.

The channel width of the organic thin film transistor having the operating characteristics of FIGS. 8A and 8B was about 145 μm, the channel length was about 5 μm, and the threshold voltage slope SS and the threshold voltage Vth were about 0.34 V / dec, respectively. And about 0.62V.

Similar to FIG. 3A, the curves a11 and b11 measure the amount of current I _DS flowing between the drain electrode and the source electrode when the gate voltage is sequentially changed from about 10V to about -40V, and the a12 and b12 curves are This is a curve showing the amount of current flowing when the gate voltage is sequentially changed from about -40V to about 10V. In addition, a11 and a2 represent the measured amount of current on a linear scale, and b11 and b12 represent the measured amount of current on a log scale.

In addition, similar to FIG. 3B, FIG. 6B is a graph showing the amount of change of the current IDS flowing between the drain electrode and the source electrode when the gate voltage is maintained at a constant value, and the curves c11-c16 respectively represent the gate voltage as "0V". , "-5V", "-10V", "-15V", "-20V", and "-25V" is a graph showing the amount of change of the current IDS flowing between the drain electrode and the source electrode.

Comparing the graph of FIG. 8A with the graph of FIG. 3A, in the off region (0V-10V) of the organic thin film transistor after HMDS surface treatment, the hysteresis characteristic was greatly decreased, and the leakage current amount was greatly reduced. It can be seen that the amount of current in the on) state slightly increases.

Moreover, the charge carrier mobility increased from about 0.43 cm ² / Vsec to about 0.69 cm ² / Vsec when the gate insulating film 30 was not surface treated, and the current flashing ratio was also about 7.35x10 ⁵ . Increased to 1.59 × 10 ⁶ ; In addition, the amount of current in the off state also decreased from about 0.118 pA / µm to about 0.048 pA / µm when the gate insulating film 30 was not surface treated. Therefore, when the gate insulating film 30 is surface-treated using HMDS, it can be seen that the performance of the organic thin film transistor is improved.

As such, due to the surface treatment of the gate insulating film 30, the flatness of the organic semiconductor 60 formed on the gate insulating film 30 is uniform and the crystallinity is increased, thereby improving the operating performance of the channel. Properties have been improved.

Next, an example of a diode manufactured using an organic thin film transistor manufactured according to another embodiment of the present invention will be described with reference to FIGS. 9 and 10.

9 is a layout view of a diode fabricated using an organic thin film transistor manufactured according to another exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view of the organic thin film transistor of FIG. 9 taken along X-X line.

As shown in FIGS. 9 and 10, the structure of the diode is an organic thin film transistor having a gate electrode 20, a gate insulating film 30, a source electrode 40 and a drain electrode 50, and an organic semiconductor 60. In this case, the gate electrode 20 and the drain electrode 50 directly contact each other and are electrically connected to each other.

As described above, since the gate insulating film 30 is formed only on a specific portion of the gate electrode 20, the gate insulating film 30 is not formed during the process of forming the source electrode 40 and the drain electrode 50. A solution for the drain electrode 50 is added dropwise to the desired portion to directly connect the drain electrode 50 and the gate electrode 20. At this time, although the surface treatment film 70 is formed on the gate electrode 20 which is not covered with the gate insulating film 30, since the thickness of the surface treatment film 70 is very thin, the gate electrode 20 and the drain, which is an upper layer thereof, are formed. It does not affect the electrical connection between the electrodes 50.

In this example, a diode fabricated using an organic thin film transistor having a surface treatment film 70 on the exposed substrate 10 and the gate insulating film 30 is illustrated. Alternatively, the organic thin film without the surface treatment film 70 is shown. The present invention can also be applied to transistors, that is, diodes fabricated using the organic thin film transistors shown in FIGS. 1 and 2. In this case, the ink for forming the drain electrode 50 is directly added dropwise to the portion for contact with the gate electrode 20 to directly connect the gate electrode 20 and the drain electrode 50 physically and electrically.

As such, a portion in which the gate insulating layer 30 is not formed without a separate photo process and an etching process for forming a via hole or the like for electrically connecting the gate electrode 20 and the drain electrode 50. The solution for forming the drain electrode 50 is added dropwise and directly connected to the drain electrode 50, thereby simplifying the manufacturing process and reducing the manufacturing cost.

In addition, since a separate visual process for forming a via hole is not performed, a phenomenon in which the threshold voltage of the device moves in a positive voltage direction due to plasma may be prevented when etching the gate insulating film through a plasma process to form a via hole. There is an advantage to simplify the circuit structure.

In the present exemplary embodiment, the organic thin film transistor having the lower gate structure in which the gate electrode is lower than the source electrode and the drain electrode has been described. However, another type of organic thin film transistor, for example, the gate electrode may be a source electrode and a drain electrode. It can also be applied to organic thin film transistors with an upper gate structure in the upper layer than the drain electrode.

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a layout view of an organic thin film transistor according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the organic thin film transistor of FIG. 1 taken along the line II-II.

3A is a graph illustrating a transfer characteristic of an organic thin film transistor manufactured according to an exemplary embodiment of the present invention.

3B is a graph illustrating output characteristics of an organic thin film transistor manufactured according to an exemplary embodiment of the present invention.

4 is a layout view of an organic thin film transistor according to another exemplary embodiment of the present invention.

5 is a cross-sectional view of the organic thin film transistor of FIG. 4 taken along the line V-V.

FIG. 6 shows the contact angles between the gate insulating film and the TIPS pentation solution dropped thereon when the gate insulating film is not surface treated with HMDS and when the surface is treated.

FIG. 7 is a graph illustrating a result of analyzing the crystallinity change of the TIPS pentagenation solution dropped on the gate insulating film by using an X-ray diffraction analyzer when the gate insulating film is not surface-treated with HMDS or surface-treated.

8A is a graph illustrating a transfer characteristic of an organic thin film transistor manufactured according to another exemplary embodiment of the present invention.

8B is a graph illustrating output characteristics of an organic thin film transistor manufactured according to another exemplary embodiment of the present invention.

9 is a layout view of a diode fabricated using an organic thin film transistor fabricated according to another embodiment of the present invention.

10 is a cross-sectional view of the organic thin film transistor of FIG. 9 taken along the line X-X.

Claims (12)

Gate electrode, A source electrode and a drain electrode insulated from the gate electrode, A gate insulating film formed between the gate electrode and the source electrode and the drain electrode, and A semiconductor overlapping the gate electrode Including, The gate electrode, the source electrode and the drain electrode include the same soluble material Thin film transistor. Gate electrode, A source electrode and a drain electrode insulated from the gate electrode, A gate insulating film formed between the gate electrode and the source electrode and the drain electrode, A surface treatment film formed on a surface of the gate insulating film, and A semiconductor formed at a position overlapping the gate electrode Including, The surface treatment film includes a thin film transistor (HMDS) (hexa methylene disilazane). delete In claim 2, And the gate electrode, the source electrode and the drain electrode include the same soluble material. In claim 4, The soluble material is a thin film transistor formed of nano silver ink. delete Forming a gate electrode on the substrate by a solution process of a first condition using a first solution, Forming a source electrode and a drain electrode by the solution process under the first condition using the first solution, Forming a gate insulating film between the gate electrode and the source electrode and the drain electrode by a solution process under a second condition using a second solution Forming a semiconductor to overlap with the gate electrode by using a third solution in a third process solution; and Treating the exposed substrate and the surface of the gate insulating film using a fourth solution to form a surface treatment film Including, The solution process is all the same solution process Method of manufacturing a thin film transistor. In claim 7, The solution process is a method of manufacturing a thin film transistor is an inkjet printing method. delete In claim 7, The forming of the surface treatment layer may include forming the surface treatment layer by applying the fourth solution to the entire surface of the exposed substrate and the gate insulating layer using a spin coder. delete delete

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