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KR100999918B1 - Printed Circuit Board and Manufacturing Method Thereof - Google Patents

Printed Circuit Board and Manufacturing Method Thereof Download PDF

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Publication number
KR100999918B1
KR100999918B1 KR1020080088177A KR20080088177A KR100999918B1 KR 100999918 B1 KR100999918 B1 KR 100999918B1 KR 1020080088177 A KR1020080088177 A KR 1020080088177A KR 20080088177 A KR20080088177 A KR 20080088177A KR 100999918 B1 KR100999918 B1 KR 100999918B1
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KR
South Korea
Prior art keywords
printed circuit
circuit board
insulating layer
pair
roughness
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Application number
KR1020080088177A
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Korean (ko)
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KR20100029403A (en
Inventor
이종진
Original Assignee
삼성전기주식회사
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Priority to KR1020080088177A priority Critical patent/KR100999918B1/en
Priority to US12/358,543 priority patent/US20100059267A1/en
Priority to JP2009015337A priority patent/JP5082117B2/en
Publication of KR20100029403A publication Critical patent/KR20100029403A/en
Application granted granted Critical
Publication of KR100999918B1 publication Critical patent/KR100999918B1/en
Priority to US13/788,916 priority patent/US20130186677A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0352—Differences between the conductors of different layers of a multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)

Abstract

인쇄회로기판 및 그 제조 방법이 개시된다. 일면의 조도(roughness)가 서로 상이하게 형성되는 한 쌍의 전도층을 제공하는 단계, 및 한 쌍의 전도층 일면이 각각 절연층의 일면과 타면을 향하도록 절연층에 한 쌍의 전도층을 각각 적층하는 단계를 포함하는 인쇄회로기판 제조 방법은, 이후 인쇄회로기판에 반도체 칩을 실장하는 패키징 공정 중 또는 인쇄회로기판이 전자 제품에 적용된 후 사용되는 중에 수반되는 열에 의해 발생되는 인쇄회로기판의 휨을 저감할 수 있다.A printed circuit board and a method of manufacturing the same are disclosed. Providing a pair of conductive layers in which roughness of one surface is formed different from each other, and a pair of conductive layers in the insulating layer, respectively, so that one surface of the pair of conductive layers faces one side and the other side of the insulating layer, respectively. A printed circuit board manufacturing method comprising the step of laminating thereafter, warpage of a printed circuit board generated by heat accompanying during a packaging process of mounting a semiconductor chip on the printed circuit board or during use after the printed circuit board is applied to an electronic product. Can be reduced.

인쇄회로기판, 조도(roughness), 휨(warpage) Printed Circuit Boards, Roughness, Warpage

Description

인쇄회로기판 및 그 제조 방법{Printed circuit board and method of manufacturing the same}Printed circuit board and method of manufacturing the same

본 발명은 인쇄회로기판 및 그 제조 방법에 관한 것이다.The present invention relates to a printed circuit board and a method of manufacturing the same.

전자 제품이 발전함에 따라, 그 부품인 인쇄회로기판은 점차 박판화되어 가고 있으며, 이에 수반되어, 인쇄회로기판의 휨(warpage) 저감이 중요한 문제로 부각되고 있다.With the development of electronic products, printed circuit boards, which are parts thereof, are becoming thinner and thinner. With this, warpage reduction of printed circuit boards has emerged as an important problem.

즉, 인쇄회로기판에 반도체 칩 등을 실장하는 패키징(packaging) 공정을 수행함에 있어, 수 차례의 가열 및 냉각 공정에 의해 박판화된 인쇄회로기판이 휘는 문제가 발생하게 되며, 또한 인쇄회로기판과 반도체 칩이 조립된 패키지가 전자 제품에 적용되어 사용됨에 있어, 역시 가열과 냉각이 반복됨에 따라, 인쇄회로기판에 주기적인 휨이 발생하여 전자 제품의 신뢰성이 낮아지는 문제가 있다.That is, in carrying out a packaging process for mounting a semiconductor chip or the like on a printed circuit board, a problem of bending a thin printed circuit board due to several heating and cooling processes may occur, and the printed circuit board and the semiconductor may also be deformed. Since the package in which the chip is assembled is used and applied to electronic products, as heating and cooling are repeated, periodic bending occurs on the printed circuit board, thereby lowering the reliability of the electronic products.

도 1은 종래 기술에 따른 인쇄회로기판(10)을 나타낸 단면도이다. 도 1을 참조하면, 종래 기술에 따른 인쇄회로기판(10)은, 절연층(20) 및 절연층(20)의 양면에 각각 금속층(30, 40)이 적층되어 있으며, 이들 금속층(30, 40)은 서로 동일한 조도(roughness)를 가지고 있다.1 is a cross-sectional view of a printed circuit board 10 according to the prior art. Referring to FIG. 1, in the printed circuit board 10 according to the related art, metal layers 30 and 40 are stacked on both surfaces of the insulating layer 20 and the insulating layer 20, respectively, and the metal layers 30 and 40 are formed. ) Have the same roughness.

이와 같이 종래 기술에 따른 인쇄회로기판(10)은 서로 동일한 조도를 가지고 있는 금속판(30, 40)을 사용하므로, 도 1에 도시된 바와 같이, 금속층(30, 40)의 패터닝(patterning)에 의해 상하 금속층(30, 40)의 잔존율이 비대칭을 이루는 경우, 상술한 바와 같이, 반도체 칩을 실장하는 패키징 공정 및 전자 제품의 사용 도중 수반되는 열에 의하여, 인쇄회로기판(10)이 잔존율이 작은 금속층(30) 방향으로 휘는 문제가 발생하는 것이다.As described above, since the printed circuit board 10 according to the related art uses the metal plates 30 and 40 having the same roughness, the patterned metal layers 30 and 40 are patterned as shown in FIG. 1. When the residual ratios of the upper and lower metal layers 30 and 40 are asymmetrical, as described above, the printed circuit board 10 has a small residual ratio due to the heat involved during the packaging process for mounting the semiconductor chip and the use of the electronic product. The problem of bending in the direction of the metal layer 30 will occur.

본 발명은, 열에 의해 발생되는 휨을 저감할 수 있는 인쇄회로기판 및 그 제조 방법을 제공하는 것이다.The present invention provides a printed circuit board and a method of manufacturing the same, which can reduce warpage caused by heat.

본 발명의 일 측면에 따르면, 일면의 조도(roughness)가 서로 상이하게 형성되는 한 쌍의 전도층을 제공하는 단계, 및 한 쌍의 전도층 일면이 각각 절연층의 일면과 타면을 향하도록 절연층에 한 쌍의 전도층을 각각 적층하는 단계를 포함하는 인쇄회로기판 제조 방법이 제공된다.According to an aspect of the invention, providing a pair of conductive layers in which roughness of one surface is formed different from each other, and the insulating layer so that one surface of the pair of conductive layers respectively face one surface and the other surface of the insulating layer Provided is a method of manufacturing a printed circuit board, including the steps of laminating a pair of conductive layers, respectively.

이 때, 전도층은 동박(copper foil)일 수 있다.In this case, the conductive layer may be a copper foil.

또한, 절연층은 에폭시(epoxy) 수지를 포함하여 이루어질 수 있다.In addition, the insulating layer may include an epoxy resin.

또한, 본 발명의 다른 측면에 따르면, 에폭시 수지를 포함하여 이루어지는 절연층, 및 일면의 조도가 서로 상이하게 형성되며, 일면이 각각 절연층의 일면과 타면을 향하도록 절연층에 각각 적층되는 한 쌍의 동박을 포함하는 인쇄회로기판이 제공된다.In addition, according to another aspect of the present invention, the insulating layer comprising an epoxy resin, and one side roughness is formed to be different from each other, a pair each laminated on the insulating layer so that one surface facing one surface and the other surface of the insulating layer, respectively Provided is a printed circuit board comprising a copper foil.

본 발명의 실시예에 따르면, 이후 인쇄회로기판에 반도체 칩을 실장하는 패키징 공정 중 또는 인쇄회로기판이 전자 제품에 적용된 후 사용되는 중에 수반되는 열에 의해 발생되는 인쇄회로기판의 휨을 저감할 수 있다.According to the exemplary embodiment of the present invention, the warpage of the printed circuit board generated by heat accompanying the semiconductor chip on the printed circuit board or during the use of the printed circuit board after being applied to an electronic product can be reduced.

본 발명에 따른 인쇄회로기판 및 그 제조 방법의 실시예를 첨부도면을 참조하여 상세히 설명하기로 하며, 첨부 도면을 참조하여 설명함에 있어, 동일하거나 대응하는 구성 요소는 동일한 도면번호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다.An embodiment of a printed circuit board and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. In the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals, and Duplicate explanations will be omitted.

도 2는 본 발명의 일 측면에 따른 인쇄회로기판(100) 제조 방법의 일 실시예를 나타낸 순서도이다. 도 3 및 도 4는 본 발명의 일 측면에 따른 인쇄회로기판(100) 제조 방법 일 실시예의 각 공정을 나타낸 단면도이다.2 is a flow chart showing an embodiment of a method for manufacturing a printed circuit board 100 according to an aspect of the present invention. 3 and 4 are cross-sectional views illustrating each process of the method of manufacturing the printed circuit board 100 according to an exemplary embodiment of the present invention.

본 실시예에 따르면, 일면의 조도(roughness)가 서로 상이하게 형성되는 한 쌍의 전도층(110, 120)을 제공하는 단계, 및 한 쌍의 전도층(110, 120) 일면이 각 각 절연층(130)의 일면과 타면을 향하도록 절연층(130)에 한 쌍의 전도층(110, 120)을 적층하는 단계를 포함하는 인쇄회로기판(100) 제조 방법이 제시된다.According to the present embodiment, providing a pair of conductive layers 110 and 120 in which roughness of one surface is different from each other, and one surface of each of the pair of conductive layers 110 and 120 A method of manufacturing a printed circuit board 100 including stacking a pair of conductive layers 110 and 120 on an insulating layer 130 facing one surface and the other surface of 130 is provided.

이와 같은 본 실시예에 따르면, 이후 인쇄회로기판(100)에 반도체 칩을 실장하는 패키징(packaging) 공정 중 또는 인쇄회로기판(100)이 전자 제품에 적용된 후 사용되는 중에 수반되는 열에 의해 발생되는 인쇄회로기판(100)의 휨(warpage)을 저감할 수 있다.According to the present embodiment as described above, the printing is generated by the heat involved during the packaging process of mounting the semiconductor chip on the printed circuit board 100 or while the printed circuit board 100 is used after being applied to electronic products The warpage of the circuit board 100 can be reduced.

이하, 도 2 내지 도 4를 참조하여, 각 공정에 대하여 보다 상세히 설명하도록 한다.Hereinafter, each process will be described in more detail with reference to FIGS. 2 to 4.

먼저, 도 3에 도시된 바와 같이, 일면의 조도(roughness)가 서로 상이하게 형성되는 한 쌍의 전도층(110, 120)을 제공한다(S110). 여기서, 한 쌍의 전도층(110, 120)은, 동박(copper foil)이며, 각 전도층(110, 120) 일면의 조도는, 서로 상이하게 형성된다.First, as shown in FIG. 3, a pair of conductive layers 110 and 120 having roughnesses on one surface of which are different from each other are provided (S110). Here, the pair of conductive layers 110 and 120 are copper foils, and the roughness of one surface of each of the conductive layers 110 and 120 is formed different from each other.

즉, 동박인 전도층(110, 120)의 일면은, 조도를 갖도록 조화 처리(roughening treatment)된 후, 절연층(도 4의 130)과의 접착력을 보다 향상시키기 위하여, 예를 들어, 앵커링(anchoring) 공정 등이 수행될 수 있다.That is, one surface of the conductive layers 110 and 120, which are copper foils, is subjected to roughening treatment to have roughness, and then, in order to further improve adhesion to the insulating layer (130 of FIG. 4), for example, anchoring ( anchoring) process may be performed.

이 때, 각 전도층(110, 120)의 일면은 서로 상이한 조도를 가지고 있으므로, 이 후 공정에서 절연층(도 4의 130)에 각 전도층(110, 120)을 압착하면, 조도가 큰 전도층(120)과 절연층(도 4의 130) 사이의 접착 강도는, 조도가 작은 전도층(110)과 절연층(도 4의 130) 사이의 접착 강도 보다 크다. 또한, 절연층(도 4의 130)의 전도층(110, 120)에 대한 횡방향, 즉, 너비 방향의 지지력 역시 조도가 큰 전도 층(120)에 인접한 절연층(도 4의 130) 부분이 더 크다.At this time, since one surface of each conductive layer (110, 120) has a different roughness from each other, if the conductive layer (110, 120) is crimped to the insulating layer (130 of Fig. 4) in a subsequent step, conduction with high roughness The adhesive strength between the layer 120 and the insulating layer 130 (FIG. 4) is greater than the adhesive strength between the conductive layer 110 having low roughness and the insulating layer 130 (FIG. 4). In addition, a portion of the insulating layer (130 in FIG. 4) adjacent to the conductive layer 120 having high roughness in the transverse direction, that is, the width direction, of the insulating layer (130 in FIG. 4) with respect to the conductive layers 110 and 120 may be formed. Is bigger.

다음으로, 도 4에 도시된 바와 같이, 한 쌍의 전도층(110, 120) 일면이 각각 절연층(130)의 일면과 타면을 향하도록 절연층(130)에 한 쌍의 전도층(110, 120)을 각각 적층한다(S120). 즉, 일면의 조도가 서로 상이하게 형성된 각 전도층(110, 120)을 절연층(130)의 일면 및 타면에 각각 적층하여 한 쌍의 전도층(110, 120) 사이에 절연층(130)이 개재되도록 배치한 후, 각 전도층(110, 120)과 절연층(130)을 고온에서 압착하는 것이다.Next, as shown in FIG. 4, the pair of conductive layers 110 and 120 are disposed on the insulating layer 130 such that one surface of the pair of conductive layers 110 and 120 faces one surface and the other surface of the insulating layer 130, respectively. Each of the layers 120 is stacked (S120). That is, the insulating layers 130 are interposed between the pair of conductive layers 110 and 120 by stacking the conductive layers 110 and 120 having different roughnesses on one surface on one surface and the other surface of the insulating layer 130, respectively. After the arrangement, the conductive layers 110 and 120 and the insulating layer 130 are compressed at a high temperature.

여기서, 절연층(130)은 반경화 상태의 에폭시(epoxy) 수지로 이루어질 수 있으므로, 조도가 형성된 각 전도층(110, 120)의 일면이 보다 효과적이고 용이하게 절연층(130)에 밀착될 수 있다.Here, since the insulating layer 130 may be made of an epoxy resin in a semi-cured state, one surface of each of the conductive layers 110 and 120 having roughness formed may be in close contact with the insulating layer 130 more effectively and easily. have.

또한, 이와 같이 한 쌍의 전도층(110, 120)을 절연층(130)에 적층함으로써, 상술한 바와 같이, 조도가 큰 전도층(120)과 절연층(130)과의 접착 강도가, 조도가 작은 전도층(110)과 절연층(130)과의 접착 강도보다 증가될 수 있고, 조도가 큰 전도층(120)에 인접한 절연층(130)이 전도층(120)에 대하여 보다 강한 횡방향 지지력을 가질 수 있으므로, 인쇄회로기판(100)에 가해지는 열로 인하여, 조도가 큰 전도층(120)이 더 팽창하는 경우라도, 상술한 접착 강도 및 지지력에 의해 이러한 팽창력의 불균형을 상쇄시킬 수 있다.In addition, by laminating a pair of conductive layers 110 and 120 on the insulating layer 130 in this manner, as described above, the adhesive strength between the large conductive layer 120 and the insulating layer 130 is rough. Can be increased than the adhesive strength between the small conductive layer 110 and the insulating layer 130, the insulating layer 130 adjacent to the conductive layer 120 having a large roughness is stronger in the transverse direction with respect to the conductive layer 120 Since it can have a supporting force, even if the conductive layer 120 having a large roughness expands further due to the heat applied to the printed circuit board 100, the imbalance of the expansion force can be offset by the aforementioned adhesive strength and bearing force. .

이하, 종래 기술과 본 실시예의 비교를 통하여, 상술한 원리를 보다 상세히 설명하도록 한다.Hereinafter, the above-described principle will be described in more detail by comparing the prior art and the present embodiment.

도 1에 도시된 종래 기술에 따른 인쇄회로기판(도 1의 10)의 경우, 각 금속층(도 1의 30, 40)은 조도가 서로 동일하므로, 각 금속층(도 1의 30, 40)을 패터닝하여 절연층(도 1의 20)의 양면에, 잔존하는 금속층(도 1의 30, 40)의 양이 서로 상이하게 되는 경우, 이후 반도체 패키징 공정 또는 전자 제품의 사용 도중 수반되는 열에 의해, 잔존량이 큰 금속층(도 1의 40)의 팽창되는 전체 양이 잔존량이 작은 금속층(도 1의 30)의 팽창되는 전체 양에 비해 크므로, 결국, 잔존량이 작은 금속층(도 1의 30) 방향으로 인쇄회로기판(도 1의 10)의 양측이 휘는 문제가 발생한다.In the case of the printed circuit board 10 of FIG. 1 according to the related art shown in FIG. 1, the metal layers 30 and 40 of FIG. 1 have the same roughness, so that each metal layer 30 and 40 of FIG. 1 is patterned. When the amounts of the remaining metal layers (30 and 40 in Fig. 1) are different from each other on both sides of the insulating layer (20 in Fig. 1), the remaining amount is due to the heat involved during the semiconductor packaging process or the use of the electronic product. Since the total amount of expansion of the large metal layer (40 in FIG. 1) is larger than the total amount of expansion of the small amount of metal layer (30 in FIG. 1), the printed circuit is eventually directed toward the metal layer (30 in FIG. 1) with a small amount of residual. The problem that both sides of the board | substrate 10 of FIG. 1 bend arises.

그러나, 본 실시예에 따르면, 각 전도층(110, 120) 일면의 조도를 서로 상이하게 형성하여, 상술한 바와 같이, 열에 의한 전도층(110, 120)의 횡방향 팽창을 억제하는 절연층(130)의 지지력을 조절할 수 있으므로, 각 전도층(110, 120)을 에칭하여 회로 패턴을 형성할 시, 조도가 큰 전도층(120)의 잔존량을 크게 하고, 조도가 작은 전도층(110)의 잔존량을 작게 하면, 조도가 큰 전도층(120)의 잔존량이 커 그에 따른 횡방향 팽창력이 증가함에도 불구하고, 조도가 큰 전도층(120)과 절연층(130)과의 강한 접착력 및 이 절연층(130)의 지지력에 의해, 팽창력이 상쇄될 수 있으므로, 결과적으로, 인쇄회로기판(100)의 휨을 저감할 수 있는 것이다.According to the present embodiment, however, the roughness of one surface of each of the conductive layers 110 and 120 is different from each other, and as described above, the insulating layer which suppresses the lateral expansion of the conductive layers 110 and 120 by heat ( Since the support force of 130 may be adjusted, when the conductive layers 110 and 120 are etched to form a circuit pattern, the remaining amount of the high roughness conductive layer 120 is increased and the low roughness conductive layer 110 is formed. If the residual amount of is small, the strong adhesion between the conductive layer 120 and the insulating layer 130 with high roughness is increased even though the residual amount of the conductive layer 120 with high roughness increases and the lateral expansion force increases accordingly. Since the expansion force may be canceled by the supporting force of the insulating layer 130, as a result, the warpage of the printed circuit board 100 can be reduced.

다음으로, 도 5를 참조하여, 본 발명의 다른 측면에 따른 인쇄회로기판(200)에 대하여 설명하도록 한다.Next, referring to FIG. 5, the printed circuit board 200 according to another aspect of the present invention will be described.

도 5는 본 발명의 다른 측면에 따른 인쇄회로기판(200)의 일 실시예를 나타 낸 단면도이다.5 is a cross-sectional view showing an embodiment of a printed circuit board 200 according to another aspect of the present invention.

본 실시예에 따르면, 에폭시 수지를 포함하여 이루어지는 절연층(230), 및 일면의 조도가 서로 상이하게 형성되며, 일면이 각각 절연층(230)의 일면과 타면을 향하도록 절연층(230)에 적층되는 한 쌍의 동박(210, 220)을 포함하는 인쇄회로기판(200)이 제시된다.According to the present embodiment, the insulating layer 230 including epoxy resin and the roughness of one surface are formed to be different from each other, and one surface of the insulating layer 230 faces the one surface and the other surface of the insulating layer 230, respectively. A printed circuit board 200 including a pair of copper foils 210 and 220 stacked is presented.

이와 같은 본 실시예에 따르면, 인쇄회로기판(200)에 반도체 칩을 실장하는 패키징 공정 중 또는 인쇄회로기판(200)이 전자 제품에 적용된 후 사용되는 중에 수반되는 열에 의해 발생되는 인쇄회로기판(200)의 휨을 저감할 수 있다.According to the present embodiment as described above, the printed circuit board 200 is generated by the heat involved during the packaging process of mounting the semiconductor chip on the printed circuit board 200 or while the printed circuit board 200 is applied to the electronic product and then used. ) Warpage can be reduced.

이하, 도 5를 참조하여, 각 구성에 대하여 보다 상세히 설명하도록 한다.Hereinafter, each configuration will be described in more detail with reference to FIG. 5.

절연층(230)은, 에폭시 수지를 포함하여 이루어진다. 이러한 절연층(230)은 반경화 상태에서 후술할 동박(210, 220)과 압착됨과 동시에, 가열 및 경화될 수 있으며, 이와 같이 반경화 상태의 절연층(230)을 이용함에 따라, 보다 효율적이고 용이하게 절연층(230)과 동박(210, 220)을 압착할 수 있다.The insulating layer 230 contains an epoxy resin. The insulating layer 230 may be heated and cured at the same time as the copper foils 210 and 220 which will be described later in a semi-cured state, and may be heated and cured. The insulating layer 230 and the copper foils 210 and 220 can be easily pressed.

한 쌍의 동박(210, 220)은, 일면의 조도가 서로 상이하게 형성되며, 일면이 각각 절연층(230)의 일면과 타면을 향하도록 절연층(230)에 각각 적층된다. 즉, 동박(210, 220)의 각 일면은 서로 상이하게 조도가 형성되며, 절연층(230)의 일면 및 타면을 향하도록 적층된다. 이에 따라, 한 쌍의 동박(210, 220) 사이에는 절연층(230)이 개재되며, 이들 동박(210, 220)과 절연층(230)이, 상술한 바와 같이, 고온에서 압착됨으로써 인쇄회로기판(200)이 형성된다.The pair of copper foils 210 and 220 are formed to have different roughnesses on one surface, and are laminated on the insulating layer 230 so that one surface thereof faces one surface and the other surface of the insulating layer 230, respectively. That is, each surface of the copper foil (210, 220) is formed to be different from each other roughness, is laminated so as to face one surface and the other surface of the insulating layer 230. Accordingly, an insulating layer 230 is interposed between the pair of copper foils 210 and 220, and the copper foils 210 and 220 and the insulating layer 230 are compressed at a high temperature, as described above, to thereby print a printed circuit board. 200 is formed.

이와 같은 인쇄회로기판(200)은 절연층(230)의 양면에 서로 비대칭의 조도가 형성된 동박(210, 220)이 배치됨으로써, 패터닝에 따른 각 동박(210, 220)의 잔존량이 상이한 경우에도, 잔존량이 큰 동박(220)의 조도를 증가시켜 동박(220)과 절연층(230) 간의 접착력 및 절연층(230)의 지지력을 증가시킬 수 있다. 따라서, 이와 같은 접착력 및 지지력에 의해, 잔존량이 큰 동박(220)의 팽창을 억제할 수 있으므로, 결과적으로 열에 의한 인쇄회로기판(200)의 휨을 저감할 수 있다.The printed circuit board 200 has copper foils 210 and 220 having asymmetrical roughnesses disposed on both surfaces of the insulating layer 230, so that the remaining amount of each copper foil 210 and 220 due to patterning is different. By increasing the roughness of the copper foil 220 having a large residual amount, the adhesion between the copper foil 220 and the insulating layer 230 and the supporting force of the insulating layer 230 may be increased. Therefore, the expansion of the copper foil 220 having a large residual amount can be suppressed by such an adhesive force and a supporting force, and as a result, the warpage of the printed circuit board 200 due to heat can be reduced.

이상, 본 발명의 일 실시예에 대하여 설명하였으나, 해당 기술 분야에서 통상의 지식을 가진 자라면 특허청구범위에 기재된 본 발명의 사상으로부터 벗어나지 않는 범위 내에서, 구성 요소의 부가, 변경, 삭제 또는 추가 등에 의해 본 발명을 다양하게 수정 및 변경시킬 수 있을 것이며, 이 또한 본 발명의 권리범위 내에 포함된다고 할 것이다.As mentioned above, although an embodiment of the present invention has been described, those of ordinary skill in the art may add, change, delete or add components within the scope not departing from the spirit of the present invention described in the claims. The present invention may be modified and changed in various ways, etc., which will also be included within the scope of the present invention.

도 1은 종래 기술에 따른 인쇄회로기판을 나타낸 단면도.1 is a cross-sectional view showing a printed circuit board according to the prior art.

도 2는 본 발명의 일 측면에 따른 인쇄회로기판 제조 방법의 일 실시예를 나타낸 순서도.Figure 2 is a flow chart showing an embodiment of a printed circuit board manufacturing method according to an aspect of the present invention.

도 3 및 도 4는 본 발명의 일 측면에 따른 인쇄회로기판 제조 방법 일 실시예의 각 공정을 나타낸 단면도.3 and 4 are cross-sectional views showing each process of one embodiment of a method for manufacturing a printed circuit board according to an aspect of the present invention.

도 5는 본 발명의 다른 측면에 따른 인쇄회로기판의 일 실시예를 나타낸 단면도.Figure 5 is a cross-sectional view showing an embodiment of a printed circuit board according to another aspect of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100: 인쇄회로기판100: printed circuit board

110, 120: 전도층110, 120: conductive layer

130: 절연층130: insulation layer

Claims (4)

일면의 조도(roughness)가 서로 상이하게 형성되는 한 쌍의 전도층을 제공하는 단계;Providing a pair of conductive layers in which roughness of one surface is formed different from each other; 상기 한 쌍의 전도층 일면이 각각 절연층의 일면과 타면을 향하도록 상기 절연층에 상기 한 쌍의 전도층을 각각 적층하는 단계; 및Stacking the pair of conductive layers on the insulating layer so that one surface of the pair of conductive layers faces one surface and the other surface of the insulating layer, respectively; And 상기 한 쌍의 전도층 중 조도가 큰 전도층의 잔존량이 크도록, 상기 한 쌍의 전도층을 에칭하여 회로패턴을 형성하는 단계를 포함하는 인쇄회로기판 제조 방법.And etching the pair of conductive layers to form a circuit pattern such that the remaining amount of the conductive layer having high roughness among the pair of conductive layers is large. 제1항에 있어서,The method of claim 1, 상기 전도층은 동박(copper foil)인 것을 특징으로 하는 인쇄회로기판 제조 방법.The conductive layer is a copper foil (copper foil) characterized in that the printed circuit board manufacturing method. 제1항에 있어서,The method of claim 1, 상기 절연층은 에폭시(epoxy) 수지를 포함하여 이루어지는 것을 특징으로 하는 인쇄회로기판 제조 방법.The insulating layer is a printed circuit board manufacturing method comprising an epoxy (epoxy) resin. 에폭시 수지를 포함하여 이루어지는 절연층; 및An insulation layer comprising an epoxy resin; And 일면의 조도가 서로 상이하게 형성되며, 일면이 각각 상기 절연층의 일면과 타면을 향하도록 상기 절연층에 각각 적층되는 한 쌍의 동박을 포함하고,The roughness of one surface is formed different from each other, and includes a pair of copper foils respectively laminated on the insulating layer so that one surface thereof faces one surface and the other surface of the insulating layer, 상기 한 쌍의 동박 중 조도가 큰 동박이 조도가 작은 동박보다 넓은 면적을 가지는 것을 특징으로 하는 인쇄회로기판.Printed circuit board, characterized in that the copper foil having a large roughness of the pair of copper foil has a larger area than the copper foil having a low roughness.
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KR100502179B1 (en) 2002-02-25 2005-08-08 스마트알앤씨 주식회사 Preparation of Metal Clad Laminate for Printed Circuit Board
KR100736518B1 (en) 2004-01-26 2007-07-06 마쯔시다덴기산교 가부시키가이샤 Method for producing circuit-forming board and material for producing circuit-forming board

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