KR100973804B1 - Thin film transistor array panel - Google Patents

Abstract

A thin film transistor panel according to the present invention includes an insulating substrate, a plurality of gate lines formed on the insulating substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, A plurality of data lines, a plurality of drain electrodes, a protective film formed on the data lines, and a plurality of pixel electrodes formed on the protective film and electrically connected to the drain electrodes, It overlaps with the entire width and does not overlap with its own gate line. In this way, by preventing the pixel electrode from overlapping with the gate line connected to the pixel electrode, it is possible to reduce the parasitic capacitance between the gate and the drain, thereby lowering the kickback voltage and maximizing the aperture ratio.

A pixel electrode, a kickback voltage, a gate line, a data line

Description

{THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout diagram of a liquid crystal display device according to an embodiment of the present invention,

FIGS. 2A and 2B are cross-sectional views of the liquid crystal display of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively,

Figs. 3, 5, 7, and 9 are layouts at an intermediate stage of a method of manufacturing a thin film transistor panel according to an embodiment of the present invention in the liquid crystal display device shown in Figs. 1 and 2B, FIG.

FIGS. 4A and 4B are cross-sectional views of the thin film transistor panel of FIG. 3 taken along lines IVa-IVa 'and IVb-IVb'

6A and 6B are cross-sectional views of the thin film transistor panel of FIG. 5 taken along lines VIa-VIa 'and VIb-VIb', respectively,

8A and 8B are cross-sectional views of the thin film transistor panel of FIG. 7 cut along lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively,

FIGS. 10A and 10B are cross-sectional views of the thin film transistor panel of FIG. 9 taken along lines IXa-IXa 'and IXb-IXb', respectively,

11 is a layout diagram of a thin film transistor panel according to another embodiment of the present invention,                 

12A and 12B are cross-sectional views of the thin film transistor panel of FIG. 11 cut along the lines XIIa-XIIa 'and XIIb-XIIb', respectively,

13 is a layout diagram of a thin film transistor panel according to another embodiment of the present invention,

FIGS. 14A and 14B are cross-sectional views of the thin film transistor panel of FIG. 13 taken along lines XIVa-XIVa 'and XIVb-XIVb'

Figs. 15, 18, and 20 are layouts at an intermediate stage of a method of manufacturing a thin film transistor panel according to an embodiment of the present invention in the liquid crystal display shown in Figs. 13 to 14B, Fig.

16A and 16B are cross-sectional views of the thin film transistor panel of FIG. 15 taken along lines XVIa-XVIa 'and XVIb-XVIb', respectively,

FIGS. 17A and 17B are cross-sectional views taken along line XVIa-XVIa 'and XVIb-XVIb' of FIG. 15, respectively, in the steps subsequent to FIGS. 16A and 16B,

19A and 19B are cross-sectional views of the thin film transistor panel of FIG. 18 taken along lines XIXa-XIXa 'and XIXb-XIXb', respectively,

21A and 21B are cross-sectional views of the thin film transistor panel of FIG. 20 cut along the lines XXIa-XXIa 'and XXIb-XXIb', respectively.

The present invention relates to a thin film transistor display panel, and more particularly, to a thin film transistor panel for a liquid crystal display.

Generally, a liquid crystal display device includes a liquid crystal layer having an anisotropic permittivity injected into a gap between two display panels and two display panels having electric field generating electrodes for generating an electric field and spaced apart by a predetermined gap. Such a liquid crystal display displays an image by applying a voltage to the electric field generating electrode to generate an electric field in the liquid crystal layer and adjusting the intensity of an electric field depending on the magnitude of the voltage to adjust the transmittance of light passing through the liquid crystal layer.

Among liquid crystal display devices, a liquid crystal display device having a thin film transistor which is formed by forming electrodes on two display panels and switching a voltage applied to the electrodes is mainly used. One of the two display panels is provided with a plurality of wirings (Hereinafter referred to as thin film transistor display panel) for transmitting data signals applied to the pixel electrodes and the pixel electrodes, common electrodes facing the pixel electrodes and red (R), green (G) , And blue (B) color filters are generally formed.

In order to improve the luminance of such a liquid crystal display device, securing a high aperture ratio is an important problem. To this end, the pixel electrode connected to the drain electrode of the thin film transistor display panel is formed so as to partially overlap the left and right data lines and the upper and lower gate lines to improve the opening.

However, since the gate electrode of the thin film transistor connected to the drain electrode and the pixel electrode, which is the same potential as the drain electrode, overlaps the gate line of the thin film transistor, the gate-drain parasitic capacitance is large and the kick- There is a problem that the voltage increases.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor display panel in which a kickback voltage is low without substantially sacrificing an aperture ratio.

In order to achieve the above object, the present invention provides a thin film transistor display panel as described below.

More particularly, the present invention relates to an insulating substrate, a plurality of gate lines formed on the insulating substrate, a gate insulating film formed on the gate lines, a semiconductor layer formed on the gate insulating film, And a plurality of pixel electrodes formed on the passivation layer and electrically connected to the drain electrodes, wherein the pixel electrodes are overlapped with the entire width of the front gate line And a thin film transistor display panel which does not overlap with its own gate line is provided.

In addition, it is preferable to further include a plurality of color filters formed under the protective film.

Alternatively, a plurality of gate lines and a plurality of data lines insulated from each other, a plurality of thin film transistors connected to the gate lines and the data lines, a plurality of pixel electrodes connected to the thin film transistors, A second display panel including a common electrode facing the pixel electrode, and a second display panel including a first display panel including a sustain electrode line overlapping the pixel electrode, a second display panel including a common electrode facing the pixel electrode, Wherein the pixel electrode overlaps with the gate line and does not overlap with the gate line of the black matrix, and the black matrix has a liquid crystal display device covering a part of the area between the gate line and the sustain electrode line.

The method of claim 6,

It is preferable that a boundary of the pixel electrode is located between the sustain electrode line and the gate line.

It is preferable that the display device further includes a plurality of color filters provided on any one of the first and second display panels.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a part of a layer, a film, an area, a plate, or the like is on another part, it includes not only the part directly above another part but also the part where there is another part in the middle. Conversely, when a part is directly above another part, it means that there is no other part in the middle.

Hereinafter, a thin film transistor substrate according to an embodiment of the present invention will be described in detail with reference to the drawings with reference to the drawings.

FIG. 1 is an arrangement view of a liquid crystal display device according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are cross-sectional views taken along lines IIa-IIa and IIb-IIb 'of the liquid crystal display device of FIG.

1 and 2B, a liquid crystal display according to an exemplary embodiment of the present invention includes an upper panel 200, a lower panel 100, and a liquid crystal layer (not shown) (3).

First, the upper display panel 200 will be described.

The upper panel 200 includes a common electrode 270, a black matrix 220, a color filter 230, a columnar spacer 220, a column spacer 320, and an alignment layer 21. The common electrode 270 is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is provided with a plurality of cutouts (not shown) . The black matrix 220 is for preventing light leakage and the color filter 230 is for color display and the spacers 320 are used for keeping the gap between the upper display panel 200 and the lower display panel 100 constant will be.

The lower panel 100 will be described in detail.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate line 121 and the storage electrode line 131 extend mainly in the lateral direction and are separated from each other. The gate line 121 transmits a gate signal, and a part of each gate line 121 protrudes upward to form a plurality of gate electrodes 124. The sustain electrode line 131 includes an expansion 137 having a predetermined voltage applied thereto, such as a common voltage, and a width extended downward.

The gate line 121 and the sustain electrode line 131 include a conductive film made of a metal such as silver or a silver alloy having a low resistivity or an aluminum-based metal such as aluminum (Al) or an aluminum alloy. (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and alloys thereof (e.g., molybdenum-tungsten (MoW) alloy], or the like. An example of the combination of the lower film and the upper film is chromium / aluminum-neodymium (Nd) alloy.

The side surfaces of the gate line 121 and the sustain electrode line 131 are inclined and the inclination angle is in the range of about 30-80 degrees with respect to the surface of the substrate 110. [

A gate insulating film 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the storage electrode line 131.

On the gate insulating film 140, a plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (abbreviated as a-Si for amorphous silicon) are formed. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of extensions 154 extend toward the gate electrode 124.

A plurality of linear and island-shaped ohmic contacts 161 and 165 made of a material such as silicide or n + hydrogenated amorphous silicon to which n-type impurity is heavily doped are formed on the semiconductor 151 have. The linear contact member 161 has a plurality of protrusions 163 and the protrusions 163 and the island-like contact members 165 are positioned on the protrusions 154 of the semiconductor 151 in pairs.

The sides of the semiconductor 151 and the resistive contact members 161 and 165 are also inclined and the inclination angle is 30-80 degrees.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the resistance contact members 161 and 165 and the gate insulating film 140, respectively.

The data line 171 extends mainly in the vertical direction and crosses the gate line 121 to transmit a data voltage. A plurality of branches extending from each data line 171 toward the drain electrode 175 form a source electrode 173. A pair of the source electrode 173 and the drain electrode 175 are separated from each other and opposed to each other with respect to the gate electrode 124. The drain electrode 175 has a protrusion 177 extending toward the extension 137 of the storage electrode line 131 and overlapping the extension 137. The gate electrode 124, the source electrode 173 and the drain electrode 175 together with the protrusion 154 of the semiconductor 151 constitute a thin film transistor (TFT) Is formed in the protrusion 154 between the electrode 173 and the drain electrode 175. The data line 171 and the drain electrode 175 also include a conductive film made of a series metal or an aluminum series metal, Layer structure including a conductive film made of chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and alloys thereof. The sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 degrees with respect to the horizontal plane.

The resistive contact members 161 and 165 exist only between the semiconductor 151 under the resistive contact members 161 and the data line 171 and the drain electrode 175 on the semiconductor 151 and serve to lower the contact resistance. The linear semiconductor 151 has portions exposed between the source electrode 173 and the drain electrode 175 as well as the data line 171 and the drain electrode 175. In most cases, The width of the data line 171 is smaller than the width of the data line 171. The semiconductor 151 may have a larger width at a portion where the semiconductor line 151 meets the gate line 121 in order to enhance the insulation between the gate line 121 and the data line 171. [

A plasma enhanced chemical vapor deposition (PECVD) process is performed on the exposed portions of the data lines 171 and the drain electrodes 175 and organic materials having photosensitivity and excellent planarization characteristics. A low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F or a passivation layer 180 made of an inorganic material such as silicon nitride is formed.

The protective film 180 is formed with a plurality of contact holes 182 and 187 for exposing the end portion 179 and the drain electrode 175 of the data line 171, respectively.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 187 and receives the data voltage from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the upper panel 200 to rearrange the liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 190 and 270.

The pixel electrode 190 and the common electrode 270 form a capacitor (hereinafter referred to as a liquid crystal capacitor) to maintain the applied voltage even after the thin film transistor is turned off. In order to enhance the voltage holding capability, The other capacitor connected in parallel with the capacitor is called a storage electrode. The storage capacitor is formed by overlapping the pixel electrode 190 and the storage electrode line 131 and overlapping the pixel electrode 190 and the neighboring gate line 121 (referred to as a previous gate line) An extended portion 137 extending the storage electrode line 131 is provided to increase the capacitance of the capacitor to increase the capacitance of the capacitor, The projection 177 of the electrode 175 is placed under the protective film 180 so that the distance between the two is close to each other.

The pixel electrode 190 overlaps the entire width of the gate line 121 that is not overlapped with the gate line 121 connected to the thin film transistor connected to the adjacent gate line 121 but is not connected to the gate line 121. The boundary between the pixel electrodes 190 is present between the storage electrode line 131 and the gate line 121 where the contact hole 187 is located. The pixel electrode 190 may further include a plurality of cutouts (not shown), which overlap the neighboring data lines 171 of the common electrode 270 to increase the aperture ratio But may not overlap.

The contact assistant member 82 is connected to the end portion 179 of the data line through the contact hole 182, respectively. The contact assistant member 82 is not essential to complement and protect the adhesion between the end portion 129 of the data line 171 and the external device, and the application of the contact assistant member 82 is optional.

Finally, an alignment film 11 is formed on the pixel electrode 190, the contact assistant member 82, and the passivation film 180. The alignment film 11 is in contact with the alignment film 21 of the upper panel 200 where the spacer 320 is located.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and an opaque reflective metal may be used in the case of a reflective liquid crystal display device. In addition, in the case of a transflective liquid crystal display device, the pixel electrode may include two electrodes, a transparent electrode and a reflective electrode.

1, the black matrix 220 overlaps the gate line 121 and the data line 171, and the thin film transistor and the thin film transistor are overlapped with each other, as shown in FIG. 1, Overlap. The black matrix 220 also overlaps the area between contact holes 187 from approximately the thin film transistor. The portion between the thin film transistor and the contact hole 187 among the boundary line of the pixel electrode 190 is shielded by the black matrix 220 to prevent light leakage at the boundary portion.

The structure of the pixel electrode 190 reduces the overlapping area of the drain electrode 175 and the pixel electrode 190 in an electrically equi-conductive state and the gate electrode 124 of the thin film transistor connected thereto, Parasitic capacitance is reduced. A decrease in parasitic capacitance leads to a decrease in the kickback voltage, which can be confirmed from the following relationship.

The kickback voltage (Vk)

Where Cgd is the parasitic capacitance due to the overlap of the gate line 121 including the gate electrode 124, the drain electrode 175 and the pixel electrode 190, Clc is the capacitance of the liquid crystal capacitor, Cst is the capacitance Capacitance, and dVg is the difference between the gate-on voltage that turns on the thin-film transistor and the gate-off voltage that turns it off. In this equation, the decrease in Cgd results in a lower amount of molecules in the denominator than in the denominator, resulting in a lower overall kickback voltage.                     

From the viewpoint of the aperture ratio, since the area from the contact hole 187 to the thin film transistor is a very small area, the aperture ratio hardly decreases.

A manufacturing method of the thin film transistor panel, which is a lower panel in the liquid crystal display device shown in Figs. 1 to 2B, will be described in detail with reference to Figs. 3 to 10B and Figs. 1 to 2B.

Figs. 3, 5, 7, and 9 are layouts at an intermediate stage of a method of manufacturing a thin film transistor panel according to an embodiment of the present invention in the liquid crystal display device shown in Figs. 1 and 2B, 4A and 4B, FIGS. 6A and 6B, FIGS. 8A and 8B, and 10A and 10B show the thin film transistor panel of FIGS. 3, 5, 7 and 9, respectively, IXa-IXa line, and IXb-IXb 'line, and lines IVb-IVb', VIa-VIa and VIb-VIb ', VIIIa-VIIIa and VIIIb-VIIIb', respectively.

First, as shown in FIGS. 3 to 4B, a conductive layer such as a metal is deposited on the insulating substrate 110 made of transparent glass to a thickness of 1,000 Å to 3,000 Å by sputtering, and then photolithography is performed to form a plurality of gates A plurality of sustain electrode lines 131 including a plurality of gate lines 121 including a plurality of electrodes 123 and a plurality of extension portions 137 are formed.

As shown in FIGS. 5 to 6B, a three-layered film of a gate insulating film 140, intrinsic amorphous silicon, and extrinsic amorphous silicon is successively laminated, and the impurity amorphous silicon layer and intrinsic The amorphous silicon layer is photo-etched to form a linear intrinsic semiconductor 151 including a plurality of linear impurity semiconductors 164 and a plurality of projections 154, respectively. Silicon nitride is preferably used as the material of the gate insulating film 140, and the deposition temperature is preferably 250 to 500 占 폚, and the thickness is preferably 2,000 to 5,000 占.

7 to 8B, a photoresist film 44 is formed on the upper film, and the upper film is patterned by wet etching and the lower film is patterned by dry etching in order to form a plurality of source electrodes 173 A plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of storage capacitor conductors 177 are formed. A conductor layer such as a metal layer is deposited on the substrate and photolithographically etched to form a plurality of drain electrodes 175 including a data line 171 including a plurality of source electrodes 173 and a protrusion 177. [

Subsequently, portions of the impurity semiconductor 164 that are not covered with the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are removed to form a plurality of linear portions 163 each including a plurality of projections 163 The resistive contact member 161 and the plurality of island-shaped resistive contact members 165 are completed, while the portion of the intrinsic semiconductor 151 below the resistive contact member 161 is exposed. At this time, the upper portion of the protrusion 154 of the intrinsic semiconductor 151 may also be etched to a certain thickness, and oxygen plasma is preferably performed subsequently to stabilize the surface of the exposed intrinsic semiconductor 151 portion.

Next, as shown in Figs. 9 to 10B, the protective film 180 is laminated and photolithographically etched to form a plurality of contact holes 182, 187. The contact holes 182 and 187 expose the end portion 179 and the drain electrode 175 of the data line 171.                     

As shown in FIGS. 1 and 2B, an IZO or ITO film is stacked by sputtering and photolithographically etched to form a plurality of pixel electrodes 190 and a plurality of contact assistants 82. In the case where the material of the pixel electrode 190 and the contact assistant 82 is IZO, the target can be a product of IDIXO (indium x-metal oxide) manufactured by Idemitsu, Inc., and includes In2O3 and ZnO, And zinc in the total amount of zinc is preferably in the range of about 15-20 atomic%. The sputtering temperature of IZO is preferably 250 DEG C or less in order to minimize the contact resistance.

Finally, an alignment film 11 is formed on the pixel electrode 190.

FIG. 11 is a layout view of a thin film transistor panel according to another embodiment of the present invention, and FIGS. 12A and 12B are cross-sectional views of the thin film transistor panel of FIG. 11 taken along lines XIVa-XIVa and XIVb-XIVb.

11 to 12B, the liquid crystal display according to the present embodiment also includes lower and upper display plates 100 and 200 facing each other and a liquid crystal layer 3 between the two.

The layered structure of the lower panel 100, that is, the thin film transistor panel is generally similar to the layered structure of the liquid crystal display shown in Figs. 1 and 2B. That is, a plurality of gate lines 121 including a plurality of gate electrodes 124 are formed on a substrate 110, and a plurality of linear semiconductors (not shown) including a gate insulating film 140 and a plurality of protruding portions 154 are formed thereon. A plurality of linear resistive contact members 161 each including a plurality of projections 163 and a plurality of island-shaped resistive contact members 165 are formed in order. A plurality of data lines 171 and a plurality of drain electrodes 175 including a plurality of source electrodes 153 are formed on the resistive contact members 161 and 165 and the gate insulating film 140, Is formed. A plurality of contact holes 182 and 187 are formed in the passivation layer 180 and a plurality of pixel electrodes 190 and a plurality of contact assistants 82 are formed on the passivation layer 180.

However, unlike the thin film transistor panel shown in FIGS. 1 and 2B, the thin film transistor panel 100 according to the present embodiment has a plurality of three primary colors formed below the protective layer 180, for example, red, green, and blue And further includes a filter 230R. As shown in FIG. 12A, the color filter 230 overlaps at the boundary portion to block light. Accordingly, in the upper panel 200, a black matrix as well as a color filter are omitted. The red or green color filter 230 located above the channel of the thin film transistor blocks or absorbs a short wavelength visible light incident on the channel of the thin film transistor.

The color filters 230R, 230G, and 230B also have a contact hole 187 that exposes the drain electrode 175 together with the protective film 180. [ The protective film 180 has a plurality of contact holes 181 for exposing the end portion 129 of the gate line 121 and contacts the end portion 129 of the gate line 121 A plurality of contact assistant members 81 are formed. The contact assistant 81 is provided in the case where a gate driving circuit (not shown) for supplying a signal to the gate line 121 is mounted on the display panel 100 or the flexible circuit board need.                     

A thin film transistor panel according to another embodiment of the present invention will be described in detail with reference to FIGS. 13 to 14B. FIG.

FIG. 13 is a layout diagram of a thin film transistor panel according to another embodiment of the present invention, and FIGS. 14A and 14B are cross-sectional views of the thin film transistor panel shown in FIG. 13 taken along lines XIVa-XIVa and XIVb-XIVb.

As shown in FIGS. 13 to 14B, the layered structure of the thin film transistor panel according to this embodiment is generally the same as the layered structure of the liquid crystal display shown in FIGS. 1 and 2B. That is, a plurality of gate lines 121 including a plurality of gate electrodes 124 are formed on a substrate 110, and a plurality of linear semiconductors (not shown) including a gate insulating film 140 and a plurality of protruding portions 154 are formed thereon. A plurality of linear resistive contact members 161 each including a plurality of projections 163 and a plurality of island-shaped resistive contact members 165 are formed in order. A plurality of data lines 171 and a plurality of drain electrodes 175 including a plurality of source electrodes 153 are formed on the resistive contact members 161 and 165 and the gate insulating layer 140, Respectively. A plurality of contact holes 182 and 187 are formed in the passivation layer 180 and a plurality of pixel electrodes 190 and a plurality of contact assistants 82 are formed on the passivation layer 180.

The semiconductor 151 has substantially the same planar shape as the data line 171 and the drain electrode 175 and the resistive contact members 161 and 165 thereunder except for the protrusion 154 where the thin film transistor is located. Note that the semiconductor 151 may be formed between the source electrode 173 and the drain electrode 175 in addition to the portion under the data line 171 and the drain electrode 175 and below the resistive contact members 161 and 165 And has a portion exposed to them. The protective film 180 has a plurality of contact holes 181 for exposing the end portions 129 of the gate lines 121 and contacted with the end portions 129 of the gate lines 121 A plurality of contact assistant members 81 are formed.

A method of manufacturing a thin film transistor panel for a liquid crystal display according to an embodiment of the present invention having the structure of FIGS. 13 to 14B will now be described in detail with reference to FIGS. 15 to 21B and FIGS. 13 to 14B .

FIGS. 15, 18 and 20 are diagrams showing the layout of the thin film transistor panel in the liquid crystal display shown in FIGS. 13 to 14B in the intermediate step of the method of manufacturing the thin film transistor panel according to the embodiment of the present invention, 16A, 16B, 19A, 19B, and 21A and 21B show the thin film transistor panel of FIGS. 15, 18, and 20, respectively, along XVIa-XVIa and XVIb-XVIb ', XIXa-XIXa, XVIb-XIXb ', and XXIa-XXIa and XXIb-XXIb'. FIGS. 17A and 17B show the TFT array panel of FIG. 15 along the lines XVIa-XVIa and XVIb-XVIb ' 16A and 16B as a cross-sectional view taken along the cutting-down direction.

First, as shown in FIGS. 15 to 16B, a conductive layer such as a metal is deposited on the insulating substrate 110 by a method such as sputtering, and is photo-etched to form a plurality of gate lines 121 And a plurality of extension portions 137 are formed on the surface of the insulating substrate 110. [

A three-layer film of a gate insulating film 140, an intrinsic amorphous silicon layer 150, and an impurity amorphous silicon layer 160 is successively deposited by chemical vapor deposition (CVD) or the like.

Next, as shown in FIGS. 17A and 17B, the gate insulating film 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively laminated by chemical vapor deposition (CVD) or the like. Silicon nitride is preferably used as the material of the gate insulating film 140, and the deposition temperature is preferably about 250 to 400 캜 and the thickness is about 2,000 to 5,000 Å. Next, the conductor layer 170, such as a metal, is deposited to a predetermined thickness by sputtering or the like, and then the photoresist layer 60 is coated thereon to a thickness of 1 to 2 μm.

Thereafter, the photosensitive film 50 is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photoresist layer varies depending on the position, and in FIGS. 17A and 17B, the photoresist layer is composed of first to third portions whose thickness gradually decreases. A first portion located in the region A (hereinafter referred to as a wiring region) and a second portion located in the region C (hereinafter referred to as a channel region) are denoted by reference numerals 42 and 44, respectively, and a region B (Hereinafter referred to as " region "), because the third portion has a thickness of zero, and the underlying conductor layer 170 is exposed. The ratio of the thickness of the first portion 42 to the thickness of the second portion 44 is different depending on the process conditions in the subsequent process and the thickness of the second portion 44 is set to 1/2 of the thickness of the first portion 42 Or less, for example, 4,000 ANGSTROM or less.

As described above, there are various methods of varying the thickness of the photoresist layer depending on the position. It is preferable that a transparent area and a light blocking area as well as a translucent area are provided in the exposure mask. Yes. The semitransparent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or an intermediate thickness. When using the slit pattern, it is preferable that the width of the slit and the interval between the slits are smaller than the resolution of the exposure apparatus used in the photolithography process. Another example is to use a reflowable photoresist. That is, a reflowable photoresist pattern is formed using a conventional mask having only a transparent region and a light-shielding region, and then reflowed to flow into a region where the photoresist film remains, thereby forming a thin portion.

If appropriate process conditions are applied, the lower layers can be selectively etched due to the thickness difference of the photoresist films 42 and 44. A plurality of data lines 171 and a plurality of drain electrodes 175 each including a plurality of source electrodes 173 as shown in Figs. 18 to 19B are formed through a series of etching steps and a plurality of protrusions 163 A plurality of linear resistive contact members 161 and a plurality of island-shaped resistive contact members 165 each including a plurality of protruding portions 154 and a plurality of protruding portions 154 are formed.

The portions of the conductor layer 170, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 located in the wiring region A are referred to as a first portion and the portion of the conductor layer 170 located in the channel region C is referred to as a first portion, A part of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 are referred to as a second portion and the conductive layer 170 located in the other region B and the impurity amorphous silicon layer 160, Let the portion of the amorphous silicon layer 150 be the third portion.

An example of the order of forming such a structure is as follows.

(1) removal of the third portion of the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region B,

(2) removing the second portion 44 of the photoresist located in the channel region,

(3) removing the second portion of the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel region C, and

(4) Removal of the first portion 42 of the photoresist film located in the wiring region A.

Another example of this sequence is as follows.

(1) removal of the third portion of the conductor layer 170 located in the other region B,

(2) removing the second portion 44 of the photoresist located in the channel region C,

(3) removing the third portion of the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region B,

(4) removing the second portion of the conductor layer 170 located in the channel region C,

(5) removing the first portion 42 of the photoresist film located in the wiring region A, and

(6) Removal of the second portion of the impurity amorphous silicon layer 160 located in the channel region (C).

The thickness of the first portion 42 of the photoresist film is reduced when the second portion 44 of the photoresist film is removed but the thickness of the second portion 44 of the photoresist film is thinner than the first portion 42 of the photoresist film, The first portion 42, which prevents it from being removed or etched, is not removed.

If the appropriate etching conditions are selected, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 and the second portion 44 of the photoresist film under the third portion of the photoresist layer can be simultaneously removed. Similarly, the portion of the impurity amorphous silicon layer 160 below the second portion 44 of the photoresist and the first portion 42 of the photoresist can be removed at the same time. For example, when a mixed gas of SF6 and HCl or a mixed gas of SF6 and O2 is used, the photoresist film and the intrinsic amorphous silicon layer 150 (or the impurity amorphous silicon layer 160) can be etched at almost the same etching rate .

If the photoresist film remnant remains on the surface of the conductor layer 170, it is removed by ashing.

In step (3) of the first example or step (4) of the second example, an etching gas used for etching the intrinsic amorphous silicon layer 150 may be a mixed gas of CF4 and HCl or a mixed gas of CF4 and O2 If the CF 4 and O 2 are used, the amorphous silicon layer 150 can be cut with a uniform thickness.

Thereafter, as shown in Figs. 20 and 21B, silicon nitride is deposited by CVD at a temperature in the range of about 250 to 1500 占 폚, an acrylic organic insulating material having excellent planarization property is applied, or an a-Si: C: O film Or an a-Si: O: F film by a PECVD method to form a protective film 180. The protective film 180 is then photoetched together with the gate insulating film 140 to form a plurality of contacts Holes 181, 182, and 187 are formed.

Finally, as shown in FIGS. 13 to 14B, an ITO layer or IZO layer having a thickness of 500 ANGSTROM to 1,500 ANGSTROM is deposited by a sputtering method and is photo-etched to form a plurality of pixel electrodes 190 and a plurality of contact assistants 81 And 82 are formed, and the alignment film 11 is applied.

The fabrication process can be simplified because the data line 171 and the drain electrode 175 and the resistive contact members 161 and 165 and the semiconductor 151 under the data line 171 and the drain electrode 175 are formed by one photolithography process.

The thin film transistor panel according to the embodiment of the present invention may be manufactured by various modified forms and methods.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

As described above, according to the present invention, by preventing the pixel electrode from overlapping with the gate line connected to the pixel electrode, it is possible to reduce the parasitic capacitance between the gate and the drain, thereby lowering the kickback voltage and maximizing the aperture ratio.

Claims (10)

Insulating substrate, A plurality of gate lines formed on the insulating substrate and having gate electrodes, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A plurality of data lines and a plurality of drain electrodes formed on the semiconductor layer, A protective film formed on the data line, and And a plurality of pixel electrodes formed on the protective film and electrically connected to the drain electrodes, Wherein the pixel electrode overlaps with the entirety of the front gate line located between two neighboring data lines and the gate electrode of the front gate line and does not overlap with the gate line of the pixel electrode. The method of claim 1, Wherein the pixel electrode overlaps the neighboring left and right data lines. The method of claim 1, And a sustain electrode line formed in the same layer as the gate line and overlapped with the pixel electrode. 4. The method of claim 3, And the drain electrode overlaps the sustain electrode line. The method of claim 1, And a plurality of color filters formed under the protective film. The method of claim 5, Wherein the color filters overlap each other in the vicinity of a boundary. A plurality of gate lines and a plurality of data lines insulated from each other, a plurality of thin film transistors connected to the gate lines and the data lines, a plurality of pixel electrodes connected to the thin film transistors, and the gate lines A first display panel including a sustain electrode line overlapping the pixel electrode, A second display panel including a common electrode facing the pixel electrode, and And a black matrix provided on one of the first display panel and the second display panel, Lt; / RTI > Wherein the pixel electrode overlaps the entirety of the front gate line positioned between two neighboring data lines and the thin film transistor of the front gate line and does not overlap with the gate line of the pixel electrode, And the black matrix covers an area between the sustain electrode line and the gate line. 8. The method of claim 7, And the boundary of the pixel electrode is located between the sustain electrode line and the gate line. 8. The method of claim 7, And a plurality of color filters provided on any one of the first and second display panels. The method of claim 9, Wherein the color filter is provided on the first display panel and the black matrix is formed by overlapping the color filter.

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