KR100971955B1 - method for fabricating of an array substrate for a liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device.

The present invention relates to a method of manufacturing an array substrate for a liquid crystal display device using a three mask process, wherein a gate electrode, a gate wiring, and a gate pad are formed in a first mask process, and a second mask process (using a halftone mask). The active layer, the source and drain electrodes, the data wiring, and the data pad electrode are formed, and the protective film is patterned by the third mask process, and then the pixel electrode and the gate pad electrode and the data pad electrode are respectively contacted with the protective film as a mask. A gate pad electrode terminal and a data pad electrode terminal are formed.

When the array substrate for the liquid crystal display device is manufactured by the three mask process as described above, the process time can be shortened and the manufacturing cost can be reduced, thereby improving the process yield and increasing the price competitiveness.

Description

Method for fabricating of an array substrate for a liquid crystal display device             

1 is a plan view schematically illustrating a general liquid crystal display device;

2 is an enlarged plan view schematically showing a part of a conventional array substrate for a liquid crystal display device;

3A to 3G, 4A to 4G, and 5A to 5G are cross-sectional views of the process of cutting through III-III ′, IV-IV ′, and V-V ′ of FIG.

6 is an enlarged plan view illustrating an enlarged portion of an array substrate for a liquid crystal display device according to the present invention;

7A to 7H, 8A to 8H, and 9A to 9H are cross-sectional views illustrating cutting processes of Fig. 6 according to the process sequence of the present invention by cutting Figs. ego,

10, 11, and 12 are cross-sectional views taken along the lines of Figs. 6A, 11B, and 12B, and an inorganic insulating film pattern is further formed below the protective film.

Description of the Related Art

100: substrate 102: gate wiring                 

104: gate electrode 106: gate pad

134: second storage electrode 136: source electrode

138: drain electrode 140: data wiring

142: data pad 160: protective film

162: pixel electrode 164: gate pad electrode

166: data pad electrode

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device.

1 is a plan view schematically illustrating a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display device 11 includes a color filter 8 including a black matrix 6 and a sub color filter 7 and a transparent electrode deposited on the color filter 8. An upper substrate 5 having electrodes 9 formed thereon, a lower substrate 22 having an array wiring including a pixel region P and a pixel electrode 56 formed on the pixel region and a switching element T, The liquid crystal 15 is filled between the upper substrate 5 and the lower substrate 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 12 and the data wiring 34 passing through the plurality of thin film transistors cross each other. Is formed.

The pixel P area is an area where the gate line 12 and the data line 34 cross each other. The pixel electrode 56 formed on the pixel region P uses a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display configured as described above, the thin film transistor T and the pixel electrode 56 connected to the thin film transistor are present in a matrix to display an image.

The gate wiring 12 transfers a pulse voltage driving a gate electrode, which is a first electrode of the thin film transistor T, and the data wiring 34 receives a source electrode, which is a second electrode of the thin film transistor T. It is a means for transmitting the driving signal voltage.

The driving of the liquid crystal panel having the configuration as described above is due to the electro-optical effect of the liquid crystal.

In detail, the liquid crystal layer 15 is a dielectric anisotropic material having spontaneous polarization characteristics, and when a voltage is applied, bipolars are formed by spontaneous polarization to arrange molecules according to the direction of application of an electric field. This has changing characteristics.

Therefore, the optical characteristic is changed according to this arrangement state, thereby causing electrical light modulation.

By the light modulation phenomenon of the liquid crystal, the image is realized by a method of blocking or passing light.

The liquid crystal display device exhibiting the above operation is very complicated in manufacturing process, and efforts are being made to shorten the process time and manufacturing cost by simplifying the process.

As a part of this, conventionally, a manufacturing method capable of completing the manufacturing process of the thin film transistor array unit from a 5 to 7 mask process to a 4 mask process has been proposed.

2 is an enlarged plan view schematically illustrating a part of an array substrate for a liquid crystal display device manufactured by a conventional four mask process.

As shown in the drawing, the gate line 12 and the data line 34 are orthogonal to define the pixel area P, and at the intersection of the gate line 12 and the data line 34, a thin film transistor (S) is used as a switching element. T) is located.

A gate pad electrode 10 is formed at one end of the gate line 12, and a data pad electrode 36 is formed at one end of the data line 34.

Each of the pad electrodes 10 and 36 is in contact with the gate pad electrode terminal 58 and the data pad electrode terminal 60 which are island-shaped transparent electrode patterns.

The thin film transistor T is connected to the gate line 12 to receive a scan signal, a gate electrode 14, a source electrode 40 connected to the data line 34 to receive a data signal, and a predetermined value. And drain electrodes 42 spaced apart from each other.

In addition, the gate electrode 14 includes an active layer 32 formed on the gate electrode 14 and in contact with the source electrode 40 and the drain electrode 42.                         

In addition, a transparent pixel electrode 56 is formed on the pixel region P in contact with the drain electrode 42, and a part of the transparent pixel electrode 56 extends over the gate wiring 12. do.

An island-shaped metal pattern 38 is formed on the gate line 12, and the metal pattern 38 contacts the transparent pixel electrode 56 extending over the gate line 12.

In the above-described configuration, a part of the gate wiring 12 is used as the first storage electrode, and the metal pattern 28 in contact with the pixel electrode 17 is used as the second storage electrode, and the first and second A storage capacitor C having a gate insulating film (not shown) positioned between two storage electrodes as a dielectric is configured.

In this case, although not shown, an ohmic contact layer (not shown) is formed between the active layer 30 and the source and drain electrodes 40 and 42, and a pure amorphous silicon layer forming the active layer and the ohmic contact layer. The impurity amorphous silicon layer is patterned to form a first pattern 35 extending below the data line 34 and the data pad electrode 36, and a second pattern 29 formed below the metal pattern 28. ) Is formed.

The configuration of the array substrate as described above is manufactured by a conventional four mask process, and a manufacturing process of the array substrate using the conventional four mask process will be described with reference to the drawings.

3A to 3G, 4A to 4G, and 5A to 5G are cut along the lines III-III ′, IV-IV ′, and V-V ′ of FIG. 2 to show a conventional four mask process sequence. 3A to 3G show a switching element, a pixel region, and a storage capacitor, FIGS. 4A to 4G show a gate pad portion, and FIGS. 5A to 5G show a data pad portion.

First, as shown in FIGS. 3A, 4A, and 5A, a first metal layer is formed on a transparent insulating substrate 22, and then a gate wiring including a gate pad electrode 10 at one end thereof in a first mask process. 12 and a gate electrode 14 protruding from the gate line 12.

The gate electrode material may use various conductive metals such as aluminum (Al), aluminum alloy, molybdenum (Mo), tungsten (W), and chromium (Cr). Particularly, in the case of using aluminum (Al) and aluminum alloy, molybdenum It is composed of a double layer using (Mo) or chromium (Cr).

The gate insulating film 16 serving as the first insulating film, the pure amorphous silicon layer 18, and the impurity amorphous silicon layer 20 are formed on the entire surface of the substrate 22 on which the gate wiring 12, the gate pad electrode 10, and the like are formed. And the second metal layer 24 are laminated.

In this case, the first insulating layer 16 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ), and the second metal layer 24 is formed of chromium (Cr). ), Molybdenum (Mo), tungsten (W), tantalum (Ta) and the like selected from a conductive metal material is formed by depositing.

The data region D, the pixel region P, and the storage region S, which include a switching element region T on the substrate 22 on which the plurality of layers are stacked, and data lines and data pad electrodes formed in a subsequent process. ).

In this case, the switching element region T is defined at one side of the pixel region P. FIG.

Next, as shown in FIGS. 3B, 4B, and 5B, a photoresist (hereinafter, referred to as “PR”) is formed on the second metal layer 24 in which the plurality of regions D, T, P, and S are defined. The "layer" is applied to form the PR layer 26. At this time, the PR layer 26 is to use a positive type (positive type) in which the lighted portion is exposed and developed.

The mask 50 including the transmissive area A, the blocking area B, and the transflective area (slit area) C is positioned on the substrate 22 on which the PR layer 26 is formed.

The transflective region C is positioned to correspond to the upper portion of the gate electrode 14 of the switching region T, and the reflector B corresponds to the data region D and the storage region S. Position it.

In this case, the PR layer 26 corresponding to the transflective region C has a characteristic of exposing only a portion of the PR layer 26 as compared with the transmissive region A. FIG.

Subsequently, an exposure step of irradiating light onto the mask 50 and a development step of removing the exposed part are performed.

When the above process is performed, as shown in FIGS. 3C, 4D, and 5D, the PR layer 26 patterned in the switching region T, the storage region S, and the data wiring region D is formed. Is formed.

After etching the second metal layer 24 exposed between the patterned PR layer 26 by a wet etching method, the lower impurity amorphous silicon layer 20 and the pure amorphous silicon layer 18 are removed by dry etching. 3D, 4D, and 5D, a source / drain electrode pattern 28 may be formed in the switching region T, and a source / drain electrode pattern 28 may be formed in the data wiring region D. Referring to FIGS. An extended data line 34 and a data pad electrode 36 are formed at one end of the data line.

At the same time, an island-shaped metal pattern 38 is formed on a portion of the gate wiring 12.

The patterned pure amorphous silicon layer and the impurity amorphous silicon layer may include a first pattern 35 extending from the lower portion of the source / drain electrode pattern 28 to the lower portion of the data line 34 and the data pad electrode 36. The second pattern 29 having an island shape is formed under the metal pattern 38.

At this time, the pure amorphous silicon layer formed under the first pattern formed in the switching region T is called the active layer 30, and the impurity amorphous silicon layer formed on the active channel layer 30 is the ohmic contact layer 32. )

Next, as shown in FIGS. 3E, 4E, and 5E, an ashing process for removing the PR layer formed on the upper portion of the channel as a previous process for forming the channel CH in the switching region T is performed. processing.

When the ashing process is performed, the thin PR layer that has been partially exposed on the gate electrode 14 is removed, and the periphery F of each of the PR patterns 26 is scraped off to lower the metal patterns 28 and 34. (Data wirings), 38, 36 (data pad electrodes)) are exposed.                         

Subsequently, a process of removing the metal layer exposed between the PR patterns 26 and the impurity amorphous silicon layer under the dry process through dry etching is performed to expose the pure amorphous silicon layer below.

In this case, when the metal layer exposed between the patterned PR layers 26 is molybdenum (Mo), it is possible to remove the metal layer exposed by dry etching and the impurity amorphous silicon layer thereunder at once, but the metal layer is chromium (Cr) In one case, the metal layer exposed between the PR patterns is first removed by wet etching, and then a process of removing the impurity amorphous silicon layer below the dry etching is performed.

3F, 4F, and 5F, the source / drain electrode patterns are once again patterned in the switching region T, so that the source electrode 40 and the drain electrode 42 are spaced apart from each other. ) Is formed and the active channel region CH of the active layer 30 is exposed while being spaced apart from each other.

As described above, an island shape is formed on the active layer 32, the source and drain electrodes 40 and 42, the data line 34, the data pad electrode 36, and the gate line 12 through the second mask process. Metal layer 38 is formed.

Subsequently, benzocyclobutene (BCB) is formed on the entire surface of the substrate 22 on which the source and drain electrodes 40 and 42, the data line 34, the data pad electrode 36, and the island-shaped metal layer 38 are formed. It is formed by applying one selected from the group of transparent organic insulating materials including acrylic resin (resin), or selected from the group of inorganic insulating materials containing silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). It deposits and forms the protective film 46 which is a 2nd insulating film.

Next, the passivation layer 46 is patterned in a third mask process, so that the drain contact hole 48 exposing a part of the drain electrode 42 and the storage contact hole exposing a part of the metal layer 38. 50, a gate pad contact hole 52 and a data pad contact hole 54 exposing portions of the gate pad electrode 10 and the data pad electrode 36 are formed.

Subsequently, as shown in FIGS. 3G, 4G, and 5G, one selected from a transparent conductive metal material including indium tin oxide (ITO) and indium zinc oxide (IZO) on top of the passivation layer 46. A transparent pixel electrode 56 which is deposited and patterned by a fourth mask process to contact the drain electrode 42 and passes through the pixel region P to contact the island-shaped metal layer 38, and the gate pad electrode. A gate pad electrode terminal 58 in contact with the electrode 10 and a data pad electrode terminal 60 in contact with the data pad electrode 36 are formed.

In the above-described process, an array substrate for a liquid crystal display device according to a conventional method can be manufactured.

The present invention has been made for the purpose of further simplifying the above-described four mask process to obtain improved process yield and to reduce material costs. The method of manufacturing an array substrate according to the present invention uses a halftone mask. Patterning a protective film protecting the thin film transistor in a predetermined shape and etching the lower gate insulating film using the mask as a mask; and forming the pixel electrode, the gate pad electrode terminal, and the data pad electrode terminal. An array substrate for a liquid crystal display device is manufactured by a mask process.

According to an exemplary embodiment of the present invention, an array substrate for a liquid crystal display device includes: a gate wiring formed on a substrate on which a pixel region is defined, and a gate pad electrode provided at one end of the gate wiring; A gate insulating layer formed on the gate line to expose the gate pad electrode and the substrate in the pixel region; A data line and a data pad electrode disposed at one end of the data line to vertically intersect the gate line to define the pixel area; A thin film transistor configured at an intersection point of the gate line and the data line, the thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; A passivation layer formed on the entire surface of the substrate including the thin film transistor and exposing the drain electrode, the gate pad electrode, the data pad electrode, and a substrate corresponding to the pixel region; A transparent pixel electrode configured to be in contact with the substrate on the substrate in the pixel region while being in contact with the exposed drain electrode; and a transparent pixel electrode which is in contact with the exposed gate pad electrode and completely covers the top and side surfaces of the gate pad electrode. And a gate pad electrode terminal and a transparent data pad electrode terminal in contact with the exposed data pad electrode and completely covering the top and side surfaces of the data pad electrode.

A semiconductor layer in which an amorphous silicon layer and an amorphous silicon layer including impurities are stacked below the source and drain electrodes, the data lines, and the data pad electrodes is formed.

A lower amorphous silicon layer is exposed around the source and drain electrodes, the data line, and the data pad electrode.

An island metal layer is formed on an upper portion of the gate wiring that defines the pixel region, and the passivation layer is configured to expose a portion of the island metal layer.

In this case, the pixel electrode contacts the exposed metal layer to form a storage capacitor having the gate wiring as the first electrode and the metal layer as the second electrode.

An inorganic insulating pattern is disposed between the passivation film, the thin film transistor, the gate wiring, and the data wiring, and has the same shape as the passivation film in plan view.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: forming a gate line, a gate pad electrode at one end of the gate line, and a gate electrode extending from the gate line on a substrate on which a pixel region is defined; A mask processing step; A data line defining the pixel region by crossing the gate insulating layer vertically with the gate insulating layer interposed therebetween, a data pad electrode at one end of the data line, a source electrode extending from the data line, and a drain spaced apart from the predetermined distance. A second mask process step of forming an active layer under the source and drain electrodes; In a third mask process of forming and patterning a protective film on the entire surface of the substrate on which the source and drain electrodes and the data wiring are formed, the protective film and the gate insulating film are sequentially patterned to form a substrate in the drain electrode and the pixel region, Exposing the gate pad electrode and the data pad electrode; Depositing a transparent electrode on the front surface of the patterned passivation layer, contacting the exposed drain electrode with the pixel electrode formed on the substrate in the pixel region, and contacting the exposed gate pad electrode with the top and side surfaces of the gate pad electrode; And forming a data pad electrode terminal in contact with the exposed data pad electrode and completely covering the top and side surfaces of the data pad electrode. It includes.

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In the second mask process, a gate insulating film, a pure amorphous silicon film, an impurity amorphous silicon film, and a metal layer are sequentially stacked on the entire surface of the substrate on which the gate wiring and the gate electrode are formed, and a switching area and a data wiring area are defined. Making a step;

Forming a photoresist layer on the metal layer, and placing a mask including a transmissive part, a blocking part, and a transflective part on the photoresist layer; Irradiating light to the upper portion of the mask to expose and develop a lower photoresist layer, leaving a stepped first photoresist pattern in the switching region, and leaving a second photoresist pattern in the data wiring region; Etching the exposed metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer between the remaining photoresist patterns; Performing an ashing process to remove the remaining photoresist pattern, exposing a central portion of the switching region; Removing the exposed metal layer and the pure amorphous silicon layer below and removing the remaining photoresist pattern, a data line including a source electrode and a drain electrode spaced apart from each other by a predetermined distance, and a data pad electrode extending from the source electrode at one end thereof. Forming a step.

The third mask process may include: heat treating the patterned passivation layer so that a surface thereof melts into an arc shape so that side surfaces of the patterned passivation layer are reverse tapered; And cutting the deposited transparent electrode by the reverse tapered side of the passivation layer so that the pixel electrode, the gate pad electrode terminal, and the data pad electrode terminal are independently configured.

In this case, a lower amorphous silicon film is exposed to the periphery of the source and drain electrodes, the data line, and the data pad.

And forming an island metal layer on the gate line defining the pixel region, wherein the passivation layer is formed to expose a portion of the island metal layer.

In this case, the pixel electrode is in contact with the exposed metal layer to form a storage capacitor having the gate wiring as the first electrode and the metal layer as the second electrode.

And forming an inorganic insulating layer between the source and drain electrodes, the data line, and the passivation layer, wherein the inorganic insulating layer is patterned using the passivation layer as an etch stop layer and formed in the same shape as the passivation layer in plan view. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

A feature of the present invention is to fabricate an array substrate for a liquid crystal display device in a three mask process.

6 is a plan view schematically illustrating a part of an array substrate for a liquid crystal display according to the present invention.

As shown, the gate line 102 and the data line 132 are orthogonal to the substrate 100 to define the pixel region P, and the gate line 112 and the data line 132 are perpendicular to each other. The thin film transistor T is formed of a switching element.

A gate pad electrode 106 is formed at one end of the gate wiring 102, a data pad electrode 142 is formed at one end of the data wiring 132, and each pad electrode 106 and 142 has an island shape. The gate pad electrode terminal 164 and the data pad electrode terminal 166 which are transparent electrode patterns overlap with each other in plan view.

The thin film transistor T is connected to the gate wiring 102 to receive a scan signal, a gate electrode 104, a source electrode 136 connected to the data wiring 132 to receive a data signal, and a predetermined value. The drain electrodes 138 are spaced apart from each other.

A pixel electrode 162 is formed in the pixel region P in contact with the drain electrode 138, and an island-shaped metal layer 134 is formed on a portion of the gate wiring 102 defining the pixel region P. To form.

The metal pattern 138 forms a storage capacitor C together with the lower gate wiring 102, the gate wiring 102 serves as a first storage electrode, and the metal pattern 134 is the pixel electrode. Contact with 162 serves as a second storage electrode.                     

In the above-described configuration, in the process of patterning the source and drain electrodes 136 and 138, the second storage electrode 134, the data line 132, and the data pad electrode 142, the lower impurity amorphous silicon layer and the pure amorphous silicon. The layer is patterned, and for convenience, the lower portion of the source and drain electrodes 136 and 138 is called the first pattern 126 of the semiconductor layer, and the first pattern 126 of the data line 132 and the data pad electrode 142 is formed. A portion extending downward is referred to as a second pattern 130 and a portion formed under the second storage electrode 134 is referred to as a third pattern 128.

In this case, the first pattern 126, the second pattern 130, and the third pattern 128 of the semiconductor layer may include the source and drain electrodes 136 and 138, the data line 132, and the data pad electrode 142 and the first pattern 126. 2 is a shape exposed to the periphery of the storage electrode 134. (In detail, the pure amorphous silicon layer of the semiconductor layer is exposed.)

In the above-described configuration, a feature of the present invention is that the passivation layer 162 is formed on the entire surface of the substrate 100 while only the pixel electrode 162, the data pad electrode terminal 164, and the gate pad electrode terminal 166 are exposed. This is to be formed.

This is described below through fabricating an array substrate using a three-mask process for forming the pixel electrode 162, the data pad electrode terminal 164, and the gate pad electrode terminal 166 using the passivation layer as a mask. have.

Hereinafter, a manufacturing process of the liquid crystal display according to the present invention will be described with reference to FIGS. 7A to 7H, 8A to 8H, and 9A to 9H.

7A to 7H, 8A to 8H, and 9A to 9H are cross sectional views taken along the lines VII-VII, VII-VII, and VII-III of FIG. 6 and shown in the process sequence of the present invention.

7A to 7H are cross-sectional views of the switching region, the pixel region, and the storage capacitor region, and FIGS. 8A to 8H are cross-sectional views of the gate pad portion, and FIGS. 9A to 9H are cross-sectional views of the data pad portion.

7A, 8A, and 9A, a first mask is formed by depositing and patterning a conductive metal such as aluminum (Al), tungsten (W), molybdenum (Mo), and chromium (Cr) on the substrate 100. In the process, the gate electrode 102, the gate electrode 104 protruding in one direction from the gate wire, and the gate pad electrode 106 are formed at one end of the gate wire 102.

At this time, the material of the gate electrode 104, which is important for the operation of the active matrix liquid crystal display, is mainly composed of aluminum having low resistance to reduce the RC delay, but pure aluminum is chemically resistant to corrosion and subsequent high temperature processes. In the case of aluminum wiring, it is used in the form of an alloy or a laminated structure is applied because it causes a wiring defect problem due to the formation of a hillock.

Next, as illustrated in FIGS. 7B, 8B, and 9B, silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 100 on which the gate wiring 102, the gate electrode 104, and the gate pad electrode 106 are formed. ) And an inorganic insulating material such as silicon nitride (SiN _X ) and an organic insulating material such as benzocyclobutene (BCB) and acrylic resin (resin) in some cases, to form a gate insulating film 108 do.

Subsequently, a pure amorphous silicon layer (a-Si: H) 110, an impurity amorphous silicon layer (n + a-Si: H) 112, and a second metal layer 114 are disposed on the gate insulating layer 108. Form.

Subsequently, a photoresist (hereinafter referred to as PR) is applied on the second metal layer to form a PR layer 116.

The second metal layer 114 is formed by depositing one selected from a group of conductive metals such as chromium (Cr), molybdenum (Mo), tungsten (W), and tantalum (Ta).

Next, the pixel region P, the switching element region, the data wiring region D, and the storage region S are defined on the substrate 100 on which the PR layer 116 is formed.

In this case, the switching element region T is defined on one side of the pixel region P. FIG.

Subsequently, a mask M including a transmissive portion A, a transflective portion C, and a blocking portion B is positioned on a spaced upper portion of the substrate 100.

In this case, the blocking part B of the mask M corresponds to the data wiring area D, the storage area S, and the periphery of the switching area T, and the semi-transmissive part C is the switching. It is positioned to correspond to the upper portion of the gate electrode 104 in the region (T).

The process of exposing and developing the PR layer 116 formed on the substrate 100 by irradiating light from the upper portion of the mask M is performed.

As a result, as shown in FIGS. 7C, 8C, and 9C, a portion corresponding to the transflective portion (C of FIG. 7B) of the mask M is partially developed on the upper portion of the switching region T. The other PR pattern 120a is left, and the PR pattern 120b remains on the data wiring area D and the storage area S at the same height as applied.

Next, the second metal layer 114, the impurity amorphous silicon layer 112, and the pure amorphous silicon layer 110 exposed between the remaining PR patterns 120a and 120b are removed, and the PR pattern is successively determined from above. Ashing processing is performed by cutting only the height.

In this case, as illustrated in FIGS. 7D, 8D, and 9D, the source / drain metal pattern 124 is formed corresponding to the switching region T, and the periphery portion of the source drain metal pattern 124 ( The PR pattern 122a remains in a state in which F) and the center portion E are exposed.

Of course, an island-shaped metal pattern 134 remains in the storage area S, the data wiring area D is connected to the source / drain metal pattern 124, and a data pad electrode 142 is formed at one end thereof. And a data pattern 132 including the PR pattern 122b that exposes the island-shaped metal pattern 134 and the peripheral portion F of the data wiring and the data pad electrodes 132 and 142. Will remain.

Subsequently, after the metal exposed between the remaining PR patterns 122a and 122b and the amorphous silicon layer below it are removed, the remaining PR patterns 122a and 122b are removed.

In this case, as illustrated in FIGS. 7E, 8E, and 9E, the source electrode 136, the drain electrode 138, and the source electrode 136 spaced apart from each other by a predetermined distance corresponding to the switching region T. ) And a data line 132 extending to the data line region D and perpendicularly intersecting with the gate line 102, and a data pad electrode 142 at an end of the data line.

At the same time, an island-shaped second storage electrode 134 is formed on a portion of the gate wiring 102 defining the pixel region.

In the above-described process, the patterned impurity amorphous silicon layer and the pure amorphous silicon layer are referred to as semiconductor layers for convenience, and the semiconductor layer may include a first pattern 126 disposed under the source and drain electrodes 136 and 138, and The second pattern 130 extends through the data line 132 and the data pad electrode 142, and a third pattern 128 disposed under the second storage electrode 134.

Each of the impurity amorphous silicon layers 126b, 130b, and 128b and the pure amorphous silicon layers 126a, 130a, and 128a are stacked.

In this case, the data lines 132, the data pad electrodes 142, the source and drain electrodes 136 and 138, and the lower amorphous silicon layers 130a, 126a, and 128a are exposed to the periphery of the second storage electrode 134. It becomes a shape.

Next, a passivation layer 160 may be formed by coating a photosensitive organic insulating layer on the entire surface of the substrate 100 on which the source and drain electrodes 136 and 138, the data line 132, the data pad electrode 142, and the second storage electrode 146 are formed. ). Examples of the photosensitive organic film include benzocyclobutene (BCB) and acryl resin.

Subsequently, the protective film 160 is exposed and developed by a third mask process, and as shown in FIGS. 7F, 8F, and 9F, except for the switching element T and the data pad electrode 142, the data wirings. 132, an upper portion of the gate wiring 102 except for the gate pad electrode 106, an upper portion of the second storage electrode 146, between each data pad electrode 142, and the gate pad electrode 106. The patterned passivation film (the same reference numerals before the pattern is used for convenience) 160 is left in the corresponding position between the two portions.

At this time, the patterned passivation layer 160 is cured at a predetermined temperature so that the surface of the passivation layer 160 is rounded in cross section (arc).

That is, one side of the patterned passivation layer 160 should be formed to be inversely tapered so that the angle is less than 90 degrees.

In order to do this, the method of dividing may be used instead of performing the curing at once.

As shown in FIGS. 7G, 8G, and 9G, the gate insulating layer 108 exposed between the patterned passivation layer 160 is etched to expose the gate pad 106.

Subsequently, as shown in FIGS. 7H, 8H, and 9H, indium tin oxide (ITO) and indium zinc oxide (IZO) are formed on the entire surface of the substrate 100 on which the patterned passivation layer 160 is formed. A pixel electrode 162 positioned in the pixel region P while being in contact with the exposed drain electrode 138 and the second storage electrode 146 by depositing a transparent conductive metal including a gate electrode and the exposed gate pad; A gate pad electrode terminal 164 having a shape surrounding the electrode 106 and a data pad electrode terminal 166 having a shape surrounding the data pad 142 are formed.

In this case, since the side surface of the passivation layer 160 is formed to be reverse tapered, the transparent electrode may be formed in an independent pattern by being cut off by the reverse taper of the passivation layer, even though the transparent electrode is deposited on the entire surface of the substrate 100. .

Therefore, as described above, by using the protective film as the photosensitive organic film as a mask, it is possible to produce an array substrate for a liquid crystal display device in a three mask process.

In the above-described process, the protective film 160 made of an organic film is formed directly on the thin film transistor T, but the contact characteristics between the protective film 160 and the active layer 126a of the thin film transistor T are improved. To this end, an inorganic insulating layer pattern may be further formed between the passivation layer 160 and the thin film transistor.

A description with reference to FIGS. 10, 11, and 12 is as follows.

10, 11, and 12 are cross-sectional views taken along the line VIII-VIII, VIII-VIII, VIII-VIII in Fig. 6.

As illustrated, an inorganic insulating layer pattern 143 is formed between the thin film transistor T and the organic passivation layer 160. The inorganic insulating layer pattern 143 is formed through a process of patterning the organic passivation layer 160 as an etch stop layer.

In detail below, after forming the source and drain electrodes 136 and 138 and the data line 132 of the thin film transistor T, an inorganic insulating material group including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) After depositing the selected one of the inorganic insulating film is formed.

Next, as described above, after forming the patterned organic passivation layer 160 on the inorganic insulating layer, the inorganic insulating layer and the lower gate insulating layer exposed between the passivation layers are formed by using the passivation layer 160 as an etch stop layer. The etching process may be performed.

Subsequently, a transparent conductive metal including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the substrate 100 on which the passivation layer 160 is formed, thereby exposing the exposed drain electrode 138. ) And the pixel electrode 162 positioned in the pixel region P while being in contact with the second storage electrode 146, the gate pad electrode terminal 164 having a shape surrounding the exposed gate pad electrode 106; The data pad electrode terminal 166 is formed to surround the data pad 142.

As described above, the inorganic insulating film pattern 143 is further formed between the thin film transistor T, the data wire 132, the gate wire 102, and the passivation layer 160. Compared with the organic layer, the interfacial characteristics of the thin film transistor T with the active layer 126a are better, so that the operating characteristics of the thin film transistor T are improved.

In addition, a defect that the organic passivation layer 160 is lifted on the gate and the data lines 102 and 132 may be prevented by the inorganic layer insulating layer pattern 143.

According to the above-described process, an array substrate for a liquid crystal display device according to the present invention can be manufactured.

When the array substrate is manufactured by the three-mask process according to the present invention, it is possible to reduce the material cost and shorten the process time, thereby increasing the price competitiveness, and thus reducing the process error occurring in a plurality of processes as much as possible. It is effective in improving process yield.

Claims (16)

A gate wiring formed on a substrate having a pixel region defined therein and a gate pad electrode provided at one end of the gate wiring; A gate insulating layer formed on the gate line to expose the gate pad electrode and the substrate in the pixel region; A data line and a data pad electrode disposed at one end of the data line to vertically intersect the gate line to define the pixel area; A thin film transistor configured at an intersection point of the gate line and the data line, the thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; A passivation layer formed on the entire surface of the substrate including the thin film transistor and exposing the drain electrode, the gate pad electrode, the data pad electrode, and a substrate corresponding to the pixel region; A transparent pixel electrode formed on and in contact with the substrate on the substrate in the pixel region while being in contact with the exposed drain electrode; a transparent pixel electrode which is in contact with the exposed gate pad electrode and completely covers the top and side surfaces of the gate pad electrode. A transparent data pad electrode terminal formed on the gate pad electrode terminal and in contact with the exposed data pad electrode and completely covering the top and side surfaces of the data pad electrode; Array substrate for a liquid crystal display device comprising a. The method of claim 1, And an amorphous silicon layer and an amorphous silicon layer containing impurities are stacked below the source and drain electrodes, the data line, and the data pad electrode. The method of claim 2, And a lower amorphous silicon layer exposed around the source and drain electrodes, the data line, and the data pad electrode. The method of claim 1, And an island-shaped metal layer formed on an upper portion of a gate line defining the pixel area. The method of claim 4, wherein And the passivation layer is configured to expose the island-like metal layer. The method of claim 5, And the pixel electrode is in contact with the exposed metal layer to form a storage capacitor having the gate wiring as the first electrode and the metal layer as the second electrode. The method of claim 1, And an inorganic insulating film pattern disposed between the passivation film, the thin film transistor, the gate wiring, and the data wiring, and having an inorganic insulating film pattern in planar shape with the passivation film. A first mask process step of forming a gate line, a gate pad electrode at one end of the gate line, and a gate electrode extending from the gate line on a substrate on which a pixel region is defined; A data line defining the pixel region by crossing the gate insulating layer vertically with the gate insulating layer interposed therebetween, a data pad electrode at one end of the data line, a source electrode extending from the data line, and a drain spaced apart from the predetermined distance. A second mask process step of forming an active layer under the source and drain electrodes; In the third mask process of forming and patterning a protective film on the entire surface of the substrate on which the source and drain electrodes and the data wiring is formed, Sequentially patterning the passivation layer and the gate insulating layer to expose the drain electrode and the substrate in the pixel region, and the gate pad electrode and the data pad electrode; Depositing a transparent electrode on the front surface of the patterned passivation layer, contacting the exposed drain electrode with the pixel electrode formed on the substrate in the pixel region, and contacting the exposed gate pad electrode with the top and side surfaces of the gate pad electrode; And forming a data pad electrode terminal in contact with the exposed data pad electrode and completely covering the top and side surfaces of the data pad electrode. Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 8, In the second mask process, the gate insulating film, the pure amorphous silicon film, the impurity amorphous silicon film, and the metal layer are sequentially stacked on the entire surface of the substrate on which the gate wiring and the gate electrode are formed. Defining; Forming a photoresist layer on the metal layer, and placing a mask including a transmissive part, a blocking part, and a transflective part on the photoresist layer; Irradiating light to the upper portion of the mask to expose and develop a lower photoresist layer, leaving a stepped first photoresist pattern in the switching region, and leaving a second photoresist pattern in the data wiring region; Etching the exposed metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer between the remaining photoresist patterns; Performing an ashing process to remove the remaining photoresist pattern, exposing a central portion of the switching region; The exposed metal layer and the lower pure amorphous silicon layer are removed and the remaining photoresist pattern is removed to form a data line including a source electrode and a drain electrode spaced apart from each other, and a data pad electrode extending from the source electrode and at one end thereof. Array substrate manufacturing method for a liquid crystal display device comprising the step of. The method of claim 9, The third mask process may include: heat treating the patterned passivation layer so that a surface thereof melts into an arc shape so that side surfaces of the patterned passivation layer are reverse tapered; And cutting the deposited transparent electrode by the reverse tapered side of the passivation layer so that the pixel electrode, the gate pad electrode terminal, and the data pad electrode terminal are independently configured. . The method of claim 8, And a lower amorphous silicon film exposed around the source and drain electrodes, the data line, and the data pad. The method of claim 8, And forming an island-shaped metal layer on the gate line defining the pixel region. The method of claim 8, And the passivation layer is formed to expose the island-shaped metal layer. The method of claim 13, And the pixel electrode is in contact with the exposed metal layer to form a storage capacitor having the gate wiring as the first electrode and the metal layer as the second electrode. The method of claim 8, And forming an inorganic insulating layer between the source and drain electrodes, the data line, and the passivation layer. The method of claim 15, And the inorganic insulating layer is patterned using the passivation layer as an etch stop layer and formed in the same shape as the passivation layer in plan view.

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