KR100969622B1 - Liquid Crystal Display Panel and Method of Fabricating the same - Google Patents

Abstract

The present invention relates to a horizontal field application type liquid crystal display panel capable of improving contrast ratio and a method of manufacturing the same.

The present invention is a gate line formed on a substrate; A data line intersecting the gate line and the gate insulating layer so as to be insulated so as to determine a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A protective film formed on the gate insulating film to protect the thin film transistor; A common line formed in parallel with the gate line on the passivation layer of the pixel region; A common electrode formed on the passivation layer of the pixel region and connected to the common line; A horizontal portion parallel to the gate line and connected to the thin film transistor, and a finger portion protruding from the horizontal portion to form a horizontal electric field with the common electrode and parallel to the common electrode; A pixel electrode; At least one of the gate insulating layer and the passivation layer overlaps the finger and the common electrode of the pixel electrode, and overlaps the portion of the horizontal part while maintaining a predetermined distance from the gate line. And a light blocking layer formed to overlap all of the edges of the common line facing the pixel electrode while maintaining a predetermined interval therebetween.

Description

Horizontal field-applied liquid crystal display panel and its manufacturing method {Liquid Crystal Display Panel and Method of Fabricating the same}             

1 is a plan view showing a thin film transistor array substrate of a conventional horizontal field application liquid crystal display panel.

FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along line II ′ in FIG. 1.

3 is a cross-sectional view illustrating an alignment non-uniformity phenomenon of a liquid crystal due to a step between a pixel electrode and a common electrode illustrated in FIG. 2.

4 is a cross-sectional view illustrating a thin film transducer array substrate including a pixel electrode and a common electrode formed of a conventional data metal.

5A and 5B are diagrams illustrating light leakage due to electrode steps formed of gate metal and data metal, respectively.

6 is a plan view illustrating a thin film transistor array substrate of a horizontal field application type liquid crystal display panel according to a first exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating the thin film transistor array substrate taken along the line II-II ′ of FIG. 6.                 

8 is a plan view illustrating another form of the light blocking layer illustrated in FIG. 6.

9A to 9E are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 7.

10 is a cross-sectional view illustrating a thin film transistor array substrate of a horizontal field applied liquid crystal display panel according to a second exemplary embodiment of the present invention.

11A and 11B are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 10.

12 is a plan view illustrating a thin film transistor array substrate of a horizontal field applied liquid crystal display panel according to a third exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating a thin film transistor array substrate taken along line III-III ′ in FIG. 12.

FIG. 14 is a plan view illustrating another form of the light blocking layer illustrated in FIG. 12. FIG.

15A to 15E are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 13.

16 is a cross-sectional view illustrating a thin film transistor array substrate of a horizontal field applied liquid crystal display panel according to a fourth exemplary embodiment of the present invention.

17A and 17B are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 16.

FIG. 18 is a cross-sectional view of a liquid crystal uniformly oriented on a lower substrate having a light blocking layer according to the first to fourth embodiments of the present invention. FIG.                 

19A and 19B are cross-sectional views illustrating a role of a light blocking layer formed to overlap a pixel electrode and a common electrode.

         <Explanation of symbols for main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10 source electrode 12, 112 drain electrode

      14, 114: pixel electrodes 16, 116: common line

18, 118: common electrode 52, 152: protective films 109, 209: light blocking layer 46, 146: gate insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a horizontal field application type liquid crystal display panel capable of improving contrast ratio and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal display devices are classified into vertical electric field types and horizontal electric field types according to the direction of the electric field for driving the liquid crystal.

In the vertical field type liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. Such a vertical field type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

In a horizontal field type liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The horizontal field type liquid crystal display device has an advantage that a viewing angle is about 160 degrees. Hereinafter, the horizontal field type liquid crystal display device will be described in detail.

The horizontal field type liquid crystal display device includes a thin film transistor array substrate (lower substrate) and a color filter array substrate (upper substrate) bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal space provided by the spacer. Liquid crystal filled in.

The thin film transistor array substrate is composed of a plurality of signal lines and thin film transistors for forming a horizontal electric field in pixels, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

1 is a plan view illustrating a thin film transistor array substrate of a conventional horizontal field type liquid crystal display panel, and FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along line II ′ in FIG. 1.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed to intersect on the lower substrate 45, a thin film transistor 6 formed at each intersection thereof, and an intersection thereof. The pixel electrode 14 and the common electrode 18 formed to form a horizontal electric field in the pixel region provided in the structure are provided, and the common line 16 connected to the common electrode 18 is provided.

The gate line 2 supplies a gate signal to the gate electrode 8 of the thin film transistor 6. The data line 4 supplies the pixel signal to the pixel electrode 14 through the drain electrode 12 of the thin film transistor 6. The gate line 2 and the data line 4 are formed in an intersecting structure to define the pixel region 5.

The common line 16 is formed in parallel with the gate line 2 with the pixel region 5 therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 16.

The thin film transistor 6 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 14 in response to the gate signal of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 further includes an active layer 48 that overlaps with the gate electrode 8 and the gate insulating layer 46 therebetween to form a channel between the source electrode 10 and the drain electrode 12. . An ohmic contact layer 50 for ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 48.                         

The pixel electrode 14 is formed in the pixel region 5 of the same metal as the drain electrode 12 of the thin film transistor 6. In particular, the pixel electrode 14 is connected to the drain electrode 12 and has a first horizontal portion 14A formed in parallel with the adjacent gate line 2 and a second horizontal portion 14B formed so as to overlap the common line 16. ) And a finger portion 14C formed parallel to the common electrode 18 between the first and second horizontal portions 14A and 14B.

The common electrode 18 is connected to the common line 16 to be formed of the same metal as the gate line 2 and the gate electrode 8 in the pixel region 5. In particular, the common electrode 18 is formed in the pixel region 5 to be parallel to the finger portion 14C of the pixel electrode 14.

Accordingly, a horizontal electric field is formed between the pixel electrode 14 supplied with the pixel signal through the thin film transistor 6 and the common electrode 18 supplied with the reference voltage through the common line 16. In particular, a horizontal electric field is formed between the finger portion 14C of the pixel electrode 14 and the common electrode 18. The horizontal electric field causes liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region 5 is changed, thereby realizing an image.

The common electrode 18 formed of the same material as the gate electrode 8 and the pixel electrode 14 formed of the same material as the drain electrode 12 have a thickness difference. That is, the common electrode 18 is formed to have a thickness of about 2500 mW, while the pixel electrode 14 is formed to have a thickness of about 1500 mW. When this is described in detail, a hill lock occurs in which aluminum neodium (AlNd) constituting the common electrode 18 grows to a predetermined number of micrometers above a predetermined temperature. In order to prevent this, aluminum neodium (AlNd) must be deposited a plurality of times, thereby forming a relatively thick common electrode 18. In contrast, since the chromium (Cr) forming the pixel electrode 14 does not generate hillocks and does not require a plurality of deposition processes, the pixel electrode 14 is formed relatively thin.

Accordingly, a first step D1 equal to the thickness of the common electrode 18 is generated between the common electrode 18 and the lower substrate 48, and the pixel electrode 14 and the gate insulating film are formed. On the 46, a second step D2 corresponding to the thickness of the pixel electrode 14 is generated. That is, the second step D2 has a height lower than that of the first step D1.

The first and second steps D1 and D2 are maintained even after the passivation layer 52 formed on the pixel electrode 14 is formed, resulting in poor rubbing of the alignment layer. That is, the common electrode region having the first step D1 having a relatively high height and the second step D2 having a relatively low height are formed by the height difference between the first step D1 and the second step D2. The rubbing of the alignment film in the pixel electrode region becomes uneven. Due to the rubbing unevenness of the alignment layer, as shown in FIG. 3, the liquid crystal corresponding to the second step D2 has a predetermined inclination, and the liquid crystal corresponding to the first step D1 has a relatively high inclination. This will occur.

Due to the light leakage phenomenon, the black luminance of the liquid crystal panel is increased to increase the contrast ratio.

In addition, due to the difference in the inclination of the respective liquid crystal corresponding to the first and second steps D1 and D2, the amount of light leakage becomes uneven, resulting in uneven brightness.

In order to prevent such a decrease in contrast ratio, U.S. Patent Application Publication No. 6,040,886 discloses a common line 16 and a common electrode 18 on the same plane with the same data metal layer as the pixel electrode 14, as shown in FIG. The formed liquid crystal display panel has been proposed.

The liquid crystal display panel shown in FIG. 4 is formed of a data metal layer such as chromium (Cr), molybdenum (Mo), titanium (Ti), etc. so that the pixel electrode 14 of the common electrode 18 has a thickness of about 1500 mW on the gate insulating film. do. That is, since the common electrode 18 and the pixel electrode 14 are formed of the data metal layer on the same plane, no step is generated between the common electrode 18 and the pixel electrode 14, and the level of the step between the gate insulating film 146 and the same It reduces and makes rubbing process uniform. Accordingly, the light leakage phenomenon is relatively reduced. In detail, when the at least one of the common electrode 18 and the pixel electrode 14 is formed as the gate metal layer, a step of about 2500 mV occurs and a relatively large amount of light leakage is generated as shown in FIG. 5A. When the common electrode 18 and the pixel electrode 14 are formed of the data metal layer, a step of about 1500 mV occurs, so that light leakage and luminance unevenness are reduced as shown in FIG. 5B.

However, when the common electrode 18 and the pixel electrode 14 are formed of data metal, the contrast ratio is slightly improved, but the aperture ratio of the liquid crystal display panel is lowered. Specifically, the data line 4 and the common electrode 18 formed on the gate insulating layer made of data metal should be spaced about 4 to 7 μm to prevent disconnection. This is to prevent the disconnection between the data line 4 to which the pixel signal is supplied and the common electrode 18 to which the reference voltage signal is supplied. The gap between the common electrode 18 and the pixel electrode 14 is reduced due to the holding interval between the common electrode 18 and the data line 4, thereby lowering the aperture ratio.

Accordingly, an object of the present invention is to provide a horizontal field application type liquid crystal display panel and a method of manufacturing the same that can improve the contrast ratio.

In order to achieve the above object, the liquid crystal display panel according to an embodiment of the present invention comprises a gate line formed on the substrate; A data line intersecting the gate line and the gate insulating layer so as to be insulated so as to determine a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A protective film formed on the gate insulating film to protect the thin film transistor; A common line formed in parallel with the gate line on the passivation layer of the pixel region; A common electrode formed on the passivation layer of the pixel region and connected to the common line; A horizontal portion parallel to the gate line and connected to the thin film transistor, and a finger portion protruding from the horizontal portion to form a horizontal electric field with the common electrode and parallel to the common electrode; A pixel electrode; At least one of the gate insulating layer and the passivation layer overlaps the finger and the common electrode of the pixel electrode, and overlaps the portion of the horizontal part while maintaining a predetermined distance from the gate line. And a light blocking layer formed to overlap all of the edges of the common line facing the pixel electrode while maintaining a predetermined interval therebetween.

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The light blocking layer is formed to completely overlap at least the finger portion and the common electrode of the pixel electrode.

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The light blocking layer is formed of the same material as at least one of the gate line and the data line.

At least one of the gate insulating film and the protective film is formed of any one of an organic insulating material.

The common electrode and the pixel electrode may be formed of a transparent conductive material including at least one of indium tin oxide, tin oxide, indium zinc oxide, and indium tin zinc oxide.

In order to achieve the above object, a method of manufacturing a liquid crystal display panel according to the present invention comprises the steps of forming a gate line on a substrate; Forming a gate insulating film on the substrate on which the gate line is formed; Forming a data line on the gate insulating layer to intersect the gate line; Forming a thin film transistor at an intersection of the gate line and the data line; Forming a light blocking layer of the same material as any one of a gate electrode and a drain electrode of the thin film transistor; Forming a protective film to cover the thin film transistor; Forming a common line, a common electrode and a pixel electrode on the passivation layer; The pixel electrode has a horizontal portion parallel to the gate line and connected to the thin film transistor, and a finger portion protruding from the horizontal portion to form a horizontal electric field with the common electrode and parallel to the common electrode; The light blocking layer overlaps a finger portion and a common electrode of the pixel electrode with at least one of the gate insulating layer and the passivation layer therebetween, and overlaps a portion of the horizontal portion while maintaining a predetermined distance from the gate line. The semiconductor device may be formed to overlap the edges of the common line facing the pixel electrode while maintaining a predetermined distance from the line and the gate line.

At least one of the gate insulating layer and the passivation layer may be formed of an organic insulating material.

The common electrode and the pixel electrode may be formed of a transparent conductive material.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 19.

FIG. 6 is a plan view illustrating a thin film transistor array substrate of a horizontal field type liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating a thin film transistor array substrate taken along line II-II ′ of FIG. 6. .

The thin film transistor array substrate of the horizontal field type liquid crystal display panel illustrated in FIGS. 6 and 7 includes a gate line 102 and a data line 104 formed on the lower substrate 145 and a thin film transistor formed at each intersection thereof. 106, a pixel electrode 114 and a common electrode 118 formed so as to form a horizontal electric field in the pixel region provided in the intersection structure, and a common line 116 connected to the common electrode 118.

The gate line 102 supplies a gate signal to the gate electrode 108 of the thin film transistor 106. The data line 104 supplies the pixel signal to the pixel electrode 114 through the drain electrode 112 of the thin film transistor 106. The gate line 102 and the data line 104 are formed in an intersecting structure to define the pixel region 105.

The common line 116 is formed in parallel with the gate line 102 with the pixel region 105 interposed therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 118.

The thin film transistor 106 keeps the pixel signal of the data line 104 charged and held in the pixel electrode 114 in response to the gate signal of the gate line 102. To this end, the thin film transistor 106 may include a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode connected to the pixel electrode 114. 112). In addition, the thin film transistor 106 further includes an active layer 148 that forms a channel between the source electrode 110 and the drain electrode 112 while overlapping the gate electrode 108 and the gate insulating layer 146 therebetween. . An ohmic contact layer 150 for ohmic contact with the data line 14, the source electrode 110, and the drain electrode 112 is further formed on the active layer 148.

The pixel electrode 114 is formed of a transparent conductive material so as to overlap the light blocking layer 109 with the gate insulating film 146 and the protective film 152 therebetween on the protective film 152 which is an inorganic insulating material. In addition, the pixel electrode 114 is connected to the drain electrode 112 of the thin film transistor 106 through the contact hole 113 penetrating through the passivation layer 152 and is formed in the pixel region 105. In particular, the pixel electrode 114 includes a first horizontal portion 114A connected to the drain electrode 112 and formed in parallel with the adjacent gate line 102, and a finger portion 114C formed in parallel with the common electrode 118. Equipped.                     

The common electrode 118 is formed of a transparent conductive material so as to overlap the light blocking layer 109 with the gate insulating layer 146 and the protective layer 152 therebetween on the passivation layer 152, which is an inorganic insulating material, and the common line 116. Are connected to and formed in the pixel region 105. In particular, the common electrode 118 is formed to be parallel to the finger portion 114C of the pixel electrode 114 in the pixel region 105.

As such, the common electrode 118 and the pixel electrode 114 may be formed of a transparent conductive material on the passivation layer 152 with a predetermined gap therebetween, thereby preventing a step between the two electrodes. In addition, the common electrode 118 and the pixel electrode 114 may be formed of a transparent conductive material that is relatively thinner than the gate metal layer and the data metal layer, thereby reducing the passivation layer 152 and the step between them. Since the rubbing defect is not generated by the reduced step, the liquid crystal is uniformly aligned.

A horizontal electric field is formed between the pixel electrode 114 supplied with the pixel signal through the thin film transistor 106 and the common electrode 118 supplied with the reference voltage through the common line 116. In particular, a horizontal electric field is formed between the finger portion 114C of the pixel electrode 114 and the common electrode 118. The horizontal electric field causes liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region 105 is changed to implement an image.

The light blocking layer 109 is formed of the same material as the gate line 102 and the gate electrode 108 so as to overlap the common electrode 118 and the pixel electrode 114 with the gate insulating layer 146 and the passivation layer 152 therebetween. It is formed on the substrate 145. As shown in FIG. 6, the light blocking layer 109 is formed to completely overlap the finger portion 114c and the common electrode 118 of the pixel electrode, so that the edges of the finger portion 114c and the common electrode 118 of the pixel electrode are overlapped. This prevents light leakage from Alternatively, the light blocking layer 109 is formed to completely overlap the finger portion 114c and the common electrode 118 of the pixel electrode as shown in FIG. 8, and maintains the pixel electrode horizontal portion while maintaining a predetermined distance from the gate line 102. Overlapping a portion of the 114a and overlapping a portion of the common line 116 while maintaining a predetermined distance from the dataline 104 and the gateline 102. Accordingly, the edge of the finger portion 114c of the pixel electrode, the edge of the common electrode 118 parallel to the finger portion 114c of the pixel electrode, and the edge of the pixel electrode horizontal portion 114a facing the common electrode 118. The light leakage phenomenon at the edge of the common line 118 facing the finger portion 114c of the pixel electrode is prevented.

9A to 9E illustrate a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

After the gate metal layer is deposited on the lower substrate 145 through a deposition method such as sputtering, the gate metal layer is patterned by a photolithography process and an etching process, so that the gate electrode 108 and the gate line 102 are shown in FIG. 9A. The gate pattern including the light blocking film 109 is formed. Here, aluminum neodium (AlNd), aluminum (Al), or the like is used as the gate metal layer.

The inorganic insulating material is entirely deposited on the lower substrate 145 on which the gate pattern is formed by a deposition method such as PECVD to form a gate insulating layer 146 as shown in FIG. 9B. Here, as the material of the gate insulating film 146, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used.

The first and second semiconductor layers are deposited on the lower substrate 145 on which the gate insulating layer 146 is formed, and then patterned by photolithography and etching to include the active layer 148 and the ohmic contact layer 150. A semiconductor pattern is formed.

After the date metal is deposited on the gate insulating layer 146 on which the semiconductor pattern is formed, patterned by a photolithography process and an etching process, the data line 104, the source electrode 110, and the drain electrode ( A source / drain pattern comprising 112 is formed. Next, the active layer 148 is exposed by dry etching the ohmic contact layer 150 of the thin film transistor using the source and drain electrodes 110 and 112 as a mask. Here, chromium (Cr), molybdenum (Mo), titanium (Ti), or the like is used as the data metal material.

 As the inorganic insulating material is deposited on the lower substrate 145 on which the source / drain patterns are formed, the passivation layer 152 is formed as shown in FIG. 9D. Here, as the material of the protective film 152, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used. Thereafter, the protective layer 152 is patterned by a photolithography process and an etching process to form a contact hole 113. The contact hole 113 exposes the drain electrode 112 of the thin film transistor.

After the transparent conductive film is deposited on the lower substrate 145 on which the passivation layer 152 is formed by a deposition method such as sputtering, the transparent conductive film is patterned through a photolithography process and an etching process using a mask, thereby as shown in FIG. 9E. The electrode 114, the common line 106, and the common electrode 118 are formed. The pixel electrode 114 and the common electrode 118 are formed to overlap the light blocking layer 109 formed of the gate metal with the gate insulating layer 146 and the passivation layer 152 therebetween. Herein, materials of the transparent conductive film include indium tin oxide (hereinafter referred to as "ITO"), tin oxide (hereinafter referred to as "TO"), and indium zinc oxide (hereinafter referred to as "IZO"). Or Indium Tin Zinc Oxide (hereinafter referred to as "ITZO").

10 is a cross-sectional view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

In the thin film transistor array substrate illustrated in FIG. 10, at least one of the gate insulating layer 146 and the passivation layer 252 which are flat as compared to the thin film transistor array substrate illustrated in FIGS. 6 and 7 is formed of an organic insulating material. Since the same components have the same reference numerals for the same components as in Figs. 6 and 7 and detailed description thereof will be omitted.

The pixel electrode 114 is connected to the drain electrode 112 of the thin film transistor 106 through a contact hole 113 penetrating through the passivation layer 252 and is formed in the pixel region 105. In particular, the pixel electrode 114 includes a first horizontal portion 114A connected to the drain electrode 112 and formed in parallel with the adjacent gate line 102, and a finger portion 114C formed in parallel with the common electrode 118. Equipped. The finger part 114c of the pixel electrode is formed of a transparent conductive material so as to overlap the light blocking layer 109 with the gate insulating film 146 and the protective film 252 interposed on the flat protective film 252.                     

The common electrode 118 is connected to the common line 116 and is formed to be parallel to the finger portion 114C of the pixel electrode 114 in the pixel region 105. The common electrode 118 is formed of a transparent conductive material so as to overlap the light blocking layer 109 with the gate insulating layer 146 and the protective layer 152 therebetween on the flat passivation layer 205 and connected to the common line 116. It is formed in the pixel region 105.

As such, since the common electrode 118 and the pixel electrode 114 are formed of a transparent conductive material on the same planar protective layer 252, a step between the two electrodes can be prevented and the rubbing process becomes uniform. Since the liquid crystal is uniformly aligned by the uniform rubbing process to prevent light leakage, the contrast ratio is improved.

The light blocking layer 109 is formed of the same material as the gate line 102 and the gate electrode 108 so as to overlap the common electrode 118 and the pixel electrode 114 with the gate insulating layer 146 and the passivation layer 252 interposed therebetween. It is formed on the substrate 145. As shown in FIG. 6, the light blocking layer 109 is formed so as to completely overlap the finger portion 114c and the common electrode 118 of the pixel electrode, and is formed between the finger portion 114c and the common electrode 118 of the pixel electrode. The light leakage phenomenon of the will be prevented. Alternatively, the light blocking layer 109 is formed to completely overlap the finger portion 114c and the common electrode 118 of the pixel electrode as shown in FIG. 8, and maintains the pixel electrode horizontal portion while maintaining a predetermined distance from the gate line 102. Overlapping a portion of the 114a and overlapping a portion of the common line 116 while maintaining a predetermined distance from the dataline 104 and the gateline 102. Accordingly, the edge of the finger portion 114c of the pixel electrode, the edge of the common electrode 118 parallel to the finger portion 114c of the pixel electrode, and the edge of the pixel electrode horizontal portion 114a facing the common electrode 118. The light leakage phenomenon at the edge of the common line 118 facing the finger portion 114c of the pixel electrode is prevented.

At least one of the gate insulating layer 146 and the passivation layer 252 is formed of an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB, and the lower substrate 145 having the passivation layer 252 formed thereon. Flattened. Accordingly, the step that may be generated by the light blocking layer 109 can be removed, thereby preventing light leakage.

11A and 11B illustrate a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

First, a protective film 252 is formed by coating an organic insulating material on the lower substrate 145 on which the light blocking layer 108 and the thin film transistor are formed by the spin coating method by the manufacturing method illustrated in FIGS. 9A to 9C. The protective film 252 is patterned by a photolithography process and an etching process to form a contact hole 113 as shown in FIG. 11A. The contact hole 113 exposes the drain electrode 112 of the thin film transistor. Here, as the organic insulating material, an acrylic organic compound having a low dielectric constant, BCB, PFCB, or the like is used.

The transparent conductive film is deposited on the lower substrate 145 on which the protective film 252 is formed by a deposition method such as sputtering. Thereafter, the transparent conductive film is patterned through a photolithography process and an etching process to form the pixel electrode 114, the common line 106, and the common electrode 118 as illustrated in FIG. 11B. The pixel electrode 114 is connected to the drain electrode 112 through the contact hole 113. The pixel electrode 114 and the common electrode 118 are formed to overlap the light blocking layer 109 formed of the gate metal with the gate insulating layer 146 and the protective layer 252 interposed on the passivation layer 252 formed flat. Here, ITO, TO, IZO, ITZO, etc. are used as a material of a transparent conductive film.

12 is a plan view illustrating a thin film transistor array substrate according to a third exemplary embodiment of the present invention, and FIG. 13 is a cross-sectional view illustrating a thin film transistor array group taken along the line “III-III ′” in FIG. 12.

12 and 13 have the same components except that the light blocking layer 209 is formed of data metal as compared to the thin film transistor array substrate shown in FIGS. 6 and 7. The same components as those of 6 and 7 will be denoted by the same reference numerals and detailed description thereof will be omitted.

The common electrode 118 and the pixel electrode 114 are formed of a transparent conductive material at predetermined intervals on the passivation layer 152, thereby preventing a step between the two electrodes. In addition, the common electrode 118 and the pixel electrode 114 are formed of a transparent conductive material that is relatively thinner than the gate metal layer and the data metal layer, thereby reducing the passivation layer 152 and the step between them. Due to the reduced step, the rubbing process becomes uniform and the liquid crystal is uniformly aligned.

The light blocking layer 209 overlaps the common electrode 118 and the pixel electrode 114 with the passivation layer 152 interposed between the data metal layers chromium (Cr), molybdenum (Mo), titanium (Ti), and the like. The light blocking film is a data metal that is relatively thinner than the gate metal and is formed to have a thickness of about 1500 mW. Accordingly, the step difference between the gate insulating layer 146 and the light blocking layer 209 is relatively reduced, thereby reducing light leakage.                     

As illustrated in FIG. 12, the light blocking layer 109 is formed to completely overlap the finger portion 114c and the common electrode 118 of the pixel electrode, so that the finger portion 114c and the common electrode of the pixel electrode when the black is implemented in the liquid crystal panel. Light leakage between 118 is prevented. Alternatively, the light blocking layer 109 is formed to completely overlap the finger portion 114c and the common electrode 118 of the pixel electrode as shown in FIG. 14, and maintains the pixel electrode horizontal portion while maintaining a predetermined distance from the gate line 102. Overlapping a portion of the 114a and overlapping a portion of the common line 116 while maintaining a predetermined distance from the dataline 104 and the gateline 102. Accordingly, the edge of the finger portion 114c of the pixel electrode, the edge of the common electrode 118 parallel to the finger portion 114c of the pixel electrode, and the edge of the pixel electrode horizontal portion 114a facing the common electrode 118. The light leakage phenomenon at the edge of the common line 118 facing the finger portion 114c of the pixel electrode is prevented.

15A to 15E are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 13.

First, the gate metal layer is deposited on the lower substrate 145 through a deposition method such as sputtering, and then the gate metal layer is patterned by a photolithography process and an etching process, so that the gate electrode 108 and the gate line (as shown in FIG. 15A). A gate pattern comprising 102 is formed. Here, aluminum neodium (AlNd), aluminum (Al), or the like is used as the gate metal layer.

An inorganic insulating material is entirely deposited on the lower substrate 145 on which the gate pattern is formed through a deposition method such as PECVD to form a gate insulating layer 146 as shown in FIG. 15B. Here, as the material of the gate insulating film 146, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used.

The first and second semiconductor layers are deposited on the lower substrate 145 on which the gate insulating layer 146 is formed, and then patterned by photolithography and etching to include the active layer 148 and the ohmic contact layer 150. A semiconductor pattern is formed.

As the data metal layer is deposited on the lower substrate 145 on which the semiconductor pattern is formed, and the data metal layer is patterned by a photolithography process and an etching process, as illustrated in FIG. 15C, the data line 104, the source electrode 110, and the drain electrode are formed. A source / drain pattern including a light blocking layer 209 is formed. Thereafter, the ohmic contact layer 150 of the thin film transistor is etched by a dry etching process using the source electrode 110 and the drain electrode 112 as a mask to expose the active layer 148 of the channel portion. Here, chromium (Cr), molybdenum (Mo), titanium (Ti), or the like is used as the data metal material.

 An inorganic insulating material is entirely deposited on the lower substrate 145 on which the source / drain patterns are formed, thereby forming the passivation layer 152 as illustrated in FIG. 15D. Here, as the material of the protective film 152, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used. Thereafter, the protective layer 152 is patterned by a photolithography process and an etching process to form a contact hole 113. The contact hole 113 exposes the drain electrode 112.

After the transparent conductive film is deposited on the lower substrate 145 on which the passivation layer 152 having the contact hole 113 is formed by sputtering or the like, the transparent conductive film is patterned through a photolithography process and an etching process, as shown in FIG. 15E. As described above, the pixel electrode 114, the common line 106, and the common electrode 118 are formed. The pixel electrode 114 is connected to the drain electrode 112 through the contact hole 113, and the common electrode 118 is formed in the pixel area in parallel with the finger portion 14C of the pixel electrode. The pixel electrode 114 and the common electrode 118 are formed to overlap the light blocking layer 209 formed of the data metal with the passivation layer 152 therebetween. Here, ITO, TO, ITZO, etc. are used as a material of a transparent conductive film.

16 is a cross-sectional view illustrating a thin film transistor array substrate according to a fourth exemplary embodiment of the present invention.

The thin film transistor array substrate shown in FIG. 16 has the same components except that the light shielding film 209 is formed of data metal on the flat protective film 252 as compared to the thin film transistor array substrate shown in FIGS. 6 and 7. Since the same components as in FIGS. 6 and 7 are given the same reference numerals, detailed description thereof will be omitted.

The pixel electrode 114 is connected to the drain electrode 112 of the thin film transistor 106 through a contact hole 113 penetrating through the passivation layer 252 and is formed in the pixel region 105. In particular, the pixel electrode 114 includes a horizontal portion 114A connected to the drain electrode 112 and formed in parallel with the adjacent gate line 102, and a finger portion 114C formed in parallel with the common electrode 118. . The finger part 114c of the pixel electrode is formed of a transparent conductive material so as to overlap the light blocking layer 209 with the gate insulating film 146 and the protective film 252 therebetween on the protective film 252 which is an organic insulating material.                     

The common electrode 118 is connected to the common line 116 and is formed to be parallel to the finger portion 114C of the pixel electrode 114 in the pixel region 105. The common electrode 118 is formed of a transparent conductive material to overlap the light blocking layer 209 with the gate insulating layer 146 and the protective layer 252 interposed on the passivation layer 205, which is an inorganic insulating material, and the common line 116. Is formed in the pixel region 105.

As such, the common electrode 118 and the pixel electrode 114 are formed of a transparent conductive material on the passivation layer 252, thereby preventing a step between the two electrodes, thereby making the rubbing process uniform. Since the liquid crystal is uniformly aligned by the uniform rubbing process to prevent light leakage, the contrast ratio is improved.

The light blocking layer 209 is formed of the same material as the data line 104 and the drain electrode 112 so as to overlap the common electrode 118 and the pixel electrode 114 with the gate insulating layer 146 and the passivation layer 252 interposed therebetween. It is formed on the substrate 145.

The light blocking layer 209 is formed of a gate insulating film so as to overlap the common electrode 118 and the pixel electrode 114 with the passivation layer 252 interposed between the data metal layers chromium (Cr), molybdenum (Mo), and titanium (Ti). 146) to have a thickness of about 1500 mm 3. Since the light blocking layer 209 is formed of a data metal that is relatively thinner than that of the gate metal, light leakage may be reduced as the step difference between the gate insulating layer 146 and the light blocking layer 209 is relatively reduced.

As shown in FIG. 12, the light blocking layer 209 is formed to overlap completely with the finger portion 114c and the common electrode 118 of the pixel electrode, and thus, between the finger portion 114c and the common electrode 118 of the pixel electrode. This prevents light leakage from Alternatively, the light blocking layer 109 is formed to completely overlap the finger portion 114c and the common electrode 118 of the pixel electrode as shown in FIG. 14, and maintains the pixel electrode horizontal portion while maintaining a predetermined distance from the gate line 102. Overlapping a portion of the 114a and overlapping a portion of the common line 116 while maintaining a predetermined distance from the dataline 104 and the gateline 102. Accordingly, the edge of the finger portion 114c of the pixel electrode, the edge of the common electrode 118 parallel to the finger portion 114c of the pixel electrode, and the edge of the pixel electrode horizontal portion 114a facing the common electrode 118. The light leakage phenomenon at the edge of the common line 118 facing the finger portion 114c of the pixel electrode is prevented.

At least one of the gate insulating layer 146 and the passivation layer 252 is formed of an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB, and the lower substrate 145 having the passivation layer 252 formed thereon. Flattened. Accordingly, the step that may be generated by the light blocking layer 109 can be removed, thereby preventing light leakage.

17A and 17B are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 16.

First, the protective film 252 is formed on the gate insulating film by coating an organic insulating material on the lower substrate on which the light blocking layer 209 and the thin film transistor are formed by spin coating using the manufacturing method illustrated in FIGS. 17A to 17C. . Here, as the organic insulating material, an acrylic organic compound having a low dielectric constant, BCB, PFCB, or the like is used. Thereafter, the protective layer 252 is patterned by a photolithography process and an etching process to form a contact hole 113 as shown in FIG. 17A. The contact hole 113 exposes the drain electrode 112 of the thin film transistor.

The transparent conductive film is deposited on the lower substrate 145 on which the passivation layer 252 having the contact hole 113 is formed by a deposition method such as sputtering. Thereafter, the transparent conductive film is patterned through a photolithography process and an etching process to form the pixel electrode 114, the common line 106, and the common electrode 118 as shown in FIG. 17B. The pixel electrode 114 is connected to the drain electrode 112 through the contact hole 113. The pixel electrode 114 and the common electrode 118 are formed to overlap the light blocking layer 109 formed on the gate insulating film 146 with the protective film 252 formed flat. Here, ITO, TO, IZO, ITZO, etc. are used as a material of a transparent conductive film.

As described above, in the TFT array substrate according to the first to fourth embodiments of the present invention, the common electrode 118 and the pixel electrode 114 are formed of a transparent conductive material on the passivation layer 252 and the gate insulating layer 146. And the light blocking layer 209 with at least one of the passivation layers 252 therebetween. As a result, the step between the common electrode 118 and the pixel electrode 114 is eliminated, so that rubbing of the alignment layer is uniform. Due to the uniform alignment, as shown in FIG. 18, the liquid crystal 160 is uniformly aligned, thereby reducing light leakage and light leakage.

19A and 19B are diagrams for describing a light blocking effect by the light blocking layers 209 and the light transmittance in the white and black implementations according to the first to fourth embodiments of the present invention.

As shown in FIG. 19A, when the common electrode and the pixel electrode are formed of a transparent conductive material, light transmittance is increased by the common electrode 118 and the pixel electrode 114 when the liquid crystal panel is white. ) Increases, while the black luminance B also increases during black implementation, thereby lowering the overall contrast ratio. On the other hand, when the light blocking layer 209 is formed to overlap the common electrode 118 and the pixel electrode 114 formed of the transparent conductive material as shown in FIG. 19B, the light is blocked by the light blocking layer 209 when the LCD is black. Is blocked. As a result, the black luminance B is lowered and the overall contrast ratio is relatively improved.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention form the pixel electrode and the common electrode on a protective film which is coplanar with a transparent conductive material, and form a light blocking layer to overlap the pixel electrode and the common electrode. Accordingly, the level difference between the pixel electrode and the common electrode can be reduced, so that the liquid crystal is uniformly aligned, and the contrast ratio is improved by preventing the black luminance from increasing when the black is blocked by the light blocking layer.

In addition, the light blocking layer is formed of a data metal layer or at least one of a gate insulating film and a protective film formed to cover the light blocking layer is formed of an organic insulating material. Accordingly, light leakage caused by the step of the light blocking layer can be reduced, and the contrast ratio is improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A gate line formed on the substrate; A data line intersecting the gate line and the gate insulating layer so as to be insulated so as to determine a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A protective film formed on the gate insulating film to protect the thin film transistor; A common line formed in parallel with the gate line on the passivation layer of the pixel region; A common electrode formed on the passivation layer of the pixel region and connected to the common line; A horizontal portion parallel to the gate line and connected to the thin film transistor, and a finger portion protruding from the horizontal portion to form a horizontal electric field with the common electrode and parallel to the common electrode; A pixel electrode; At least one of the gate insulating layer and the passivation layer overlaps the finger and the common electrode of the pixel electrode, and overlaps the portion of the horizontal part while maintaining a predetermined distance from the gate line. And a light blocking layer formed to overlap all of the edges of the common line facing the pixel electrode while maintaining a predetermined interval therebetween. delete The method of claim 1, And the light blocking layer is formed so as to completely overlap at least the finger portion and the common electrode of the pixel electrode. delete The method of claim 1, And the light blocking layer is formed of the same material as at least one of the gate line and the data line. The method of claim 1, And at least one of the gate insulating film and the protective film is formed of any one of an organic insulating material. The method of claim 1, And the common electrode and the pixel electrode are formed of a transparent conductive material including at least one of indium tin oxide, tin oxide, indium zinc oxide, and indium tin zinc oxide. Forming a gate line on the substrate; Forming a gate insulating film on the substrate on which the gate line is formed; Forming a data line on the gate insulating layer to intersect the gate line; Forming a thin film transistor at an intersection of the gate line and the data line; Forming a light blocking layer of the same material as any one of a gate electrode and a drain electrode of the thin film transistor; Forming a protective film to cover the thin film transistor; Forming a common line, a common electrode and a pixel electrode on the passivation layer; The pixel electrode has a horizontal portion parallel to the gate line and connected to the thin film transistor, and a finger portion protruding from the horizontal portion to form a horizontal electric field with the common electrode and parallel to the common electrode; The light blocking layer overlaps a finger portion and a common electrode of the pixel electrode with at least one of the gate insulating layer and the passivation layer therebetween, and overlaps a portion of the horizontal portion while maintaining a predetermined distance from the gate line. A method for manufacturing a horizontal field application type liquid crystal display panel, wherein the liquid crystal display panel is formed to overlap all edges of the common line facing the pixel electrode while maintaining a predetermined distance from the line and the gate line. The method of claim 8, And at least one of the gate insulating layer and the passivation layer is formed of an organic insulating material. The method of claim 8, And wherein the common electrode and the pixel electrode are made of a transparent conductive material.

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