KR100969439B1 - Method for manufacturing a printed circuit board having a landless via - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed circuit board, and more particularly, to a method of manufacturing a printed circuit board having landless vias by forming a resist layer having open holes that match with the via holes using an electrodeposited photosensitive resist. It is about. According to the present invention, a resist layer having an open hole may be formed on a substrate on which a via hole is formed, and thereafter, in the resist layer patterning process, there is no need to form a pattern corresponding to the via land in connection with the open hole. An opening without vias can be formed by patterning an opening for forming a circuit layer including a pattern to be formed. Therefore, by removing the land larger than the diameter of the via to form a fine circuit pattern to connect with the via, it is possible to implement a high-density circuit pattern, thereby producing a printed circuit board having a small size and reduced number of layers .

Landless, Land, Via, Electrodeposition, Electrodeposition, Resist

Description

Method for manufacturing a printed circuit board having a landless via}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed circuit board, and more particularly, to a method of manufacturing a printed circuit board having landless vias by forming a resist layer having open holes that match with the via holes using an electrodeposited photosensitive resist. It is about.

Printed Circuit Board (PCB) is used for mounting and wiring parts of electronic devices. After attaching thin plates such as copper to one surface of phenol resin insulation board or epoxy resin insulation board, they are etched according to the wiring pattern of the circuit. It is made by drilling a hole for attaching and mounting the parts by constructing the required circuit (removing it by leaving only the circuit on the wire).

The printed circuit board includes a single-sided PCB in which wiring is formed only on one side of the insulating board, a double-sided PCB in which wiring is formed on both sides, and an MLB (Multi Layered Board) that is wired in multiple layers. In the past, single-sided PCBs were used because of simple components and simple circuit patterns. However, in recent years, due to increased complexity of circuits and increased demand for high density and miniaturized circuits, it is common to use double-sided PCBs or MLBs.

A multilayer printed circuit board is constructed by alternately stacking circuit layers and insulating layers. In this structure, in order to connect the internal circuit layer and the external circuit layer, a via is required through the insulating layer to electrically connect the internal circuit layer and the external circuit layer. When manufacturing a multilayer printed circuit board through a build-up process, a process of forming a via hole capable of conducting with an external circuit layer is essential in an insulating layer stacked on the completed inner circuit layer.

At this time, the land is essentially formed in the portion connected to the upper circuit through the via hole for stable electrical conduction between the layers. Lands are designed in consideration of machining errors for forming vias, errors in exposure equipment used in forming the upper layer circuits, and in-process deformation of the raw materials used. Since the variation between equipment, materials, and processes is inevitable, the design of land has been taken for granted in order to increase productivity and process yield when manufacturing a printed circuit board. However, as the electronic industry develops, highly integrated semiconductors are developed, and miniaturization and thinning of electronic components are accelerating, and miniaturization, thinning, and high density are required in printed circuit boards on which these electronic components are mounted. To this end, efforts have been made to refine the wiring of the printed circuit board and to narrow the gaps of the vias, but the densification of the printed circuit board is limited due to the presence of lands. In order to improve the interlayer matching of high density substrates, new fixed matching exposure facilities are being developed to improve the matching force of the laser equipment for forming vias or to form microcircuits, but the improvement of such equipment is time-consuming and fundamentally reduces land. It has the limitation that it cannot be completely removed.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a printed circuit board for removing a land of vias used for interlayer connection in order to further increase wiring density in a printed circuit board requiring high density wiring, particularly a package board on which a highly integrated semiconductor is mounted. .

1 shows a process of manufacturing a multilayer printed circuit board by a conventional method. First, as shown in FIG. 1A, when a double-sided substrate 1 manufactured in a conventional manner is provided, the insulating layer 2 is coated as shown in FIG. 1B, and the via hole 3 of the insulating layer 2 is formed. The via hole 3 is processed at the position to be formed using a laser. At this time, the laser can be used both CO2 laser, YAG laser. Next, as shown in Fig. 1C, an electroless chemical copper plating layer 4 is formed on the entire surface of the substrate, so that electroplating is possible. Then, as shown in FIG. 1D, the photosensitive film 5 is applied, exposed and developed for circuit formation on the electroless chemical copper plating layer 4 to pattern the photosensitive film 5 (FIG. 1E). Then, as shown in FIG. 1F, after forming the circuit 6 by electrolytic copper plating, the photosensitive film 5 is peeled off (FIG. 1G), and the exposed electroless chemical copper plating layer 4 is etched. By removing, an outer layer circuit having a fine pattern is completed (FIG. 1H).

At this time, in the patterning process of the photosensitive film 5, in consideration of the deviation of the laser processing the via hole 3 and the deviation during exposure, the land 7 to be stably electrolytic copper plating after the via hole 3 is processed. The photosensitive film should be patterned by determining the size of. That is, the size of the land 7 is determined according to the accuracy of the via hole processing and the matching force of the circuit formation. Typically, lands are designed to have an area of at least seven times the top area of the via holes 3, and lands 7 occupy a substantial portion of the board area, which impedes a high density of circuits.

The present invention was created to solve the problems of the prior art as described above, and it is possible to form a fine circuit pattern by removing the land of the via, and has a printed circuit having a landless via hole having a good connection with the circuit pattern for connecting the via. We propose a method of manufacturing a substrate.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a printed circuit board having landless vias, including: (A) processing a via hole in an insulating layer and a metal layer formed on the insulating layer; (B) forming a resist layer on the metal layer by an electrodeposition method, the resist layer having open holes that mate with the via holes; (C) patterning the resist layer to form an opening for forming a circuit layer; And (D) plating the openings and the via holes to form circuit layers and vias, and removing the remaining resist layer.

According to a preferred feature of the present invention, the method may further include forming an electroless plating layer on an inner wall of the via hole before the step (C).

In another preferred embodiment of the present invention, the method may further include forming an electroless plating layer on the inner wall and the opening of the via hole after the step (C).

In another preferred aspect of the present invention, the width of the opening connected to the opening is smaller than the diameter of the via.

As another preferable feature of the present invention, the resist layer is an electrodeposition photosensitive resist.

As another preferred feature of the invention, the step of processing the via hole, i) forming a via hole by CNC drilling; And ii) performing a desmear process to remove burrs generated by drilling.

In another preferred embodiment of the present invention, the step of processing the via hole, i) removing the metal layer of the portion where the via hole is to be formed; And ii) forming via holes by laser processing the insulating layer of the portion where the metal layer is removed.

As another preferable feature of the present invention, the metal layer is an electroless copper plating layer.

As another preferable feature of the present invention, the metal layer is a copper foil layer having a thickness of 1 μm to 3 μm.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

According to the present invention, there is no land of the via, so that the circuit pattern connecting to the via can be finely formed to increase the density of the circuit pattern, thereby producing a printed circuit board having a small size and a reduced number of layers.

In addition, according to the present invention, a resist layer having an open hole that matches the via hole of the substrate can be formed by using the characteristics of the electrodeposited photosensitive resist, thereby manufacturing a printed circuit board having landless vias in a simple manufacturing process. There is an advantage to this.

Hereinafter, exemplary embodiments of a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. Throughout the accompanying drawings, the same or corresponding components are referred to by the same reference numerals, and redundant descriptions are omitted. In this specification, the terms first, second, etc. are used to distinguish one component from another component, and the component is not limited by the terms.

2 to 9 are diagrams sequentially illustrating a process of manufacturing a double-sided substrate 100 (see FIG. 9) by a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention. In this embodiment, a method of manufacturing the double-sided substrate 100 by using a modified semi additive process (MSAP) is described and illustrated, but is not limited thereto, and is referred to as a semi additive process (SAP). It should be understood that it is also possible to manufacture the double-sided substrate 100.

First, as shown in FIG. 2, a substrate on which the first metal layer 120 is formed is provided on the first insulating layer 110. In the present embodiment, a double-sided copper clad laminate (CCL) having a thickness of 1 μm to 3 μm as the first metal layer 120 is laminated on the first insulating layer 110. In the case of using the semi-additive process (SAP), a substrate having an electroless plating layer formed on both surfaces of the first insulating layer 110 may be provided.

3, the first via hole 130 penetrating the first metal layer 120 and the first insulating layer 110 is formed. The first via hole 130 may be formed by CNC drilling, and the desmear process may be performed to remove burrs generated by drilling after the first via hole 130 is formed.

Next, as shown in FIG. 4, a first resist layer 140 having a first open hole 145 to match the first via hole 130 is formed on the first metal layer 120.

In the present embodiment, the first resist layer 140 is formed by an electro deposition method using an electro-depositable photo-resist. Electrodeposited photosensitive resists are generally distinguished from dry film type resists used for circuit formation of printed circuit boards and are liquid type resists consisting of a solution in which particles of charged resist are dispersed. Since the particles of the resist are charged, the substrate to be applied is placed in a container containing the electrodeposited photosensitive resist, and a voltage is applied to a portion to form a resist layer, whereby the resist is applied only to the portion where the voltage is applied.

By using the properties of the electrodeposited photosensitive resist, the substrate having the first via hole 130 formed therein is placed in a container containing the electrodeposited photosensitive resist, and the voltage is applied to the first metal layer 120 to match the first via hole 130. The first resist layer 140 having the first opening hole 145 may be formed. In FIG. 4, a portion of the first opening hole 145 is indicated by a dashed line for clarity.

Next, as shown in FIG. 5, the first resist layer 140 is patterned to form a first opening 165 for forming a first circuit layer. Electrodeposited photosensitive resist is a positive-type (negative-type) and negative type (negative-type) like a dry film type resist generally used, the negative type is used in this embodiment. Therefore, the part where the first circuit layer 160 is formed, that is, the part to be plated is masked, irradiated with light, cured, and then developed to pattern the first resist layer 140.

Here, the process of patterning the 1st resist layer 140 is briefly described. After contacting the photomask on which the pattern of the first circuit layer 160 is printed on the first resist layer 140, ultraviolet rays are irradiated. At this time, the unprinted portion of the photomask transmits ultraviolet rays to form a cured portion in the first resist layer 140 under the photomask, and the printed black portion of the photomask does not transmit ultraviolet rays and thus under the photomask. An uncured portion is formed in the first resist layer 140. Subsequently, after the photomask is removed, the development process is performed such that the cured portion of the first resist layer 140 remains to remove the uncured portion of the first resist layer 140 to form the first circuit layer 160. The first opening 165 is formed.

In this case, an organic solvent or an organic solvent mixture is used for developing the first resist layer 140. In general, developing solutions for electrodeposited photoresists include propylene glycol methyl ether acetate, γ-butyrolactone, acetone, cyclopentanone, diacetone alcohol, tetrahydrofufurfuryl alcohol, 1-methylpyrrolidinone, anisole and ethyl lac Tate can be used.

On the other hand, in the patterning process of the first resist layer 140 of the present embodiment, unlike the resist layer patterning according to the conventional method, it is not necessary to pattern the via hole 130. This is because the pattern of the first resist layer 140 for the via hole 130 corresponds to the first opening hole 145. Therefore, it is sufficient to form a first opening 165 connected to the first opening 145. The width of the first opening 165 connected to the first opening hole 145 is preferably smaller than the diameter of the first via hole 130. Accordingly, in the first via 170 and the first circuit layer 160 to be formed by the process described below, the first via 170 does not have a land larger than the via diameter. Features and advantages of the present invention to this will be described later.

6, the first seed layer 150 is formed on the inner walls of the first opening 165 and the first via hole 130 by performing electroless plating on the entire surface of the substrate.

In general, the electroless plating process includes a degreasing process, a soft etching process, a pre-catalyst process, a catalyst treatment process, an activator process, an electroless copper plating process, and an anti-oxidation process. The catalyst precipitation method including the process is used. Typically, palladium derivatives are used as catalysts for electroless plating of substrates.

In this embodiment, electroless plating is performed using palladium as a catalyst. In this case, roughness of about 3 μm to 5 μm is formed inside the first via hole 130, so that the palladium derivative is adsorbed, but the surface of the first resist layer 140 (electrodeposition photosensitive resist) is not formed at all. Therefore, the palladium derivative is not adsorbed, and the palladium derivative remaining on the surface of the first resist layer is removed in the washing step. Since the electroless plating layer cannot be formed in the portion where the palladium derivative is not adsorbed, the first circuit layer 160 having the inner wall of the first via hole 130 coated with the palladium derivative and the first resist layer 140 removed is formed. The first seed layer 150 is formed only on the surface of the dragon opening. That is, as shown in FIG. 6, the first seed layer 150 is not formed on the surface of the first resist layer 140.

Meanwhile, the process of forming the first seed layer 150 of the present application is a preliminary step for performing electroplating on the inner wall of the first via hole 130, and forming the first seed layer 150 on the inner wall of the first via hole 130. It aims to do it. Therefore, the process of forming the first seed layer 150 may be performed prior to the patterning process of the first resist layer 140. That is, after forming the first seed layer 150 on the inner wall of the first via hole 130, the first resist layer 140 may be patterned.

Thereafter, as illustrated in FIG. 7, electroplating is performed to form the first circuit layer 160 and the first via 170. Electrolytic copper plating is performed on the first opening 165 and the first via hole 130 by using the first metal layer 120 as a lead line. The thickness of the first circuit layer 160 is generally 10 μm to 15 μm, and the inner wall of the first via hole 130 is plated to the same thickness as the thickness of the first circuit layer 160. In this case, fill plating may be performed to fill the first via hole 130 with an electrolytic plating layer to more stably connect the circuit.

Next, as shown in FIG. 8, the remaining first resist layer 140 is removed, and as shown in FIG. 9, the exposed portion of the first metal layer 120 is removed by flash etching. 1 circuit layer 160 is completed. For example, an organic acid may be used to remove the first resist layer 140.

Referring to FIG. 9, it can be seen that the first via 170 has no land larger than the diameter of the first via 170 formed at the top and the bottom thereof. That is, when manufacturing a printed circuit board by the method according to the invention it is possible to implement a landless via without land.

An advantage of removing the land is briefly described with reference to FIG. 19 as follows. 19A is a plan view of a circuit in which the lands 7 of the conventional via hole 3 are formed, and FIG. 19B is a plan view of a landless circuit manufactured according to the present invention.

As shown in the drawing, in the printed circuit board manufactured by the conventional method, only one pattern may be formed between adjacent via holes 3 when the pitch between the via holes 3 is 240 μm. When the landless via 70 is formed according to the method described above, the circuit may be designed such that two patterns are formed between the vias 70 while reducing the pitch of the vias 70 in the same microcircuit. Therefore, it is possible to reduce the size and density of electronic devices, and to reduce the size of the printed circuit board and reduce the number of layers of the multilayer board, thereby lowering the manufacturing cost of the printed circuit board.

Hereinafter, a method of forming an additional outer layer on the double-sided substrate 100 formed by the above-described process as a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention. Here, description overlapping with the above-described process is omitted.

10 to 18 are diagrams sequentially showing a process of manufacturing an additional outer layer on the double-sided substrate 100 by a method for manufacturing a printed circuit board according to a preferred embodiment of the present invention.

First, as shown in FIG. 10, the second insulating layer 210 is stacked on the outer layer of the double-sided substrate 100, and the second metal layer 220 is formed on the first insulating layer 110. In this embodiment, the second circuit layer 260 (see FIG. 16) is formed by a modified semi-additive process (MSAP), and the second insulating layer 210 and the copper foil are laminated together. In the case of the semi-additive process (SAP), the second insulating layer 210 is laminated and the second metal layer 220 is formed by electroless plating.

After stacking the second insulating layer 210, as shown in FIG. 12, a second via hole 230 is formed at a position where vias of the second metal layer 220 and the second insulating layer 210 are to be formed. . In this case, as shown in FIG. 11, after performing the window forming process of removing the second metal layer 220 at the position where the via hole is to be formed, the second insulating layer 210 is formed by CO ₂ laser or YAG laser drilling. It is preferable to process the two via holes 230.

Next, as shown in FIG. 13, a second resist layer 240 having a second open hole 245 that matches the second via hole 230 is formed on the second metal layer 220. Since the second resist layer 240 is made of an electro-deposited photosensitive resist, and the forming method is the same as that of the first resist layer 140 and is very similar, detailed description thereof will be omitted.

Subsequently, as shown in FIG. 14, the second opening 265 for forming the second circuit layer 260 is patterned in the second resist layer 240, and as shown in FIG. 15, the second via hole 230. The second seed layer 250 is formed by electroless plating an inner wall of the ()) and an exposed portion of the second metal layer 220. As described above, the second seed layer 250 may be formed before the patterning of the second resist layer 240.

In this case, in patterning the second resist layer 240, it is not necessary to form a pattern for the second via hole 230, and the second opening 265 including a pattern connected to the second opening hole 245. It is enough to pattern it. Therefore, it is possible to form landless vias without an upper land as described above.

Next, as shown in FIG. 16, the second circuit layer 260 and the second via 270 are formed on the second seed layer 250 using the second metal layer 220 as a lead line. In this case, similar to the first via 170, the inner wall of the second via hole 230 may be formed by plating the same thickness as that of the second circuit layer 260, but here, fill plating may be performed to form the inner wall of the second via hole 230. The second via hole 230 is filled with an electrolytic plating layer to form a second via 270.

Thereafter, as shown in FIG. 17, the remaining second resist layer 240 is removed, and as shown in FIG. 18, the exposed portion of the second metal layer 220 is removed by flash etching. 260).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Therefore, such modifications or variations will have to belong to the claims of the present invention.

FIG. 1 is a diagram sequentially illustrating a process of manufacturing a printed circuit board having vias with a conventional land.

2 to 18 are views showing the manufacturing hole of the printed circuit board according to the preferred embodiment of the present invention in order.

FIG. 19A is a schematic plan view of the printed circuit board of FIG. 1H viewed from above, and FIG. 19A is a schematic plan view of the printed circuit board of FIG. 18 viewed from above.

<Description of Major Symbols in Drawing>

100 Double-sided board 110 First insulation layer

120 First metal layer 130 First via hole

140 First resist layer 145 First opening

150 first seed layer 160 first circuit layer

165 First Opening 170 First Via

210 Second Insulation Layer 220 Second Metal Layer

230 Second via hole 240 Second resist layer

245 Second opening hole 250 Second seed layer

260 Second circuit layer 265 Second opening

270 Second Via

Claims (9)

(A) processing via holes in the insulating layer and the metal layer formed on the insulating layer; (B) forming a resist layer having an open hole that matches the via hole only on the metal layer by an electric deposition method by applying a voltage to the metal layer; (C) patterning the resist layer to form an opening for forming a circuit layer; And (D) plating the openings and the via holes to form circuit layers and vias, and removing the remaining resist layer; Method of manufacturing a printed circuit board having a landless via comprising a. The method of claim 1, And forming an electroless plating layer on an inner wall of the via hole prior to the step (C). The method of claim 1, And forming an electroless plating layer on the inner wall and the opening of the via hole after the step (C). The method of claim 1, The width of the opening connected to the opening is a manufacturing method of a printed circuit board having a landless via smaller than the diameter of the via. The method of claim 1, And the resist layer has landless vias made of an electrodeposited photosensitive resist. The method of claim 1, The step of processing the via hole, Iii) forming via holes by CNC drilling; And Ii) performing a desmear process to remove burrs generated by drilling; Method of manufacturing a printed circuit board having a landless via comprising a. The method of claim 1, The step of processing the via hole, Iii) removing the metal layer of the portion where the via hole is to be formed; And Ii) forming via holes by laser processing the insulating layer of the portion where the metal layer is removed; Method of manufacturing a printed circuit board having a landless via comprising a. The method of claim 1, And the metal layer has a landless via that is an electroless copper plating layer. The method of claim 1, The metal layer is a manufacturing method of a printed circuit board having a landless via which is a copper foil layer having a thickness of 1㎛ 3㎛.

Images