KR100968411B1 - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a capacitor having a high capacitance in a limited area and having a stable structure. To this end, the present invention comprises the steps of forming an interlayer insulating film on a substrate on which a conductive active region is formed; Forming a storage node contact plug penetrating the interlayer insulating layer and connected to the conductive active region; Forming an insulating film for forming a capacitor to cover the storage node contact plug; Selectively removing the capacitor forming insulating layer to form a capacitor forming hole through which the storage node contact plug is exposed; Performing a recess process in which a portion of an upper portion of the exposed storage node contact plug is removed; Forming a storage node electrode with a conductive layer on a side of a recessed region of the upper portion of the storage node contact plug and inside the capacitor forming hole; Forming a dielectric thin film on the storage node electrode; And forming a plate electrode on the dielectric thin film as a conductive film.

Semiconductors, Capacitors, Metastable Polysilicon Films.

Description

METHODS FOR FABRICATING CAPACITOR IN SEMICONDUCTOR DEVICE}             

1A and 1D are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the prior art.

2A and 2H are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to a preferred embodiment of the present invention.

Figure 3 is a table showing the etching selectivity in the case of using the NH ₄ OH / H ₂ O mixture and HF / HNO ₃ mixture in the recess step to increase the storage surface area by the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

30: substrate

31: active area

32: interlayer insulating film

33: Contact Plug

34 etch stop film                 

35: insulating film for capacitor formation

36: capacitor formation hole

37: recessed area

38 ': storage electrode

39: Hemispherical Silicon Grain

40: dielectric thin film

41: plate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor having increased capacitance by increasing the surface area of a storage electrode.

Recently, with the development of semiconductor manufacturing technology, the demand for memory devices has increased so that high capacitance is required in a small area. The capacitance of the capacitor is proportional to the dielectric constant and area of the dielectric and inversely proportional to the thickness.

As devices become more integrated, a method of maximizing capacitor capacity has been proposed, such as using an insulator having a high dielectric constant, increasing the area of the electrode, or reducing the thickness of the dielectric.                         

Among these, efforts to increase the capacitor area are as follows. First, the capacitor is designed in three dimensions to secure an electrode film with a larger surface area. Three-dimensional capacitors include cylinders, concaves, and the like.

Second, it is an attempt to secure the amount of electricity storage by increasing the effective area by giving the irregularities on the surface of the charge storage. A metastable polysilicon (Metatable PolySilicon), that is, hemispherical silicon grain (Grain) is deposited on the electrode surface to reduce the surface area of the electrode How to increase.

Hemispherical Shaped Grains (HSG) refers to the deposition of polysilicon surfaces in a hemispherical shape when silicon is deposited around 580 ° C in a low pressure chemical vapor deposition (LPCVD) system. The temperature of 580 ° C corresponds to a transition zone in which the structure of the deposited silicon changes from amorphous to polycrystalline, which can be adjusted by temperature and pressure, the flow rate of SiH ₄ used as a seed material, and the like.

When the surface of the electrode is made of irregularities to increase the surface area, the capacitance can be increased by about 2 times compared to the planarized electrode structure.

However, as semiconductor devices become more integrated, capacitors are manufactured in a more limited area, and thus, it is difficult to secure sufficient capacitance even on the surface of an electrode on which hemispherical silicon grains are formed.

1A to 1D are process cross-sectional views showing a capacitor manufacturing method of a semiconductor device according to the prior art, in particular, a three-dimensional concave type capacitor manufacturing method.

As shown in FIG. 1A, in the capacitor manufacturing method, an interlayer insulating film 12 is formed on a semiconductor substrate 10 on which an active region 11 is formed, and then penetrates the interlayer insulating film 12 to form a semiconductor substrate 10. A contact hole is formed to be connected to the active region 11. Subsequently, the contact hole is filled with a conductive silicon film to form a storage node contact plug 13.

Subsequently, an etch stop layer 14 is formed, and a capacitor forming insulating film 15 is formed thereon to a height at which the capacitor is to be formed, and then the capacitor forming insulating film 15 is selectively formed so that the contact plug 13 is exposed. The capacitor forming hole 16 is formed to be removed. At this time, the capacitor forming insulating film 15 is etched first, and in this process, the etch stop film 14 serves as a barrier to stop the etching process. Thereafter, the etch stop layer 14 is selectively removed to expose the contact plug 13.

Subsequently, as shown in FIG. 1B, the storage electrode 17 is formed in the capacitor forming hole 16 using the conductive silicon film.

Subsequently, as shown in FIG. 1C, an embossed hemispherical silicon grain 18 having an uneven structure is formed on the storage electrode 17 of the capacitor.

Subsequently, as shown in FIG. 1D, a dielectric thin film 18 is formed on the storage electrode 17. Subsequently, a plate electrode 20 is formed of a conductive film on the dielectric thin film 19.                         

As described above, as semiconductor devices become more and more integrated, there is a limit to forming only on the storage electrodes of the capacitors in order to secure a constant capacitance in a limited area. Therefore, in order to secure a constant capacitance, the shape of the storage electrode is formed in three dimensions, and hemispherical silicon grains are formed on the surface of the storage electrode.

However, as described above, it is increasingly difficult to secure a desired capacitance in an increasingly high-density memory device. If the manufactured capacitor does not have a desired amount of capacitance, the semiconductor device such as a memory degrades the refresh characteristics and decreases the sensing margin of the data, thereby directly reducing the wafer yield.

The present invention has been proposed to achieve the above object, and an object of the present invention is to provide a method of manufacturing a capacitor having a stable structure while having a high capacitance in a limited area.

The present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a substrate on which a conductive active region is formed; Forming a storage node contact plug penetrating the interlayer insulating layer and connected to the conductive active region; Forming an insulating film for forming a capacitor so as to cover the storage node contact plug; Selectively removing the capacitor forming insulating layer to form a capacitor forming hole through which the storage node contact plug is exposed; Performing a recess process in which a portion of an upper portion of the exposed storage node contact plug is removed; Forming a storage node electrode with a conductive layer on a side of a recessed region of the upper portion of the storage node contact plug and inside the capacitor forming hole; Forming a dielectric thin film on the storage node electrode; And forming a plate electrode on the dielectric thin film as a conductive film.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

2A to 2H are cross-sectional views illustrating a capacitor manufacturing process according to a preferred embodiment of the present invention.

As shown in FIG. 2A, the capacitor manufacturing method according to the present embodiment first forms an interlayer insulating film 32 on the semiconductor substrate 30 on which the active region 31 is formed, and then penetrates the interlayer insulating film 32. A contact hole connected to the active region 31 of the semiconductor substrate 30 is formed. Subsequently, the contact hole is filled with a conductive polysilicon layer to form a storage node contact plug 33. The interlayer insulating layer 32 may include undoped-silicate glass (USG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), high density plasma (HDP) oxide, spin on glass (SOG) film, and TEOS. (Tetra Ethyl Ortho Silicate) film, or an oxide film using HDP (high densigy plasma), or a thermal oxide film (Thermal Oxide). have.

Subsequently, an etch stop layer 34 is formed of an insulating layer of a nitride film series, and an insulating layer 35 for forming a capacitor is formed on the upper portion thereof so that the storage electrode of the capacitor is formed. Here, the capacitor forming insulating film 34 may be formed of Undoped-Silicate Glass (USG), Phospho-Silicate Glass (PSG), Boro-Phospho-Silicate Glass (BPSG), High Density Plasma (HDP) oxide film, and Spin On Glass (SOG). Film, TEOS (Tetra Ethyl Ortho Silicate) film or HDP (high densigy plasma) oxide film, etc., or thermal oxide film (Thermal Oxide) is formed by oxidizing silicon substrate at high temperature between 600 ~ 1,100 ℃ in furnace It can be formed using.

In addition, the capacitor forming insulating film 35 may be formed by forming a single chemical vapor deposition (CVD) oxide film or by stacking a plurality of CVD oxide films. When the multiple CVD oxide film is stacked with the capacitor forming insulating film 35, the wet etching rate is faster than that of the upper film. This is for stably forming the lower region when forming the capacitor forming hole.

In addition, the height of the capacitor formation insulating film 35 and the etch stop film 34 together is formed to a height of 6000 ~ 2000Å. In addition, the height of the etch stop film 34 may be formed in the range of 100 ~ 2000Å.                     

Subsequently, as shown in FIG. 2B, the capacitor forming insulating layer 35 formed on the storage note contact plug 33 is selectively removed to form the capacitor forming hole 36. Herein, the removing process may use a wet etching process or a dry etching process. At this time, the nitride film-based insulating film used as the etch stop film 34 serves as an etch stop film in the etching process for forming the capacitor forming hole.

Next, as shown in FIG. 2C, the etch stop layer 34 at the bottom of the capacitor forming hole 36 is removed.

Next, as shown in FIG. 2D, a recess process is performed to remove a portion 37 of the storage node contact plug 37.

At this time, the recess process may be performed by both a wet etching process and a dry etching process. First, in the case of the dry etching process, the etching selectivity between the oxide film used as the insulating film 32 and the polysilicon film used as the storage node contact plug 37 is sufficiently applied in the case of dry etching. .

Second, even when the wet etching method is applied, an etchant having a sufficient wet etching selectivity between the oxide film used as the insulating film 32 and the polysilicon film used as the storage node contact plug 37 is used.

Figure 3 is a table showing the etching selectivity in the case of using the NH ₄ OH / H ₂ O mixture and HF / HNO ₃ mixture in the recess step to increase the storage surface area according to the present invention. As shown in FIG. 3, the mixed solution of NH ₄ OH / H ₂ O or the mixed HF / HNO ₃ solution is a thermal oxidized film or a CVD oxide film, and the etching selectivity is sufficiently large to be used as the storage node cone plug 33 by wet etching. The polysilicon film can be effectively recessed.

Referring to the bar shown in Figure 3, when the wet etching process using a mixed solution of NH ₄ OH / H ₂ O, the ratio of NH ₄ OH and H ₂ O ratio of 1.2 ~ 1:20 and temperature When polysilicon was etched at 90Å / min under the experimental conditions of 65 ℃, thermal oxide film (SiO ₂ ) was 0.2Å, CVD oxide film (HDP SiO ₂ ): 0.3 ~ 1 막, nitride film (Si ₃ N ₄ ): 0.3 ~ 1Å It can be seen that the degree of etching proceeds. Therefore, the etching selectivity of polysilicon and various insulating films (thermal oxide film, CVD oxide film, nitride film) is about 450: 1, 90 to 300: 1, and 90 to 300: 1. Therefore, the above-described recess process can be performed without any problem.

Also, in the case of the HF / HNO ₃ mixed liquid, the polysilicon film used as the storage node contact plug 33 made of polysilicon is maintained by maintaining a high etching selectivity between the polysilicon and various insulating films as shown in FIG. Can be used to set.

In case of using NH ₄ OH / H ₂ O mixed solution, the mixing ratio is 10: 1 ~ 1: 500 (volume ratio), and when HF / HNO ₃ mixed solution is used, the mixing ratio is 20: 1 ~ 1: 100 We assume (volume ratio).

In addition, when using the mixed solution of NH ₄ OH / H ₂ O or the HF / HNO ₃ mixed solution in the above-mentioned recess step, the dipping time of the temperature of the wet bath is reduced to 4 to 100 ° C. Advance in the range of 5 to 3600 seconds. At this time, the recess process proceeds to be recessed in the range of 50 ~ 5000Å.

In addition, when the above-described recess process is performed by the wet etching method, the cleaning process after removing the nitride stop film 34 and the process of recessing the polysilicon film used as the storage node cone plug 33 and The pre-cleaning process for depositing the polysilicon film for the storage electrode formed in the subsequent process can be carried out by combining one recipe (process conditions) on the cleaning equipment, thereby reducing the process step.

Subsequently, as illustrated in FIG. 2E, the conductive electrode 38 for the storage electrode is formed using the conductive polysilicon film along the recess 37 and the capacitor forming hole 36 pattern. In this case, the conductive film for the storage electrode uses a doped single film or a film in which the doped film and the undoped polysilicon film are sequentially deposited, and the total thickness is formed to a thickness of 100 to 1000 Å.

Subsequently, as illustrated in FIG. 2F, the storage electrode conductive layer 38 is left in the region 37 and the capacitor forming hole 36 where the recess process is performed, and the remaining portions are removed to form the storage electrode 38 ′. . This swarm removal process uses an etch back process or a chemical mechanical polishing process (CMP) method.

Here, the storage electrode 38 ′ is formed not only on the sidewall of the capacitor forming hole but also to the region 37 in which the storage node contact plug 38 is recessed, thereby increasing the surface area of the storage electrode 38 ′. In addition, since the surface area of the storage electrode 38 ′ is increased but the height of the capacitor forming hole 36 is the same as before, there is no additional process burden such as wet etching or dry etching to form the capacitor forming hole.                     

2G, hemispherical silicon grains 39 are then formed on the surface of the storage electrode 38 '. At this time, the process of growing the hemispherical silicon grains is grown for 50 to 70 seconds at a temperature of 400 ~ 800 ℃ range.

Subsequently, as shown in FIG. 2H, a dielectric thin film 40 is formed on the surface of the storage electrode 38 ′, and a plate electrode 41 is formed of a conductive material thereon.

Here, the dielectric thin film 40 may be formed by applying a metal organic chemical vapor deposition method or an atomic layer deposition method, such as SIO ₂ , SiO ₂ / Si ₃ N ₄ mixed film, TaON, Ta ₂ O ₅ , TiO ₂ , Ta-Ti-O mixed film, Al Form one of ₂ O ₃ , HfO ₂ , HfO ₂ / Al ₂ O ₃ , SrTiO ₃ , (Ba, Sr) TiO _3, or (Pb, Sr) TiO ₃ to form a range of 50 to 500 kV. In addition, the plate electrode 41 is formed in the range of 500 to 3000 mW using a conductive film such as TiN, Ru, polysilicon, or the like using a sputtering burr, a CVD method, or an atomic layer deposition method.

As described above, by increasing the surface area of the storage electrode by recessing the straw node contact plug 33 as in the present invention, it is possible to prevent a failure factor of the memory device such as deterioration of the refresh characteristics and decrease of the sensing margin, thereby directly increasing the yield. Can be improved.

In addition, the method of increasing the surface area by recessing the straw node contact plug as described above is a dry etching solution or a wet etching solution having a large etching selectivity with the surrounding oxide film even when the storage node is not polysilicon. Applicable by using                     

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

By manufacturing the capacitor according to the present invention, it is possible to produce a capacitor which is structurally stable with high capacitance in a limited area without any additional investment.

Claims (9)

Forming an interlayer insulating film on the substrate on which the conductive active region is formed; Forming a storage node contact plug penetrating the interlayer insulating layer and connected to the conductive active region; Forming an insulating film for forming a capacitor to cover the storage node contact plug; Selectively removing the capacitor forming insulating layer to form a capacitor forming hole through which the storage node contact plug is exposed; Performing a recess process in which a portion of an upper portion of the exposed storage node contact plug is removed; Forming a storage node electrode with a conductive layer on a side of a recessed region of the upper portion of the storage node contact plug and inside the capacitor forming hole; Forming a dielectric thin film on the storage node electrode; And Forming a plate electrode on the dielectric thin film using a conductive film Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1 The storage node contact plug is formed of a conductive polysilicon film, the capacitor manufacturing method of the semiconductor device. The method of claim 2 The recess process of removing a portion of the upper end of the storage node contact plug is And etching the polysilicon used as the storage node contact plug and the interlayer insulating layer to a etch selectivity ratio of 1:40 or more, and performing a dry etching process. The method of claim 2, The recess process in which a predetermined portion of the upper end of the storage node contact plug is removed is performed by a wet etching process using a NH ₄ OH / H ₂ O mixed solution or a HF / HNO ₃ mixed solution. . The method of claim 4, wherein In the case of using the NH ₄ OH / H ₂ O mixture in the recess step, the method of manufacturing a capacitor of a semiconductor device, characterized in that the mixing ratio of NH ₄ OH and H ₂ O proceeds in the range of 10: 1 ~ 1: 500 . The method of claim 4, wherein In the case of using the HF / HNO ₃ mixture in the recess step, the method of manufacturing a capacitor of a semiconductor device, characterized in that the mixture ratio of HF and HNO ₃ to 20: 1 ~ 1: 100 (volume ratio). The method according to claim 5 or 6, The interlayer insulating film A method for manufacturing a capacitor of a semiconductor device, characterized in that one selected from thermally oxidized film, CVD oxide film or nitride film. The method of claim 4 The recess process is a capacitor manufacturing method of a semiconductor device, characterized in that the process of the wet bath temperature in the range of 4 ~ 100 ℃, the dipping time in the range of 5 ~ 3600 seconds. The method of claim 1, Before forming the dielectric thin film, And forming hemispherical silicon grains on the surface of the storage electrode to increase the surface area of the storage electrode.

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