KR100954630B1 - Semiconductor integrated circuit - Google Patents

Abstract

Bypass capacitors having a predetermined capacitance on the power supply / ground lines adjacent to the driver circuits in the chip reduce the adverse effects of transients during switching. The capacitance of the bypass capacitor is set larger than the parasitic capacitance of the driver circuit to prevent the characteristic impedance of the power / ground line from being higher than the characteristic impedance of the internal wiring.

Bypass Capacitor, Driver Circuit

Description

Semiconductor Integrated Circuits {SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to circuit structures for use in electronic circuits such as logic circuits and memories operating at high speeds, and more particularly to circuit structures of semiconductor integrated circuits.

Generally, semiconductor integrated circuits include memory or logic circuits formed within semiconductor chips. Recently, the demand for digital semiconductor integrated circuits that operate at high speed in the GHz band has increased according to the demand for digitization. Digital semiconductor integrated circuits usually include a number of transistors. In this case, each transistor is connected to a power supply for supplying electrical energy and a ground for discharging the supplied energy to form a transistor circuit.

The transistor circuit operates as an on-off switch or gate circuit while no signal is transmitted from the transistor even if the power supply does not supply electrical energy even when the transistor is in the on state.

Considering the transistor gate circuit here, the gate circuit is immediately turned on. If the on-resistance is small, a phenomenon occurs in which the wiring cannot supply electric charge when the connected power supply tries to supply electric energy (charge). The reason why the wiring cannot supply electrical energy will be described later in detail. Assuming that the power / ground wiring is a transmission line and the characteristic impedance is 50 kHz, the wiring cannot supply charge if the on-resistance of the transistor gate circuit is about 15 kHz, which is lower than the characteristic impedance. Fortunately, in many cases the characteristic impedance of the signal line is greater than 50 kHz. Therefore, the problem of not being able to supply charge is avoided. However, it is necessary to cope with the instantaneous change for supplying charge to the transistor parasitic capacitor. The pipes to supply the charge must be made thick. In other words, there is a need for a configuration and method for lowering the characteristic impedance of power / ground. Accordingly, the inventor of the present invention discloses a configuration and method for lowering the characteristic impedance of power supply / ground in Japanese Patent Laid-Open No. 2000-174505 (hereinafter referred to as Reference 1).

In addition, the faster the switching operation of the transistor circuit, the inductance that resists a sudden increase in current becomes insignificant along with the above-mentioned problems. Even if the characteristic impedance of the power supply / ground is lower than the characteristic impedance of the signal line, it is impossible to keep up with the rapid opening and parasitic charge of the transistor gate circuit due to the parasitic inductance of the power supply / ground wiring. Therefore, there is a need for a configuration and method for lowering parasitic inductance.

In addition, the signal energy (charge amount) that determines reception is insufficient until charging of all capacitors of the receiving transistor gate is completed by the current controlled by the on-resistance. This causes an operational delay of the receiving transistor itself. As a result, the current of the power source continues to flow during this time.

As such, the state in which flexible switching control in the transistor gate circuit becomes impossible becomes prominent in the digital circuit in the GHz band due to the rate-controlling caused by the power supply / ground supply capability.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit and a circuit structure capable of sufficiently guaranteeing the charge supply capability of the power source / ground so that the characteristics of the transistor gate circuit are not suppressed even when fast operation is required.

A circuit structure according to the first aspect of the present invention is a circuit structure including a driver circuit and a power / ground line structure in a chip, wherein the power / ground line has a predetermined capacitance as a power-ground connection circuit to be adjacent to the driver circuit. It is characterized in that it is connected to a capacitor having a.

In the above configuration, the predetermined capacitance is larger than the parasitic capacitance of the driver circuit, or the capacitance element having the predetermined capacitance is connected to the driver circuit so as to be complementary to the capacitance element of the driver circuit in operation. It is done.

The predetermined capacitance is at least equal to or greater than the accumulated charge of the driver circuit or the total parasitic capacitance of the circuit structure.

Also, preferably, the capacitor includes at least one of a pn diffusion capacitor and an electrode capacitor.

A circuit structure according to another aspect of the present invention further includes a configuration in which a unit circuit including a transistor is connected to the power / ground line in a chip, wherein the characteristic impedance of the power / ground line is configured to transmit a signal through the driver circuit. It is characterized in that it is lower than the characteristic impedance of the signal transmission line for transmission.

According to another aspect of the present invention, a semiconductor integrated circuit includes a unit circuit group including a plurality of unit circuits having transistors in a chip, and a power source disposed in the chip and supplying power to the unit circuit group. And a ground wiring portion, wherein the power / ground wiring portion includes a capacitance adjusting portion at a position immediately before a branch of the unit circuit group.

The capacitance adjusting section is a wiring section configured such that the capacitance is larger than that of the unit circuit group.

On the other hand, the power supply / ground wiring part includes at least one bypass capacitor, and the bypass capacitor of the power supply / ground wiring part is not larger than (receiving gate capacity + its wiring capacity) / (number of units). It features.

In the above, in the case where a single bypass capacitor is embedded in the unit circuit group, the capacity C _p of the bypass capacitor is C _p ≤ a x N x (receive end) provided that N is the number of units. Gate capacitance + its wiring capacitance), a is a coefficient equivalent to a given execution access in consideration that it is not accessed at the same time, and a <

More specifically, the capacitance C _p of the bypass capacitor is expressed as C _p ≤ a × N × (b + c) fF if the receiving gate capacitance is bfF and the wiring capacitance is cfF, and N = 1 Characterized in that it comprises a.

Each unit forming the unit circuit group is a memory including a plurality of memory cells for storage. In this case, the capacitance C _p of the bypass capacitor is larger than the cell capacity of each memory cell.

In this case, the number N of units is characterized in that it is in the range of 1 to 10.

In more detail, the capacitance C _p of the bypass capacitor is selected to be several times greater than the cell capacity of each memory cell.

The bypass capacitor may be arranged for each unit circuit, or 1 / (by number of the unit circuits) may be arranged in the chip.

In a semiconductor integrated circuit according to another aspect of the present invention, a fine connection pad is disposed on the entire area of the chip and is alternately drawn as a power / ground pad, and the bypass capacitor is connected to a bumpless flip chip connection. And a capacitor group made of the same semiconductor material, the capacitor group being connected to the power / ground pad.

The fine connection pads are arranged in two rows around the chip, and the pads form pad pairs of signals and ground.

In addition, the pitch of the bumpless flip chip connection is characterized in that 10㎛ or less.

The bumpless flip chip is disposed on almost the entire area of the chip.

Preferably, the pad includes a signal pad connected to a driver circuit connected to drive a load of a receiver of a chip different from an external wiring, and the bypass capacitor connected to the driver circuit connected through the signal pad. Is larger than the internal circuit capacitor.

In this case, the bypass capacitor is disposed in any one of the empty space around the chip, the capacitor substrate, and the outer region of the signal pad, and the signal pad is not disposed at the center of the chip.

Further, the capacitor is formed on a capacitor substrate composed of a material different from that of the chip, in which case the capacitor substrate is almost the same area (size) for the SOI capacitor substrate and the intra-chip capacitor. It is characterized in that any one of a capacitor embedded ceramic substrate, and a capacitor embedded plastic thin film wiring substrate.

Under the above conditions, the capacitor is formed as a larger capacitor by lowering the degree of division, while each of the capacitors is provided with an electrode drawn out more than the capacitor.

In the present invention, a direct current resistor is inserted immediately before the output transistor so as to reduce the instantaneous spike current due to the parasitic capacitance charge caused by the depletion layer of the output transistor.

In this case, the sum of the characteristic impedance of the power supply / ground and the series resistance is characterized in that it is less than or equal to the signal line characteristic impedance.

According to the above-described configuration of the present invention, it is possible to provide a semiconductor integrated circuit and a circuit structure capable of sufficiently guaranteeing the charge supply capability of the power source / ground so that even when fast operation is required, the characteristics of the transistor gate circuit are not suppressed.

Although the present invention has been described in connection with some embodiments, various modifications and the like may be made by those skilled in the art to which the present invention is practiced without departing from the spirit of the invention.

Prior to describing a semiconductor integrated circuit and a circuit structure according to an embodiment of the present invention, the principles of the present invention will be described to facilitate understanding of the present invention.

The source of power / ground is usually located outside of the chip and the length of the wiring increases, which prevents the charge supply when the transistor is in the on state. This is a problem in high speed switching. The above problem corresponds to the problem that the fire truck takes a lot of time to reach the fire scene. That is, if a fireplug is provided at a fire place at the time of a fire, people can cope quickly by using the fire hydrant.

The above description is provided if there is sufficient charge storage in the power / ground connection of the transistor that transmits the signal to fill the load capacity of the transistor's load capacitor, i.e., bypass capacitor (also known as decoupling capacitor). Corresponds to the problem. Only the amount of charge in the reservoir needs to be an amount related to the voltage drop of the minimum potential that ensures transistor operation. This is similar to a good fire if there is sufficient fire extinguishing material for the early evolution of a sufficient amount of water or flame.

In the electronic circuit, if a voltage drop within 20% is allowed, for example, the sum of the accumulated charge amount and the parasitic capacitance of the transmit transistor is 5fF, and the charge amount defined similarly for the signal receiving transistor is 5fF, and the transmit transistor and the receive are assumed. Assuming that the wiring capacitance to be connected between the transistors is 10fF, the power supply / ground connection (strictly, the wiring length is physically zero) of the transmitting transistor is 20fF / 0.2 = 100fF = 0.1pF by the formula Q = CV. There is a need to have a pass capacitor.

According to the present invention, the arrangement and configuration of the bypass capacitor according to the above-described principle has been disclosed for supplying charge to a load of a receiving transistor as a load and a transmission line connected to the receiving side transistor.

In addition, it is important that the power transmission pipe connecting to the signal oscillation transistor (driver) from the external power supply through the bypass capacitor is thicker than the transmission line pipe for transmitting the signal. It is already described in detail in Reference 1. Hereinafter, the circuit structure of the present invention will be described on the premise of the structure described in Document 1 above, but the present invention is not necessarily limited to the above structure.

The principles of the invention will now be described in more detail with reference to the accompanying drawings.

First, in Fig. 1, a description will be made of the transient response of a driver circuit made by a transistor. The ideal MOS transistor Q1 is turned on by the ideal input signal, at which time the on-state current (I _o ) = V _dd / R _on . The foregoing premise arises when the power source can supply a charge equivalent to the current at one instant. Assuming there is no switching delay of the transistor, at the next instant the current encounters the transmission line and receives a resistor equivalent to the characteristic impedance.

The equivalent circuit under these conditions is shown in the middle stage of FIG. At this time, the on-state current (I _T = V _dd / (R _on + Z _o ) flows in. The current (I _o ) is usually ignored and whether the power supply can supply the charge through which I _T flows is under discussion. is. current as to define the amount of movement of the charge, the charge amount is Q = 1 × t. although is it that defines the spatial charge density difficult, but the spatial charge density at each location into a voltage at said place. V _dd It is clear from the image that it is not guaranteed at each location Assuming that the power supply is ideal and the condition is maintained for the time t _pd , the amount of charge occupied on the transmission line is expressed as QT = I _T x t _pd .

Thereafter, a new load R _L is applied to the current I _T. The transmission line is fully charged and thus does not become a load, and becomes an equivalent circuit at the bottom of FIG. That is, I _I = V _dd / (R _on + R _L ). The instant the current flowing in I _T encounters in the load the current becomes I _I. In this case, if I _T > I _I , the charge is reflected directly back to the transmission line. If I _T < I _I, negative reflection is observed.

After the time 2t _pd elapses, the power source is affected by the reflection. However, the above problem is not mentioned here because the object of the present invention is to completely solve the problem of the initial state, that is, the problem of the transient state. However, it should be noted that solving the first problem leads to improving the second problem, which leads to an expansion of the design margin for the circuit layer.

In the electronic circuit shown in Fig. 1, the above-described change of state occurs at the speed of light. The switching speed of the conventional transistor is too slow, such as high tide and low tide of the tide compared to the luminous flux of the length of the transmission line was not able to recognize the problem of time lag as shown in FIG.

Next, the present invention will be described with reference to Fig. 2, which metaphorically explains the state of change of charge density for better understanding of the present invention.

In FIG. 2, assume a pipe in which a large tank filled with water is connected to the valve through the pipe and the empty pipe passes through the bottom of the valve and is connected to the load pipe. Assuming that the water tank shown in FIG. 2 corresponds to the supply power supply, the loads of the pipes, valve shutters, empty supply pipes, and thin pipes connected to the water tanks in the circuit shown in FIG. 1 include power supply wiring, transistor gate, signal wiring, And a load, respectively. The shaded portion of FIG. 2 is filled with water, indicating that the water is filled directly up to the valve.

Assuming that the power supply lines have the same characteristic impedance for pipes of the same thickness, ie signal lines, the concept is as shown in FIG. Referring to FIG. 3, the following describes a phenomenon that occurs when the valve is opened when the water source pipe has the same thickness with respect to the supply pipe.

As shown in FIG. 3, the water immediately up to the valve of the water source pipe flows to the bottom of the valve as shown at the top of FIG. 3 as soon as the valve is opened. Although the problem of gravity is ignored, water diffuses into spaces with zero water pressure. The water pressure directly above the valve naturally drops. Information about the water pressure dropped is transmitted to the tank at the rate at which pressure is transmitted, but because the source pipe is long, it takes time. The pressure transfer rate is equal to the speed of sound. In the case of water, the speed is approximately 1000 m / s. In order to compensate for the volume reduction of the piping during this time, the water of the target part must be expanded in three dimensions. In particular, the water pressure of the corresponding part is reduced. Since the upper pipe is the same thickness as the lower pipe, the volume is exactly doubled. Water hardly expands like a solid. Thus, as shown at the bottom of Fig. 3, the flow of water is the flow of water filling about half of the pipe cross section.

The exact same phenomenon occurs in the electronic circuit shown in FIG. The electron density can change indefinitely (like air). Therefore, considering only that the transmission speed is the luminous flux, the above phenomenon can be explained with reference to the conceptual diagram shown at the top of FIG. Naturally, the electron density, ie the voltage reduced by half, is (1/2) V _dd . Depending on the transistor characteristics, an on-state current (I _T = V _dd / (R _on + Z _o )) is expected, but for a time up to 2t _pd , the current ((1/2) I _T = (1/2) V _dd / Only (R _on + Z _o )) will flow. Here, the power supply wiring has the same length and characteristic impedance with respect to the signal wiring. If t _pd of the line is 1 ns, a 1 GHz clock (on time is 0.5 ns or less) is obtained. As is apparent from the above, there is a need to increase the thickness of the piping of the power supply wiring, i.e., to lower the characteristic impedance.

This is the principle for achieving the first and second effects disclosed in Japanese Patent Application No. 2000-350904 (hereinafter referred to as Ref. 2). Since the present invention assumes the above basic configuration, the concept is shown again in FIG.

Referring to the electronic circuit of FIG. 4, the drop in voltage becomes smaller as the volume is reduced. For example, assuming that the characteristic impedance of the power supply wiring is 10 Hz and the characteristic impedance of the signal wiring is 50 Hz, the voltage reduction at the transistor on-resistance of 10 Hz is ((50 + 10) / (10 + 10 + 50)) V _dd = 0.857V _dd .

The above is explained in the simple embodiment of FIG. In Fig. 5, the pair of power supply lines and ground lines are shown as lines of power supply / ground pairs, and are actually represented by a cylindrical shape indicating a distributed constant element circuit, although the power supply and ground wiring patterns are arranged on the chip. The lines of the illustrated power / ground pair are assumed to have characteristic impedance Z _Ops and transmission delay t _pdps . In the same way, it is assumed that the signal line is also represented as a distributed integer element circuit, and has a characteristic impedance Z ₀ and a transmission delay t _pd .

In FIG. 5, current flows through the characteristic impedance Z _0ps of the line of the power / ground pair introduced from the power source. Therefore, the voltage drop of V _dd × (R _on + Z ₀ ) / (R _on + Z ₀ + Z _0ps ) on the signal line is only during the transmission delay time (t _pdps ) due to the length of the line of the power / ground pair. Will occur. This time will be explained in more detail below. Assuming that t is the time when a voltage drop occurs, and if t _pd ≧ t _pdps , the voltage drops during the time that 0 <t <t _pdps is satisfied. If t _pd ≤ t _pdps , the voltage drops during the time that 0 <t <t _pd is satisfied. If the delay time meets the lower _pd t <t <t t _{pdps pdps} than the voltage drop is changed to _{V dd × (R on + R} L) / (R on + R L + Z 0ps).

Although there is an operating time to compensate for the voltage drop on the line of the power / ground pair sensed by the power source and there is a subsequent voltage fluctuation, the description of subsequent voltage fluctuations is directed to improving the initial state of the invention. Will be omitted.

Assuming that the characteristic impedance of the line of the power / ground pair is equal to the characteristic impedance of the signal line and that the on-resistance of the transistor is negligible compared to its characteristic impedance, the amplitude of (1/2) V _dd is first received at the receiver end. Flows into. If the capacity of the receiver stage has a capacity of several fF at the CMOS gate, it is considered almost open end and the signal energy is considered to be fully reflected. The voltage sensed by the CMOS gate is (1/2) x 2V _dd = V _dd . As a result, the signal sent to the gate becomes normal and is transmitted only by the transmission line delay of the signal transmission line.

If several signal lines are supplied in the form of a line of a single signal power / ground pair, the characteristic impedance of the line of the power / ground pair is equal to or less than one-th the number of signal lines. That is, more preferably Z _0ps ≤ Z ₀ / N, where N is the number of shared signal lines. The above is the second condition described in Cited Document 2.

Even with this premise, the problem of power / ground fluctuations still exists and many of the following problems related to transistor switching delays are not solved.

The first problem is that it is not possible to supply the necessary charge for the load present beyond the output signal, and the present invention provides a means to solve the problem. Examples of supplying charge to the load include charge-up for the signal line and charge-up for the gate capacitor of the receiver described above. A smaller power supply / ground characteristic impedance can withstand more rapid charge-up, but the charge supply from a distant power supply is not actually expected and during that time the opposite transition time begins. In conventional products, bypass capacitors are placed as close to the load as possible to solve the problem and bypass capacitors are often integrated into the chip (eg Intel's Pentium® II, Pentium® III, And Pentium® 4).

However, in the conventional products, the power supply / ground is not suitable for line handling, and thus the parasitic inductance L _c becomes high despite the short wiring, and the above problem is not completely solved (bypass capacitor). Is less than or equal to 100 μm of the gate in the publication of Pentium® III).

According to the present invention, it has been found that the transmission line integrated in the chip is very effective when parasitic inductance is also considered. In Fig. 6, the conceptual structure of the present invention is disclosed. From the diagram, a structure in which a more effective intra-chip bypass capacitor C _p (or a bypass capacitor C _{p in a} chip) is embedded adopts a transmission line of a power / ground pair. In addition, it is used additionally.

More specifically, the circuit structure shown in FIG. 6 includes a transmission line 20 and a chip 21 of a power / ground pair. One end of the transmission line 20 of the power / ground pair is connected to the power source 22 and the other end is disposed in the chip 21. The power line of the transmission line 20 of the illustrated power / ground pair is connected to a plurality of driver circuits 25 that operate in response to an input signal in the chip 21. In addition, a plurality of receiver circuits 26 are provided in the chip 21 in addition to the driver circuit 25. The driver circuit 25 and the receiver circuit 26 are respectively connected to each other via the intra-chip signal transmission line 27.

In the above example, it is assumed that N intra-chip signal transmission lines 27 are arranged and each transmission line has a characteristic impedance Z ₀ and a transmission delay t _pd . On the other hand, the transmission line 20 of the power / ground pair has a characteristic impedance (Z _0ps ) and the transmission delay (t _pdps ), and the characteristic impedance (Z _0ps ) of the transmission line 20 of the power / ground pair is a (1 / Assume that N is set not to be higher than Z0 (where a is a coefficient equivalent to the execution access determined considering that N intra-chip signal transmission lines 27 are not simultaneously accessed, and a &lt; 1).

Moreover, the transmission line 20 of the power supply / ground pair of the chip 21 is connected to the bypass capacitor C _p as described above, and the transmission line 20 of the power supply / ground pair has a parasitic inductance L _c . Assume that it is accompanied.

이고 게이트 용량(C_OX) = bε_oxLW/t_OX는 5fF라고 가정한다. In the following, the simulation is performed using the characteristic impedances Z _0ps and Z ₀ of the transmission line 20 and the signal line 27 of the power / ground pair as variables. In this case, the transistors of the driver circuit 25 and the receiver circuit 26 comprise MOS transistors and the on-resistance of the transistors on the transfer side, i.e. the driver circuit 25, is

And gate capacitance C _OX = bε _ox LW / t _OX is 5fF.

In this case, L, W, t _OX , ε _ox , k, b, V _G , V _DD and V _T are the gate length (0.18 μm), gate width (0.5 μm), effective gate oxide film thickness (0.0015 μm), the dielectric constant of _{SiO 2 (4 × 8.854 × 10} -12 F / m), the gain factor (0.001) of the transistor, the effective gate area ratio (ratio of 2.3) to the parasitic capacitance, the gate voltage (0.5V), 1. 5V, and Threshold voltages (0.25V at the receiver) are shown respectively.

Assuming that the signal transition time is 25 ps, the delay time of the signal line is negligible, the parasitic capacitance of the line C ₁ is 10fF, and the gate capacitance of the receiver C _r is 5fF, the equivalent circuit shown in FIG. As shown in.

Based on the equivalent circuit shown in FIG. 7, the overall concept of the essential configuration is varied as the characteristic impedances Z _Ops , Z ₀ of the transmission line 20 and the signal line 27 of the power / ground pair are changed. Based on the results of

Table 1 shows the simulation results.

Condition 1 and Condition 2 are used when the characteristic impedance Z _Ops of the transmission line 20 of the power / ground pair is higher than the characteristic impedance Z ₀ of the two intra-chip signal transmission lines 25. On the other hand, condition 3 and condition 4 are when the characteristic impedance Z _Ops of the transmission line 20 of the power / ground pair is lower than the characteristic impedance Z ₀ of the two intra-chip signal transmission lines 25. Used. As is apparent from this, condition 3 and condition 4 satisfy the necessary conditions of the present invention. In contrast, condition 2 satisfies the requirements of the present invention for parasitic dose L _c .

In Fig. 8, the detailed circuit structure used for the simulation is shown. Here, two signal transmission lines are represented by a single transmission line. As will be apparent from the comparison of FIGS. 7 and 8, the bypass capacitor C _p is set to 60fF to change the parasitic inductance L _c of FIG. 8.

FIG. 9 shows simulation results in the circuit structure shown in FIG. 8 under conditions 1, 2, 3, and 4 of Table 1. FIG. In Fig. 9, the current change in the upper end and the voltage change in the lower end are respectively shown. As shown in Fig. 9, although some resonances were observed in the conditions 3 and 4 in the current and the voltage, this level of resonance energy is actually absorbed by the inserted wiring resistance. Since the ground fluctuation cannot be simulated by the circuit simulation, attention was paid to the supply voltage drop. The output shown in FIG. 9 is shown in Table 2. The condition is satisfactory in the order of Condition 4, Condition 3, Condition 2, and Condition 1.

The characteristic impedance of the line of the power / ground pair is preferably lower than the characteristic impedance of the load line (Z _Ops ) and is good if the parasitic inductance (L _c ) on the bypass capacitor is low.

As is apparent from Table 2, 25 ps or less were observed at the input rise of the simulation under condition 3 or condition 4 and the frequency f equivalent to the pulse was 0.35 / 25 ps = 14 GHz. The results show that switching at 14 GHz is practically possible and much better than the results achieved by the current technology, which makes it clear that the present invention is very effective in high speed operation.

In addition, as in condition 2, the characteristic is improved by reducing the inductance L _c of the bypass capacitor C _p . Thus, it is also possible to propose a configuration for reducing the inductance L _c of the bypass capacitor C _p according to the invention.

In the equivalent circuit shown in Fig. 8, the transmission delay of the line of the power / ground pair is assumed to be 100ps, but in a line with an insulator having a dielectric constant of 4, the transmission delay is equivalent to a wiring length of 15 mm. Simply placing a bypass capacitor around the LSI package pin can function as a power source in this case.

In Fig. 8, assuming that wiring is made from the bypass capacitor to the transistor via the transmission line, a good power supply line with a parasitic inductance of only 50 pH is disclosed. The same logic applies to ground. The capacitance (C _p ) of a 60 fF bypass capacitor, twice the load capacity (C ₁ ), is attached to two sets of drivers and is applied with an extremely large parasitic inductance of 5 nH and 10 pH achievable with the above proposal. For the transmission line, we assume the setting value of 5Ω, which is proposed in this proposal, and 100Ω observed when not considered as a transmission line. Naturally, in the case of 100 Hz, the parasitic inductance is not a low value of 50 pH, but a severe state of several nH. However, low parasitic inductance is used for comparison. Increasing the parasitic inductance of the power supply / ground accelerates the delay of the power supply time. As a result, the effect of the bypass capacitor C _p becomes large. According to the present invention, the low parasitic inductance (condition 2 and condition 4) of the bypass capacitor is effective to overcome this situation.

In general, the above-described simulation results are described. Bypass capacitors are embedded in the power / ground wiring portion just before branching to the unit circuit group, and the group of unit circuits (memory units and logic gates) including the transistors are included. In the semiconductor integrated circuit comprising the capacitor, it was found that the capacity of the bypass capacitor C _p is equal to or less than (the receiver gate capacity + its wiring capacity) / (the number of units). More specifically, in the case where a single bypass capacitor is embedded in the unit circuit group, the capacitance C _p increases with the number N of units and it is effective to be set to satisfy the following equation.

C _P ≤ a × N × (b + c)

Where b is the receiving gate capacitance, c is its wiring capacitance, and a is the coefficient corresponding to execution access (a &lt; 1). In Figure 8, b is 5fF and c is 10fF. Here, it is good if n is chosen in the range between 1-10. In addition, the bypass capacitor function may be equivalently realized by widening a part of the power supply / ground wiring portion as described later, thus eliminating the need to actively place the bypass capacitor.

As a method of supplying power / ground wiring into the chip, a so-called coplanar waveguide method is adopted as the transmission line. For example, in an Intel Pentium® II chip manufactured in a 0.25 μm process, the power / ground wiring of the fifth layer (top layer) has a pitch width of 2.56 μm. However, there is a problem that the line is not practical to reduce the characteristic impedance of the power supply / ground wiring to less than 50 kHz.

Under such circumstances, the present invention adopts a configuration in which a stacked pair of lines as shown in FIG. 10 is used to increase the capacity, thereby lowering the characteristic impedance to less than 50 Hz.

In FIG. 10, the stacked pair of track configurations according to the present invention will be described in more detail. The illustrated embodiment illustrates the configuration of a power / ground pair in a plurality of layers. Here, substrates and components except power / ground pairs are omitted for simplicity. The wide power supply line 31a is disposed on the uppermost layer of FIG. 10 and the plurality of narrow power supply lines 31b are disposed on both sides of the wide power supply line 31a. In addition, like the wide power line 31a, the wide ground line 32a is positioned on the lower layer of the wide power line 31a so as to face the wide power line 31a so as to be stacked. do. A plurality of narrow ground lines 32b are also disposed on both sides of the wide ground line 32a, and the narrow ground lines 32b are disposed opposite the upper power line 31b.

In the illustrated embodiment, the wide power supply line 31a is electrically connected to the power supply layer 31c disposed in the layer below the wide ground line 32a via the plug 33a. The lower power supply layer 31c is narrower than the wide power supply line 31a. On the other hand, the ground layer 32a is electrically connected to the lower ground layer 32c disposed in the lower layer of the power layer 31c via the plug 33b, and the lower ground layer 32c is the lower power layer. It is arranged opposite to 31c.

As described above, the capacity of the power supply / ground pair is increased by using a stacked structure of power supply and ground lines as well as using a wide power supply layer. Accordingly, the characteristic impedance required for the power supply / ground pair can be realized.

If the layer structure described above causes losses due to phase lag and a long approach is also required in the lines of the intra-chip stacked pairs, the bypass capacitors are as close to the transistors as possible and are therefore ideally embedded in the chip.

When stacked pairs of tracks are used, the supply energy increases as described above even though the total number of tracks increases. Thus, a single pair of layers or a maximum of two pairs of layers is sufficient.

In FIG. 11, the circuit structure according to another embodiment of the present invention is similar to the lowermost plug 33b in the hierarchical configuration shown in FIG. 10 by the connection to the power / ground wiring via the plug 40. Capacity can be achieved. Specifically, the circuit structure shown in FIG. 11 includes a power supply line 41 on a chip and a ground line 42 disposed two-dimensionally separated from the power supply line 41.

An inverter including the NMOS 43 and the PMOS 44 is formed in the chip region between the ground line 42 and the power supply line 41. The source of the NMOS 43 is connected to the ground line 42 and the source of the PMOS 44 is connected to the power supply line 41. The gates of the NMOS 41 and the PMOS 42 are commonly connected to the input terminal 45, and the drain of the NMOS 41 and the drain of the PMOS 42 are electrically connected to the output terminal 46. Although a single inverter is shown in this embodiment, a large number of devices (not shown) are usually integrated with the inverter in a semiconductor integrated circuit.

In addition, the power supply line 41 and the ground line 42 are formed in a multi-layered configuration in the same manner as shown in FIG. 10, and the power supply line 41 and the ground line 42 shown in the stacked configuration have different layer shapes. It is laminated on the ground line and the power line. The power supply line 41 and the ground line 42 are electrically connected to the ground line and the power supply line on another layer via the plug 40.

In the example shown above, the power line or ground line on the other layer is provided with a wide electrode portion 47 as shown by the dashed-dotted line, so that the required capacitance can be obtained from the wide electrode portion 47. It is composed. As is apparent from the above, the required capacity is achieved only by the wide electrode portion 47 due to the illustrated configuration. Further, by arranging the wide electrode portion 47 in another unit, it becomes possible to achieve the characteristic impedance of the power supply / ground pair described in FIG.

In FIG. 12, the capacitor is formed of the NMOS 41 and the PMOS 42 shown in FIG. The capacitor is configured to obtain a large capacitance by connecting the drain of the NMOS 43 and the source of the PMOS 44 to the power supply line 41 and the ground line 42 via the diffusion layers 48 and 49, respectively. The gate and the source of the PMOS 44 are connected to the gate and the source of the NMOS 43, respectively. Thus, the required capacitance and characteristic impedance can also be obtained by placing a bypass capacitor with a specially designed gate capacitance.

In Fig. 13, an embodiment of a circuit structure according to another embodiment of the present invention using a capacitor used in a DRAM as a bypass capacitor is shown. More specifically, the access transistor 51 that always maintains the on state is disposed in the P-type substrate 52. The access transistor 51 has two N-type diffusion regions 53 and a gate electrode 54 located in the gate region, and the gate electrode 54 is connected to a word line. In the above embodiment, it is assumed that the word line is always given a signal for turning on the access transistor 51.

In addition, each diffusion region 53 is provided with plugs 55 and 56, which plug 55 is connected to the bit line 57 and the bit line 57 is electrically connected to the upper layer, that is, the power supply layer.

In addition, the plug 57 is connected to the bypass capacitor 60 having the same configuration as the DRAM capacitor. The bypass capacitor 60 includes a lower electrode 61, an upper electrode 62, and a high dielectric layer 63 disposed between the lower electrode 61 and the upper electrode 62.

14, a description will be given of a circuit structure according to another embodiment of the present invention. In the illustrated embodiment, the semiconductor chip 71 is connected to the substrate 72 with the capacitor portion embedded using a bumpless super connection technique. In this case, the active layer and the wiring layer 73 of the chip are formed on the semiconductor chip 71, and the capacitor portion 74 and the substrate wiring portion are disposed on the substrate 72. The bumpless super connection technique for connecting the chip 71 to the substrate 72 is not described because it is already described in JP-A No. 2000-299379. In the structure shown, it has already been confirmed that better simulation results are achieved by inserting a resistor into the chip 71 or the substrate 72. In this case, the resistor may be a semiconductor resistor such as a gate channel resistor and a diffusion layer resistor, or may be a thin film resistor.

In Fig. 15, the configuration shown in Fig. 14 will be described in more detail. In the illustrated embodiment, the stacked paired tracks 75 are disposed on the side of the chip 71 and the stacked paired tracks 76 are also disposed on the side of the substrate 72. The stacked pairs of lines 75, 76 form the lines of the power / ground pair described above. In the illustrated embodiment, the stacked pairs of lines 75, 76 are arranged to intersect at right angles and are connected to each other via plug 77 by a bumpless super connection technique.

In FIG. 16, the same configuration as shown in FIG. 15 is shown except that the stacked pairs of lines 75 and 76 are positioned and arranged in parallel so as to face each other vertically.

In Fig. 17, a sample cross section of a bumpless shooter connection will be shown below. In the chip 71, the intra-chip power supply line 71a and the intra-chip ground line 71b are wired in the form of a stacked pair. On the other hand, the intra-substrate power supply line 72a and the intra-substrate ground line 72b are disposed in the substrate 72. In this example, the buried capacitor is disposed within a portion of the intra-substrate ground line 72b and a portion of the intra-substrate power line 72a in the substrate 72 in which the high dielectric 83 is an intra-substrate power line. Disposed between a portion of 72a and a portion of intra-substrate ground line 72b. In addition, each line in the chip 71 is connected to a pair of lines in which power / ground is stacked in the substrate via the plug 84. Although the connections between the above are shown in succession by the plugs, bumpless super connection technology can be used for the boundary connection between them and the dummy wiring layer 85 can be used to ensure the connection in the area where the plug is not used. . In addition, a plug is arranged in the plug, and the capacitor of the substrate is connected by the plug. In this example, high dielectric 83 is used as the capacitor to reduce the opposing area, but ordinary dielectric capacitors can of course be used. The dummy connection wiring 85 can be used as the capacitor electrode in the above configuration.

As mentioned above, the paired power / ground pairs at the top layer include wide wiring in the form of a sprip under electrical energy control conditions, regardless of miniaturization in the manufacturing process. The wiring pitch is several μm. If the external connection pad corresponding to the pitch is formed as shown in Figs. 15 and 16, the same effect can be achieved by embedding the capacitor in the mounting substrate instead of placing the bypass capacitor in the chip. In this case, it is preferable to use the bumpless super connection technique described above. In addition, it is good to select a plug pitch or a bump pitch in the range of 2-10 micrometers. If the bypass capacitor embedded in the substrate is a Si substrate, the same structure as in the chip is obtained. If it is an insulated substrate made of alumina, polyimide, or benzocyclobutane, all kinds of conventional capacitor configurations such as, for example, metal electrode capacitors or multi-layer capacitors can be adopted.

Furthermore, if a variable capacitor is arranged in the driver circuit, the bypass capacitor according to the present invention can be configured to be complementary in operation to the variable capacitor. More specifically, complementary operation can be realized by using a bypass capacitor configured as shown in FIG. 12 and having the same size as the inverter.

1 is a diagram showing a circuit structure illustrating the principle of the present invention.

2 is a diagram metaphorically illustrating the principles of the present invention using a piping model of water.

3 is a diagram illustrating the operation of the system shown in FIG. 2 in more detail.

4 is a diagram illustrating the operation of a model modified based on the model of FIG.

FIG. 5 is an equivalent diagram illustrating an electronic circuit corresponding to the model shown in FIG. 4. FIG.

6 is a circuit diagram conceptually illustrating the present invention.

FIG. 7 is an equivalent circuit diagram of the circuit diagram shown in FIG. 6. FIG.

FIG. 8 is an equivalent circuit diagram showing in more detail the equivalent circuit diagram shown in FIG. 7. FIG.

9 is a diagram showing a simulation result of the circuit shown in FIG. 8;

10 is a three-dimensional wiring diagram illustrating a circuit structure according to an embodiment of the present invention.

11 is a plan view showing a circuit structure according to another embodiment of the present invention.

12 is a circuit structure diagram according to still another embodiment showing a modification of the circuit structure shown in FIG.

13 is a diagram showing a circuit structure according to another embodiment of the present invention.

Fig. 14 is a diagram showing a connection method used when forming a circuit structure according to another embodiment of the present invention.

FIG. 15 is a diagram showing an embodiment of a wiring structure connected using the connection method shown in FIG. 14; FIG.

FIG. 16 is a diagram showing another embodiment of a wiring structure connected using the connection method shown in FIG.

17 is a diagram showing in more detail a substrate and a chip connected using the connection method.

Claims (24)

In a semiconductor integrated circuit, A unit circuit group including a plurality of unit circuits having transistors in a chip, A power supply / ground wiring portion disposed in the chip and supplying power to the unit circuit group, The power / ground wiring portion includes a capacitance adjusting portion at a position immediately before a branch of the unit circuit group, And the capacitance adjusting section is a wiring section configured such that the capacitance is larger than that of the unit circuit group. delete The method of claim 1, And the power / ground wiring portion comprises at least one bypass capacitor. The method of claim 3, And the bypass capacitor of the power supply / ground wiring portion is not larger than (receive end gate capacity + its wiring capacitance) / (number of units). The method of claim 3, In the case where a single bypass capacitor is embedded in the unit circuit group, the capacity C _p of the bypass capacitor is C _p ≤ a x N x (receive end gate capacity + its wiring, provided that N is the number of units). Capacity) a is a coefficient equivalent to a given execution access in consideration of not being accessed at the same time, wherein a &lt; The method of claim 5, The capacitance C _p of the bypass capacitor is represented by C _p ≤ a × N × (b + c) fF when the receiving gate capacitance is bfF and the wiring capacitance is cfF. A semiconductor integrated circuit comprising N = 1. The method of claim 5, And each unit forming the unit circuit group is a memory including a plurality of memory cells for storage. The method of claim 7, wherein And the capacitance C _p of the bypass capacitor is greater than the cell capacity of each memory cell. The method of claim 8, And the number N of units is in the range of 1 to 10. The method of claim 9, And the capacitance C _p of the bypass capacitor is selected as a multiple of the cell capacitance of each memory cell. The method of claim 8, Wherein the bypass capacitors are arranged per unit circuit, or fewer bypass capacitors are disposed in a chip than the number of the unit circuits. The method of claim 5, Fine connection pads are disposed over the entire area of the chip and alternately drawn out as power / ground pads, And the bypass capacitor includes a group of capacitors made of the same semiconductor material in a bumpless flip chip connection, the group of capacitors being connected to the power / ground pad. The method of claim 12, And the fine connection pads are arranged in two rows around the chip and the pads form pad pairs of signal and ground. The method of claim 12, And a pitch of the bumpless flip chip connection is 10 mu m or less. The method of claim 14, And the bumpless flip chip is disposed over an entire area of the chip. The method of claim 12, The pad has a signal pad connected to a driver circuit connected for driving a load of a receiver of a chip different from the external wiring; And the bypass capacitor connecting to the driver circuit connected through the signal pad is larger than an internal circuit capacitor. The method of claim 16, And the bypass capacitor is disposed in any one of an empty space around the chip, a capacitor substrate, and an outer region of the signal pad. The method of claim 16, And the signal pad is not disposed at the center of the chip. The method of claim 12, And the capacitor is formed on a capacitor substrate made of a material different from that of the chip. The method of claim 19, Wherein the capacitor substrate is any one of an SOI capacitor substrate, a capacitor embedded ceramic substrate having the same area for an intra-chip capacitor, and a capacitor embedded plastic thin film wiring board. The method of claim 20, And the capacitor is formed as a larger capacitor by lowering the degree of division. The method of claim 21, And the capacitor is provided with an electrode drawn out more than the capacitor. The method of claim 21, And a direct current resistor is inserted immediately before the output transistor to reduce the instantaneous spike current due to the parasitic capacitance charge caused by the depletion layer of the output transistor. The method of claim 23, wherein Wherein the sum of the characteristic impedance of the power supply / ground and the series resistance is less than or equal to the signal line characteristic impedance.

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