KR100945761B1 - Single-side Polishing Method of Bare Semiconductor Wafers - Google Patents
Single-side Polishing Method of Bare Semiconductor Wafers Download PDFInfo
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- KR100945761B1 KR100945761B1 KR1020080042753A KR20080042753A KR100945761B1 KR 100945761 B1 KR100945761 B1 KR 100945761B1 KR 1020080042753 A KR1020080042753 A KR 1020080042753A KR 20080042753 A KR20080042753 A KR 20080042753A KR 100945761 B1 KR100945761 B1 KR 100945761B1
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- 238000005498 polishing Methods 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 13
- 235000012431 wafers Nutrition 0.000 title description 39
- 239000004744 fabric Substances 0.000 claims abstract description 39
- 239000012528 membrane Substances 0.000 claims abstract description 16
- 239000013013 elastic material Substances 0.000 claims abstract description 5
- 229920002050 silicone resin Polymers 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 1
- 239000002086 nanomaterial Substances 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 7
- 239000003795 chemical substances by application Substances 0.000 description 5
- 238000005259 measurement Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/27—Work carriers
- B24B37/30—Work carriers for single side lapping of plane surfaces
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- Microelectronics & Electronic Packaging (AREA)
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- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
본 발명은, 폴리싱될 반도체 웨이퍼의 이면에 폴리싱 압력을 전달하게 되는 탄성 재료로 이루어진 멤브레인이 있는 폴리싱 헤드를 이용함에 의한 베어 반도체 웨이퍼의 단면 폴리싱 방법으로서, 상기 반도체 웨이퍼는, 매끈한 표면을 갖고 폴리싱제가 공급되는 동안 폴리싱 천에 대해 압박되는 한편 리테이너 링(retainer ring)에 의해 멤브레인에서 미끄러져 벗어나는 것이 방지되는 것인 베어 반도체 웨이퍼의 단면 폴리싱 방법에 관한 것이다. 상기 리테이너 링에는 폴리싱 천에 면하는 측면상에 채널이 마련되어 있다.SUMMARY OF THE INVENTION The present invention is a cross-sectional polishing method of a bare semiconductor wafer by using a polishing head having a membrane made of an elastic material that transmits a polishing pressure to the backside of a semiconductor wafer to be polished, wherein the semiconductor wafer has a smooth surface and a polishing agent is used. A method of cross-sectional polishing of a bare semiconductor wafer, which is pressed against a polishing cloth while being fed while being prevented from slipping out of the membrane by a retainer ring. The retainer ring is provided with a channel on the side facing the polishing cloth.
Description
본 발명은, 폴리싱될 반도체 웨이퍼의 이면에 폴리싱 압력을 전달하게 되는 탄성 재료로 이루어진 멤브레인이 있는 폴리싱 헤드를 이용함에 의한 베어(미구조화) 반도체 웨이퍼의 단면 폴리싱[CMP; chemical-mechanical polishing(화학 기계적 폴리싱)] 방법에 관한 것이다.The present invention relates to cross-sectional polishing of bare (non-structured) semiconductor wafers by using a polishing head having a membrane made of an elastic material that transmits a polishing pressure to the backside of the semiconductor wafer to be polished [CMP; chemical-mechanical polishing].
멤브레인(멤브레인 캐리어)을 구비한 상기 폴리싱 헤드(또는 캐리어 헤드)는 특히 전자 부품의 구조를 평탄화하기 위해 이용된다. 그러나, 때때로, 베어 반도체 웨이퍼의 폴리싱을 위해서도 폴리싱 헤드가 이용된다는 보고가 있다. 이러한 예는 미국 특허출원공개공보 제 2002/0077039 A 호에서 찾을 수 있다. CMP의 주요 목적은, 폴리싱된 반도체 웨이퍼의 최대한 전체적이고 국부적인 평탄화를 이루는 것이다.The polishing head (or carrier head) with a membrane (membrane carrier) is used in particular for flattening the structure of electronic components. However, sometimes there are reports that a polishing head is also used for polishing a bare semiconductor wafer. Such an example may be found in US Patent Application Publication No. 2002/0077039 A. The main purpose of CMP is to achieve maximum overall and local planarization of the polished semiconductor wafer.
폴리싱 천(polishing cloths)에는 흔히 홈으로 형성된 표면 구조[조직(texture)]가 마련되어 있다. 상기 홈은, 폴리싱 천 위의 폴리싱제(polishing agent)의 균일한 분포 및 그에 따른 반도체 웨이퍼의 균일한 폴리싱을 촉진한다. 미국 특허출원공개공보 제 2005/0202761 A1 호는, 홈이 마련되어 있고 폴리싱제의 분포 및 소비에 관하여 최적화된 폴리싱 천을 이용한 CMP 방법을 설명하고 있다.Polishing cloths are often provided with a grooved surface structure (texture). The groove promotes a uniform distribution of polishing agent on the polishing cloth and thus a uniform polishing of the semiconductor wafer. US Patent Application Publication No. 2005/0202761 A1 describes a CMP method using a polishing cloth that is grooved and optimized for the distribution and consumption of the polishing agent.
국부적인 평탄화에 관한 베어 반도체 웨이퍼의 특성에 대한 요건은, 특히 나노구조형상(nanotopography) 파장 스펙트럼에서 끊임없이 증가하고 있고, 이들 요건을 충족할 수 있도록 특별한 노력이 필요하다. 본 발명의 발명자에 의한 실험에, 베어 반도체 웨이퍼를 폴리싱하는데에 조직화된 폴리싱 천과 조합하여 멤브레인 폴리싱 헤드를 이용하게 되면, 폴리싱된 반도체 웨이퍼의 나노구조형상이 그 요건을 충족하지 못하는 것으로 확인되었다. The requirements for the properties of bare semiconductor wafers with respect to local planarization are constantly increasing, especially in the nanotopography wavelength spectrum, and special efforts are needed to meet these requirements. In experiments by the inventors of the present invention, when using a membrane polishing head in combination with an organized polishing cloth for polishing a bare semiconductor wafer, it was found that the nanostructure of the polished semiconductor wafer did not meet its requirements.
따라서, 본 발명의 목적은, 전술한 단점을 극복하고, 탄성 재료로 이루어진 멤브레인을 구비한 폴리싱 헤드를 이용하여, 베어 반도체 웨이퍼를 단면 폴리싱하기 위한, 전체 범위에서 새로운 요건에 부합하는 방법을 제공하는 것에 있다. It is therefore an object of the present invention to overcome the aforementioned disadvantages and to provide a method which meets new requirements in a full range for cross-sectional polishing bare semiconductor wafers using a polishing head having a membrane made of an elastic material. Is in.
상기 목적은, 폴리싱될 반도체 웨이퍼의 이면에 폴리싱 압력을 전달하게 되는 탄성 재료로 이루어진 멤브레인이 있는 폴리싱 헤드를 이용함에 의한 베어 반도체 웨이퍼의 단면 폴리싱 방법으로서, 상기 반도체 웨이퍼가, 폴리싱제가 공급되는 동안에 매끈한 표면을 갖고 폴리싱제를 공급하는 폴리싱 천에 대해 압박되는 한편, 리테이너 링(retainer ring)에 의해 멤브레인에서 미끄러져 벗어나는 것이 방지되며, 상기 리테이너 링에는 폴리싱 천에 면하는 측면상에 채널이 마련되어 있는 것인 방법에 의해 달성된다.The object is a cross-sectional polishing method of a bare semiconductor wafer by using a polishing head having a membrane made of an elastic material that transmits a polishing pressure to the back side of the semiconductor wafer to be polished, wherein the semiconductor wafer is smooth while the polishing agent is supplied. Pressed against a polishing cloth having a surface and supplying a polishing agent, while being prevented from slipping out of the membrane by a retainer ring, the retainer ring being provided with a channel on the side facing the polishing cloth; Is achieved by the method.
본 발명에 따른 방법에 의하면, 반도체 웨이퍼를 최대한 전체적이고 국부적으로 평탄화할 수 있으며 폴리싱 후에 보다 우수한 나노구조형상을 나타낼 수 있는 효과가 있다. According to the method according to the present invention, it is possible to planarize the semiconductor wafer as fully and locally as possible and to exhibit a better nanostructure shape after polishing.
본 발명의 발명자들은, 연구중에, 바람직하지 않은 나노구조형상은 이용된 폴리싱 천의 표면 구조에 실질적으로 기인하였다는 점을 확인하였다. 폴리싱 천에 는 홈의 패턴이 마련되어 있는데, 이는 폴리싱천에 폴리싱제가 넓은 표면에 걸쳐 공급되게 하고 폴리싱 후에 폴리싱 천으로부터 반도체 웨이퍼를 용이하게 들어올리기 위함이다.The inventors of the present invention, during the study, found that the undesirable nanostructures were substantially attributable to the surface structure of the polishing cloth used. The polishing cloth is provided with a pattern of grooves in order to allow the polishing cloth to be supplied over a large surface and to easily lift the semiconductor wafer from the polishing cloth after polishing.
본 발명의 방법은 그러한 폴리싱 천을 제거하여, 필요한 나노구조형상을 얻을 수 있다. 대신에, 반도체 웨이퍼는 조직화되지 않은, 즉 매끈한 표면을 갖는 폴리싱 천에서 폴리싱되고, 여기서 매끈한 표면이란 인위적으로 첨가된 음각[예컨대, 홈(grooves) 또는 리세스(recesses)] 및 인위적으로 첨가된 양각[예컨대, 리지(ridges) 또는 범프(bumps)]을 구비하지 않는 표면을 의미하고자 한 것이다. 폴리싱 천의 표면은, 폴리싱 중에 반도체 웨이퍼와 접촉하게 되는 영역에서만 매끈할 필요가 있다. The method of the present invention can remove such polishing cloth to obtain the required nanostructure shape. Instead, the semiconductor wafer is polished in a polishing cloth having an unorganized, ie smooth surface, wherein the smooth surface is an artificially added intaglio (eg, grooves or recesses) and artificially added embossing. It is intended to mean a surface that does not have (eg, ridges or bumps). The surface of the polishing cloth needs to be smooth only in the areas where it comes into contact with the semiconductor wafer during polishing.
그러나, 매끈한 표면을 갖는 폴리싱 천을 이용하는 것은 조직화된 폴리싱 천을 이용함으로써 피할 수 있는 문제를 수반하기도 한다. 폴리싱 천의 홈은, 폴리싱 후에 폴리싱 천으로부터 반도체 웨이퍼를 들어올리는 것을 용이하게 한다. 폴리싱 천과 반도체 웨이퍼 사이에 수용된 폴리싱제는 폴리싱 천에 반도체 웨이퍼가 강하게 부착되게 한다. 폴리싱 헤드의 멤.브레인은 비교적 연질이어서, 폴리싱 헤드가 매끈한 폴리싱 천으로부터 들어 올려질 때 반도체 웨이퍼가 기울어지고 멤브레인에서 분리되기 쉽다. 따라서, 폴리싱 천으로부터 폴리싱 헤드와 함께 반도체 웨이퍼를 들어올리려 시도할 때, 반도체 웨이퍼가 폴리싱 천 위에 남아있을 수 있다. 이를 막기 위해, 본 발명에 따른 방법에서 바람직하게는 30 mm/min 이상 50 mm/min 이하의 속도로 폴리싱한 후에 폴리싱 헤드가 폴리싱 천으로부터 들어 올려진다. 더 높은 속도에서는, 반도체 웨이퍼가 폴리싱 천 위에 남겨지는 일이 흔히 발생한다. 또한, 폴리싱하고 나서 폴리싱 천을 들어올리기 전에, 폴리싱 천 내의 홈에 의해 또는 폴리싱 플레이트의 에지에 의해 폴리싱 헤드를 안내하는 것이 바람직하다. 이는 마찬가지로 반도체 웨이퍼의 고착력을 감소시키는 역할을 한다. 홈은, 폴리싱 중에 반도체 웨이퍼에 의해 덮이지 않은 폴리싱 천의 영역에, 바람직하게는 에지 영역에 있는데, 이는 본 발명에 따르면 매끈한 폴리싱 천이 폴리싱을 위해 요구되기 때문이다. However, using a polishing cloth having a smooth surface also entails a problem that can be avoided by using an organized polishing cloth. The groove of the polishing cloth facilitates lifting the semiconductor wafer from the polishing cloth after polishing. The polishing agent contained between the polishing cloth and the semiconductor wafer causes the semiconductor wafer to adhere strongly to the polishing cloth. The membrane of the polishing head is relatively soft, so that the semiconductor wafer is inclined and detached from the membrane when the polishing head is lifted from a smooth polishing cloth. Thus, when attempting to lift the semiconductor wafer together with the polishing head from the polishing cloth, the semiconductor wafer may remain on the polishing cloth. To prevent this, in the method according to the invention, the polishing head is lifted from the polishing cloth after polishing at a speed of preferably at least 30 mm / min and at most 50 mm / min. At higher speeds, it often happens that semiconductor wafers are left on the polishing cloth. It is also preferable to guide the polishing head by grooves in the polishing cloth or by the edge of the polishing plate after polishing and before lifting the polishing cloth. This likewise serves to reduce the sticking force of the semiconductor wafer. The grooves are in the area of the polishing cloth, which is not covered by the semiconductor wafer during polishing, preferably in the edge area, because according to the invention a smooth polishing cloth is required for polishing.
베어 반도체 웨이퍼의 폴리싱을 위해 고려되어야 하는 또 다른 정성적 파라미터는 헤이즈(haze)(미세거칠기)이다. 폴리싱 천에 면하는 측면 상에 채널이 마련되어 있는 리테이너 링이 폴리싱에 이용될 때 특히 낮은 헤이즈 값이 얻어진다는 것을 알아냈다. 예컨대 미국 특허 제 6,224,472 B1 호에는 적합한 리테이너 링이 개시되어 있다. 300 mm의 직경을 갖는 베어 반도체 웨이퍼를 폴리싱하기 위해, 채널의 수는 바람직하게는 적어도 30개, 특히 바람직하게는 적어도 45개이며, 이는 헤이즈(미세거칠기)가 채널의 수가 증가함에 따라 감소하는 경향이 있기 때문이다. Another qualitative parameter that should be considered for polishing bare semiconductor wafers is haze (fine roughness). It has been found that particularly low haze values are obtained when retainer rings with channels on the side facing the polishing cloth are used for polishing. For example, US Pat. No. 6,224,472 B1 discloses a suitable retainer ring. In order to polish bare semiconductor wafers having a diameter of 300 mm, the number of channels is preferably at least 30, particularly preferably at least 45, which means that haze tends to decrease as the number of channels increases. Because of this.
베어 반도체 웨이퍼는 금속성 불순물 또는 입자에 기인한 오염에 대해 보호되어야 한다. 따라서, 폴리싱 중에 반도체 웨이퍼와 직접 접촉하는 폴리싱 헤드의 멤브레인은 적절한 재료로 이루어져야 한다. 가능한 한 적은 수의 입자가 형성되도록, 가능한 한 어떠한 금속도 배출되어서는 안 되며 가능한 최저의 마찰 계수를 가져야 한다. 실리콘 수지로 이루어진 멤브레인이 특히 적절한 것으로 입증되었다. Bare semiconductor wafers must be protected against contamination due to metallic impurities or particles. Therefore, the membrane of the polishing head that is in direct contact with the semiconductor wafer during polishing should be made of a suitable material. In order to form as few particles as possible, no metal should be released as far as possible and have the lowest coefficient of friction possible. Membranes made of silicone resins have proved particularly suitable.
본 발명의 성과는, 실시예와 비교예를 비교함으로써 이하에서 설명될 것이 다. The achievements of the present invention will be described below by comparing Examples and Comparative Examples.
실시예와Examples and 비교예Comparative example ::
300 mm의 직경을 갖는 실리콘으로 제조된 반도체 웨이퍼를 단면 폴리싱하였고, 그 폴리싱 결과가 나노구조형상에 대하여 조사되었다. 본 발명에 따른 방법에 의해 폴리싱된 반도체 웨이퍼의 군은, 비교예의 반도체 웨이퍼와 동일한 조건하에서 폴리싱되었을지라도, 폴리싱 후에 보다 우수한 나노구조형상을 나타냈다. 유일한 차이점은, 비교예의 반도체 웨이퍼는 조직화된 폴리싱 천 위에서 폴리싱되었다는 점이었다. 도 1 및 도 2는 각각 실시예의 반도체 웨이퍼와 비교예의 반도체 웨이퍼 에서의 나노구조형상 측정 결과를 도시한다. 비교예의 반도체 웨이퍼의 경우에 폴리싱 천의 조직의 흔적을 명확히 확인할 수 있는데(도 2), 이는 나노구조형상이 손상되었다는 것을 의미한다. A semiconductor wafer made of silicon having a diameter of 300 mm was polished in cross section and the polishing result was examined for nanostructures. The group of semiconductor wafers polished by the method according to the invention showed better nanostructure shapes after polishing, even if polished under the same conditions as the semiconductor wafers of the comparative example. The only difference was that the semiconductor wafer of the comparative example was polished on a textured polishing cloth. 1 and 2 show the results of nanostructure measurements on the semiconductor wafer of Example and the semiconductor wafer of Comparative Example, respectively. In the case of the semiconductor wafer of the comparative example, traces of the structure of the polishing cloth can be clearly seen (FIG. 2), which means that the nanostructure shape is damaged.
도 1은 실시예의 반도체 웨이퍼에서의 나노구조형상 측정 결과를 도시한다.1 shows the results of nanostructure measurements on semiconductor wafers of Examples.
도 2는 비교예의 반도체 웨이퍼에서의 나노구조형상 측정 결과를 도시한다.2 shows nanostructure shape measurement results on a semiconductor wafer of Comparative Example.
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|---|---|---|---|
| DE102007026292.4 | 2007-06-06 | ||
| DE102007026292A DE102007026292A1 (en) | 2007-06-06 | 2007-06-06 | Process for one-sided polishing of unstructured semiconductor wafers |
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| KR20080107258A KR20080107258A (en) | 2008-12-10 |
| KR100945761B1 true KR100945761B1 (en) | 2010-03-08 |
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| KR1020080042753A KR100945761B1 (en) | 2007-06-06 | 2008-05-08 | Single-side Polishing Method of Bare Semiconductor Wafers |
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| US (1) | US20080305722A1 (en) |
| JP (1) | JP2008306189A (en) |
| KR (1) | KR100945761B1 (en) |
| CN (1) | CN101320690A (en) |
| DE (1) | DE102007026292A1 (en) |
| SG (1) | SG148911A1 (en) |
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Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009030292B4 (en) * | 2009-06-24 | 2011-12-01 | Siltronic Ag | Method for polishing both sides of a semiconductor wafer |
| DE102009030295B4 (en) | 2009-06-24 | 2014-05-08 | Siltronic Ag | Method for producing a semiconductor wafer |
| DE102009038941B4 (en) | 2009-08-26 | 2013-03-21 | Siltronic Ag | Method for producing a semiconductor wafer |
| DE102009051008B4 (en) | 2009-10-28 | 2013-05-23 | Siltronic Ag | Method for producing a semiconductor wafer |
| DE102009052744B4 (en) | 2009-11-11 | 2013-08-29 | Siltronic Ag | Process for polishing a semiconductor wafer |
| DE102010005904B4 (en) * | 2010-01-27 | 2012-11-22 | Siltronic Ag | Method for producing a semiconductor wafer |
| DE102010010885B4 (en) * | 2010-03-10 | 2017-06-08 | Siltronic Ag | Method for polishing a semiconductor wafer |
| DE102010013520B4 (en) | 2010-03-31 | 2013-02-07 | Siltronic Ag | Process for double-sided polishing of a semiconductor wafer |
| DE102010014874A1 (en) | 2010-04-14 | 2011-10-20 | Siltronic Ag | Method for producing a semiconductor wafer |
| DE102010024040A1 (en) | 2010-06-16 | 2011-12-22 | Siltronic Ag | Process for polishing a semiconductor wafer |
| CN102263024A (en) * | 2011-07-18 | 2011-11-30 | 北京通美晶体技术有限公司 | Back side anticorrosion method of single side polishing wafer |
| DE102011082777A1 (en) | 2011-09-15 | 2012-02-09 | Siltronic Ag | Method for double-sided polishing of semiconductor wafer e.g. silicon wafer, involves forming channel-shaped recesses in surface of polishing cloth of semiconductor wafer |
| DE102011089362B4 (en) | 2011-12-21 | 2014-01-16 | Siltronic Ag | A method of polishing a substrate of semiconductor material |
| DE102012201516A1 (en) | 2012-02-02 | 2013-08-08 | Siltronic Ag | Semiconductor wafer polishing method for semiconductor industry, involves performing removal polishing on front and back sides of wafer, and single-sided polishing on front side of wafer in presence of polishing agent |
| DE102013204839A1 (en) | 2013-03-19 | 2014-09-25 | Siltronic Ag | Method of polishing a wafer of semiconductor material |
| DE102013205448A1 (en) | 2013-03-27 | 2014-10-16 | Siltronic Ag | A method of polishing a substrate of semiconductor material |
| DE102013213838A1 (en) | 2013-07-15 | 2014-09-25 | Siltronic Ag | A method of polishing a substrate of semiconductor material |
| DE102015217109B4 (en) | 2015-09-08 | 2022-08-18 | Siltronic Ag | Process for polishing a substrate made of semiconductor material |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030171076A1 (en) | 2002-01-22 | 2003-09-11 | Moloney Gerard S. | Chemical mechanical polishing apparatus and method having a retaining ring with a contoured surface for slurry distribution |
| US20050221734A1 (en) | 2001-12-27 | 2005-10-06 | Zuniga Steven M | Carrier head with a non-stick membrane |
| WO2005123342A1 (en) | 2004-06-17 | 2005-12-29 | Systems On Silicon Manufacturing Co. Pte. Ltd. | Process for producing improved membranes |
| US20060046621A1 (en) * | 2004-08-31 | 2006-03-02 | Tech Semiconductor Singapore Pte. Ltd. | Retaining ring structure for edge control during chemical-mechanical polishing |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5769696A (en) * | 1995-02-10 | 1998-06-23 | Advanced Micro Devices, Inc. | Chemical-mechanical polishing of thin materials using non-baked carrier film |
| JP3106418B2 (en) * | 1996-07-30 | 2000-11-06 | 株式会社東京精密 | Polishing equipment |
| US5944583A (en) * | 1997-03-17 | 1999-08-31 | International Business Machines Corporation | Composite polish pad for CMP |
| US6132294A (en) * | 1998-09-28 | 2000-10-17 | Siemens Aktiengesellschaft | Method of enhancing semiconductor wafer release |
| US6287174B1 (en) * | 1999-02-05 | 2001-09-11 | Rodel Holdings Inc. | Polishing pad and method of use thereof |
| US6527624B1 (en) * | 1999-03-26 | 2003-03-04 | Applied Materials, Inc. | Carrier head for providing a polishing slurry |
| US6224472B1 (en) | 1999-06-24 | 2001-05-01 | Samsung Austin Semiconductor, L.P. | Retaining ring for chemical mechanical polishing |
| US6267643B1 (en) * | 1999-08-03 | 2001-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd | Slotted retaining ring for polishing head and method of using |
| EP2085181A1 (en) * | 2000-07-31 | 2009-08-05 | Ebara Corporation | Substrate holding apparatus and substrate polishing apparatus |
| EP1193031A1 (en) * | 2000-09-29 | 2002-04-03 | Infineon Technologies SC300 GmbH & Co. KG | Arrangement for polishing disk-like objects |
| DE10058305A1 (en) | 2000-11-24 | 2002-06-06 | Wacker Siltronic Halbleitermat | Process for the surface polishing of silicon wafers |
| KR100867339B1 (en) * | 2000-12-01 | 2008-11-06 | 도요 고무 고교 가부시키가이샤 | Polishing pads and manufacturing method thereof |
| DE10217374A1 (en) * | 2002-04-18 | 2003-06-18 | Wacker Siltronic Halbleitermat | Production of semiconductor wafers made from silicon comprises sawing a single crystal made from silicon into silicon wafers, forming a mechanical cut on both sides of the wafers, polishing using polishing plates, and surface polishing |
| US6869335B2 (en) * | 2002-07-08 | 2005-03-22 | Micron Technology, Inc. | Retaining rings, planarizing apparatuses including retaining rings, and methods for planarizing micro-device workpieces |
| JP2005026538A (en) * | 2003-07-04 | 2005-01-27 | Renesas Technology Corp | Method of manufacturing semiconductor integrated circuit device |
| KR100600231B1 (en) * | 2003-07-12 | 2006-07-13 | 동부일렉트로닉스 주식회사 | CMP polishing head and its operation method |
| US6821192B1 (en) * | 2003-09-19 | 2004-11-23 | Applied Materials, Inc. | Retaining ring for use in chemical mechanical polishing |
| TWI280177B (en) * | 2004-02-02 | 2007-05-01 | Powerchip Semiconductor Corp | Dummy process of chemical mechanical polishing process and polishing pad conditioning method |
| US6951510B1 (en) | 2004-03-12 | 2005-10-04 | Agere Systems, Inc. | Chemical mechanical polishing pad with grooves alternating between a larger groove size and a smaller groove size |
| KR100632468B1 (en) * | 2005-08-31 | 2006-10-09 | 삼성전자주식회사 | Retainer Rings, Polishing Heads & Chemical Mechanical Polishing Devices |
| JP2008062355A (en) * | 2006-09-08 | 2008-03-21 | Fujitsu Ltd | Polishing apparatus and method for manufacturing electronic apparatus |
-
2007
- 2007-06-06 DE DE102007026292A patent/DE102007026292A1/en not_active Ceased
-
2008
- 2008-04-09 SG SG200802734-4A patent/SG148911A1/en unknown
- 2008-04-28 CN CNA2008100948297A patent/CN101320690A/en active Pending
- 2008-05-08 KR KR1020080042753A patent/KR100945761B1/en active IP Right Grant
- 2008-05-14 TW TW097117655A patent/TW200849357A/en unknown
- 2008-05-22 US US12/154,347 patent/US20080305722A1/en not_active Abandoned
- 2008-06-06 JP JP2008148771A patent/JP2008306189A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050221734A1 (en) | 2001-12-27 | 2005-10-06 | Zuniga Steven M | Carrier head with a non-stick membrane |
| US20030171076A1 (en) | 2002-01-22 | 2003-09-11 | Moloney Gerard S. | Chemical mechanical polishing apparatus and method having a retaining ring with a contoured surface for slurry distribution |
| WO2005123342A1 (en) | 2004-06-17 | 2005-12-29 | Systems On Silicon Manufacturing Co. Pte. Ltd. | Process for producing improved membranes |
| US20060046621A1 (en) * | 2004-08-31 | 2006-03-02 | Tech Semiconductor Singapore Pte. Ltd. | Retaining ring structure for edge control during chemical-mechanical polishing |
Also Published As
| Publication number | Publication date |
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| CN101320690A (en) | 2008-12-10 |
| JP2008306189A (en) | 2008-12-18 |
| SG148911A1 (en) | 2009-01-29 |
| US20080305722A1 (en) | 2008-12-11 |
| TW200849357A (en) | 2008-12-16 |
| DE102007026292A1 (en) | 2008-12-11 |
| KR20080107258A (en) | 2008-12-10 |
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