KR100939407B1 - Flash memory device and manufacturing method thereof - Google Patents

Abstract

According to an exemplary embodiment of the present invention, an upper portion of a first gate insulating layer and a second gate insulating layer is formed such that both ends of the first gate insulating layer formed on the semiconductor substrate, the second gate insulating layer formed on the select region of the first gate insulating layer, and both ends of the second gate insulating layer are included. The flash memory device includes a flash memory device including a first select line and a second select line.

Select Line, Device Isolation, Gate Insulation, Patterning, High Voltage Transistor

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a flash memory device for protecting an active region between select lines and a method of manufacturing the same.

The flash memory device includes a memory cell array that stores data. The memory cell array includes a plurality of strings, each string including memory cells, source select transistors and drain select transistors. It will be described in detail with reference to the following drawings.

1 is a plan view illustrating a flash memory device.

Referring to FIG. 1, a flash memory device includes a plurality of active regions ACT separated by an isolation layer ISO and electrically insulated from each other. Memory cells are connected to word lines WL to form a page. Select transistors are formed at both ends of the memory cells connected in series in the string, select transistors formed at the source terminal are connected to a source select line (SSL), and drain select transistors formed at the drain terminal are drain select line. line; DSL). In the figure the vicinity of the source is shown. In particular, since a subsequent contact plug is formed between the source select lines SSL1 and SSL2 20, the spacing between the source select lines SSL1 and SSL2 is the word line WL included in the string region 10. It is preferable to form wider than the interval between the interval between the word line WL and the source select line (SSL1 or SSL2).

Meanwhile, in the gate patterning process for forming the word line WL and the source select lines SSL1 and SSL2 (or the drain select lines), the etching rate is different depending on the interval of the exposed region, thereby forming a part of the active region. Can be exposed.

Specifically, the etching rate may be higher between the source select lines SSL1 and SSL2 than in the string region 10. Accordingly, a portion of the active region may be exposed between the string region 10 and the source select lines SSL1 and SSL2 20.

2A is a cross-sectional picture taken along the line A-A 'in FIG. 1, and FIG. 2B is a cross-sectional picture taken along the line B-B' in FIG. 1. In FIG. 2A, since the surface of the active region 21 is covered with the device isolation layer 22, the upper corner region 23 of the active region 21 is not exposed. However, in FIG. 2B, the upper corner region 23 of the active region may be exposed due to the high etching rate in the gate patterning process. When the active region is exposed, the adhesion to the contact plug to be subsequently formed may be degraded, thereby deteriorating electrical characteristics of the flash memory device.

The problem to be solved by the present invention is to form a thick gate insulating film formed between the select lines to prevent the exposure of the active region in the subsequent gate patterning process.

A flash memory device according to an embodiment of the present invention includes a first gate insulating layer formed on a semiconductor substrate. And a second gate insulating film formed on the select region of the first gate insulating film. A flash memory device includes a first select line and a second select line formed on the first gate insulating layer and the second gate insulating layer so that both ends of the second gate insulating layer are included.

One side of both ends of the second gate insulating layer is included in the middle of the first select line, and the other side is included in the middle of the second select line, and each of the first select line and the second select line is stepped by the second gate insulating layer. Is generated.

A flash memory device according to another embodiment of the present invention includes a first gate insulating layer formed on a semiconductor substrate. And a second gate insulating film formed on the select region of the first gate insulating film. The flash memory device includes a flash memory device including a first select line and a second select line formed on the second gate insulating layer.

The first select line and the second select line are formed to be parallel to each other, and the select region is the sum of the width of the first select line, the width of the second select line, and the width between the first select line and the second select line. Equal or wide

The select region does not overlap a word line neighboring each of the first select line and the second select line.

In the method of manufacturing a flash memory device according to an embodiment of the present invention, a first gate insulating layer is formed on a semiconductor substrate. A second gate insulating film is formed on the select region of the first gate insulating film. A first conductive film, a dielectric film, and a second conductive film are formed over the first gate insulating film and the second gate insulating film. And forming a first select line and a second select line by patterning the second conductive layer, the dielectric layer, and the first conductive layer such that both ends of the second gate insulating layer are included.

The second gate insulating film is simultaneously formed in the cell region and the peripheral circuit region of the semiconductor substrate. The second gate insulating film included in the cell region is formed to overlap a portion of the region where the first select line and the second select line are to be formed, and the second gate insulating film included in the peripheral circuit region is formed in the region where the high voltage transistor is to be formed. do. At this time, the second gate insulating film is formed of an oxide film.

The stacked thickness of the first gate insulating film and the second gate insulating film in the select region is formed to a thickness of 300 kPa to 500 kPa.

In a method of manufacturing a flash memory device according to another exemplary embodiment, a first gate insulating layer is formed on a semiconductor substrate. A second gate insulating film is formed on the select region of the first gate insulating film. A first conductive film, a dielectric film, and a second conductive film are formed over the first gate insulating film and the second gate insulating film. And forming a first select line and a second select line by patterning the second conductive film, the dielectric film, and the first conductive film so as to be included in the select region.

Each of the first select line and the second select line is formed so as not to contact the first gate insulating film.

The turn on voltage of the first select line or the second select line is equal to the turn on voltage of the high voltage transistor.

A voltage of 20V to 30V is applied to turn on transistors electrically connected to the first select line or the second select line.

According to an exemplary embodiment of the present invention, the gate insulating layer formed between the select lines is thickened to prevent exposure of the active region in a subsequent gate patterning process. By preventing the exposure of the active region, it is possible to suppress the occurrence of leakage current and to improve the adhesion of a subsequently formed layer, thereby preventing deterioration of electrical characteristics of the flash memory device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3A to 3G are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention, and FIGS. 4A to 4G illustrate a method of manufacturing a flash memory device according to an embodiment of the present invention. It is a plan view for. 3A to 3G are sectional views taken along the line AA ′ in FIGS. 4A to 4G.

3A and 4A, a first gate insulating layer 302 is formed on the semiconductor substrate 300. The first gate insulating film 302 may be formed of an oxide film. In this case, the oxide film in the region where the memory cell is to be formed is also called a tunnel insulating film, but for convenience of description, the oxide film is referred to as the first gate insulating film 302.

3B and 4B, a second gate insulating layer 304 is formed on the first gate insulating layer 302 in the region B where a subsequent select line is to be formed. For example, after the insulating film is formed on the first gate insulating film 302, a patterning process may be performed to form the second gate insulating film 304. In particular, the second gate insulating layer 304 may be simultaneously formed in the process of forming the gate insulating layer for the high voltage region (HVN region) of the peripheral circuit region. Accordingly, the thickness of the gate insulating film (first and second gate insulating films) of the select region C on which the second gate insulating film 304 is formed is preferably equal to the thickness of the gate insulating film of the high voltage region. For example, the stacking thickness of the first gate insulating film 302 and the second gate insulating film 304 may be formed to a thickness of 300 kPa to 500 kPa.

In addition, it is preferable that both ends of the second gate insulating layer 304 are included in the region B in which the select line to be subsequently formed is formed. Then, the select transistor can be operated even if the driving voltage applied to the subsequent select line is applied at the same voltage as the conventional one.

3C and 4C, the first conductive layer 306 for the floating gate is formed on the first gate insulating layer 302 and the second gate insulating layer 304. The first conductive film 306 may be formed of a polysilicon film. Specifically, the first conductive film 306 may be formed of a single layer film of a doped polysilicon film, or may be formed of a multilayer film in which doped and undoped polysilicon films are stacked.

3D and 4D, the device isolation mask pattern 308 is formed on the first conductive layer 306 to partition the device isolation region. The trench 300a is formed by etching the first conductive layer 306 and a part of the semiconductor substrate 300 according to the device isolation mask pattern 308.

3E and 4E, the device isolation layer 310 is filled in the trench 300a of FIG. 4D. The device isolation mask pattern (308 of FIG. 4D) is removed. Subsequently, an etching process for adjusting the effective field height (EFH) of the device isolation layer 310 is performed.

3F and 4F, a dielectric film 312, a second conductive film 314 for a control gate, a metal film 318, and gate patterning are disposed on the first conductive film 306 and the device isolation layer 310. A hard mask pattern 318 is formed for the process. The dielectric film 312 may be formed by stacking an oxide film, a nitride film, and an oxide film. The second conductive film 314 may be formed of a polysilicon film, for example, a doped polysilicon film. The metal film 318 may be formed of tungsten (W). In this case, a step may occur in an upper portion of both ends of the second gate insulating layer 304.

3G and 4G, the metal pattern 316a, the second conductive pattern 314a, the dielectric pattern 312a and the first conductive pattern 306a may be patterned according to the hard mask pattern 318. Form. In this case, the first conductive pattern 306a is in contact with a portion of the first gate insulating layer 302 and a portion of the second gate insulating layer 304. As a result, the word line WL and the source select line SSL or the drain select line DSL are formed. In the patterning process, a portion of the first gate insulating layer 302, the second gate insulating layer 304, or the device isolation layer 310 may be formed in regions other than the word line WL and the source (or drain) select line SSL or DSL. Exposed. In particular, since the spacing between the source (or drain) select lines SSL or DSL is wider than the spacing between the word lines WL, the etching rate may vary, but the first and second gate insulating layers 302 and 304 As a result, the exposure of the active region due to the difference in etching rates can be suppressed. Each area will be described with reference to the following drawings.

5A is a cross-sectional view taken along the line D-D 'of FIG. 4G, and FIG. 5B is a cross-sectional view taken along the line E-E' of FIG. 4G. The cross section in the D-D 'direction is a cross section between the word line WL and the source select line SSL, or a cross section between the word lines WL. The cross section in the E-E 'direction is a cross section between the source select lines SSL (or the drain select lines DSL). Referring to FIG. 5A, the first gate insulating layer 302 may be prevented from exposing the active region in a cross section along the D-D 'direction narrower than the interval between the source select lines SSL. Referring to FIG. 5B, in the cross section of the EE 'direction between the source select lines SSL, the first and second gate insulating layers 302 and 304 may be formed by the first and second gate insulating layers 302 and 304 even if the etching area is wider than the area of the DD' direction during the gate patterning process. Exposure of the active area can be prevented.

6 is a cross-sectional view of a flash memory device according to another exemplary embodiment.

Referring to FIG. 6, the second gate insulating layer 304 may be formed to have a wider width than the above-described embodiment. Specifically, both ends of the second gate insulating layer 304 may be formed to be exposed between the source select line SSL or DSL and the word line WL, respectively. In particular, since the gate insulating film of the source select line SSL or DSL is formed of the first and second gate insulating films 302 and 304, the thickness of the gate insulating film of the high voltage transistor HVN formed in the peripheral circuit region is the same. Accordingly, it is preferable to apply the turn on voltage of the select line SSL or DSL to the same voltage as the turn on voltage of the high voltage transistor. For example, the turn on voltage of the source select line SSL or DSL may be applied at 20V to 30V.

As described above, by preventing the exposure of the active region during the gate patterning process, it is possible to improve the adhesion between the contact plug and the active region to be formed later and to suppress the occurrence of leakage current, thereby preventing the deterioration of the electrical characteristics of the flash memory device. Can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a plan view illustrating a flash memory device.

FIG. 2A is a cross-sectional view taken along the line AA ′ in FIG. 1.

FIG. 2B is a cross-sectional photograph of the direction BB ′ in FIG. 1.

3A to 3G are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

4A to 4G are plan views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment.

5A and 5B are cross-sectional views between active regions in accordance with the present invention.

6 is a cross-sectional view of a flash memory device according to another exemplary embodiment.

<Explanation of symbols for the main parts of the drawings>

300: semiconductor substrate 302: first gate insulating film

304: second gate insulating film 306: first conductive film

308 device isolation mask pattern 310 device isolation layer

312 dielectric film 314 second conductive film

316: metal film 318: hard mask pattern

Claims (17)

A first gate insulating film formed on the semiconductor substrate; A second gate insulating film formed on the select region of the first gate insulating film; And And a first select line and a second select line formed on the first gate insulating layer and the second gate insulating layer such that both ends of the second gate insulating layer are included. The method of claim 1, One side of both ends of the second gate insulating layer is included in the middle of the first select line, the other side is included in the middle of the second select line. The method of claim 1, Each of the first select line and the second select line has a step difference caused by the second gate insulating film. A first gate insulating film formed on the semiconductor substrate; A second gate insulating film formed on the select region of the first gate insulating film; And And a first select line and a second select line formed on the second gate insulating layer. The method of claim 4, wherein And the first select line and the second select line are formed parallel to each other. The method of claim 4, wherein And the select region is equal to or wider than the sum of the width of the first select line, the width of the second select line, and the width between the first select line and the second select line. The method of claim 6, And the select region does not overlap a word line neighboring each of the first select line and the second select line. Forming a first gate insulating film on the semiconductor substrate; Forming a second gate insulating film on the select region of the first gate insulating film; Forming a first conductive layer, a dielectric layer, and a second conductive layer on the first gate insulating layer and the second gate insulating layer; And Forming a first select line and a second select line by patterning the second conductive layer, the dielectric layer, and the first conductive layer to include both ends of the second gate insulating layer, respectively. Way. The method of claim 8, And the second gate insulating layer is simultaneously formed in a cell region and a peripheral circuit region of the semiconductor substrate. The method of claim 9, And a second gate insulating layer included in the cell region so as to overlap a portion of a region where the first select line and the second select line are to be formed. The method of claim 9, And the second gate insulating layer included in the peripheral circuit region is formed in a region where a high voltage transistor is to be formed. The method of claim 8, And the second gate insulating film is formed of an oxide film. The method of claim 8, And a stacked thickness of the first gate insulating film and the second gate insulating film in the select region is 300 두께 to 500 Å. Forming a first gate insulating film on the semiconductor substrate; Forming a second gate insulating film on the select region of the first gate insulating film; Forming a first conductive layer, a dielectric layer, and a second conductive layer on the first gate insulating layer and the second gate insulating layer; And And patterning the second conductive film, the dielectric film, and the first conductive film so as to be included in the select region to form a first select line and a second select line. The method of claim 14, Wherein each of said first select line and said second select line is formed so as not to be in contact with said first gate insulating film. The method of claim 14, The turn on voltage of the first select line or the second select line is the same as the turn on voltage of the high voltage transistor. The method of claim 14, And applying a voltage of 20V to 30V to turn on transistors electrically connected to the first select line or the second select line.

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