KR100910288B1 - Method for driving plasma display panel - Google Patents

Abstract

In the driving method of the plasma display panel, it is possible to change the light emission in the erase discharge. A scan electrode driving circuit 3 for driving the scan electrode 112, a sustain electrode driving circuit 2 for driving the sustain electrode 111, an address electrode driving circuit 4 for driving the address electrode 121, In the method of driving a plasma display panel having a control circuit 5 for controlling the operation of each driving circuit, a reset period in which one field is divided into a plurality of subfields for operation, and each subfield adjusts the charge in a cell An address period for designating a cell to emit light, a sustain period for repeatedly discharging the scan electrode and the sustain electrode to emit light, and an erasing period for reducing the amount of wall charges formed in the light emitting cell at the end of the sustain period To drive each of the driving circuits, and select and apply at least two or more kinds of erase waveforms having different light emission amounts according to the driving scheme of the erase period. Randomly selects an erase waveform.

Subfield, erase discharge, sustain electrode driving circuit, scan electrode driving circuit, sustain period, control circuit

Description

Driving method of plasma display panel {METHOD FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an AC plasma display panel for use in display devices such as personal computers and workstations, flat televisions, and displays for displaying advertisements and information.

In the conventional three-electrode AC type color plasma display, there has been a period of erasing or reducing wall charges at the end of the sustain period (sustain period). Since this drive waveform follows the next reset period, there are limitations in polarity and the like. When the operation pulse applied to the scan electrodes is made negative, the number of discharges of the sustain, which is necessarily located between the scan period and the reset period, is either odd or even in all subfields SF. I had to.

As a driving method of such an AC type color plasma display, in a memory type AC plasma display having a dot matrix type and an address display separation method, at least two sets of electrodes for maintaining and erasing discharge, One to three thin-line erase pulses that discharge, but shorten the time to form a wall telephone, and sequentially apply two or three erase pulses of shorter pulse width and pulse interval to the two electrodes and erase pulses. It is proposed to gradually lower the potential of (see Patent Document 1, for example). In this example, however, no consideration was given to the polarity of the charge following the next reset.

Further, a plasma in which a plurality of X electrodes and a plurality of Y electrodes are arranged in parallel with each other, and each Y electrode is sandwiched between the X electrodes, and the plurality of address electrodes are arranged so as to intersect the X electrode and the Y electrode spaced apart from each other A driving method of a display panel, comprising: a first display step of performing display by discharge between each of the Y electrodes and one of the X electrodes adjacent to the respective X electrodes, the Y electrode and the respective Y electrodes; It is proposed to separate in time the second display step of performing display by discharge between adjacent X electrodes (see Patent Document 2, for example).

Patent Document 1: Japanese Patent No. 3372706

Patent Document 2: Japanese Patent No. 2801893

Problems to be Solved by the Invention

In the above-described conventional driving method, when the number of sustain discharges is changed, it is necessary to change the multiple times of 2, as the odd times for odd times and even times for even times. Could not express. In order to enable the number of times of sustain discharge including erasing, whichever is odd or even, it is necessary to reverse the polarity of the sustain electrode and the scan electrode in the reset period, and the circuit configuration becomes complicated and the cost increases. I have a problem.

According to the present invention, in the plasma display panel driving method and the plasma display device, the step of changing the luminance of the sustain discharge is made smaller by making the state of the charge before entering the subsequent reset equal and changing the amount of emitted light in the erase discharge. The purpose.

Means for solving the problem

In view of the above problems, the present invention intends to express intermediate brightness by changing the light emission amount of the erase discharge to equalize the charge state before the subsequent reset. This makes it possible to select an erase waveform having a large amount of light emission and an erase waveform having a small amount of light emission in each erasing period.

The present invention has a scan electrode and a sustain electrode arranged in parallel with the front substrate, and has a sustain period for repeatedly discharging the scan electrode and the sustain electrode to emit light, and a reset period for adjusting the amount of charge in the cell. And at the end of the sustaining period, in a plasma display having an erasing period for reducing the amount of wall charges formed in the light emitting cells, at least two or more kinds of erasing waveforms having different light emission levels can be selected by the driving method of the erasing period. This is to express the brightness of the middle.

That is, the present invention is formed between a scan electrode and a sustain electrode arranged in parallel with a front substrate, an address electrode disposed on a rear substrate in a direction orthogonal to the scan electrode and the sustain electrode, and formed between the front substrate and the rear substrate. A plasma display panel having a cell, a scan electrode driving circuit for driving the scan electrodes, a sustain electrode driving circuit for driving the sustain electrodes, an address electrode driving circuit for driving the address electrodes, and a control for controlling the operation of these driving circuits In the plasma display device having a circuit, the control circuit operates by dividing one field into a plurality of subfields, each subfield adjusting an amount of charge in a cell, an address period for designating a cell to emit light; A sustain period for repeatedly discharging at the scan electrode and sustain electrode to emit light of the cell; At the end of the sustain period, a circuit for driving the respective drive circuits as an erasing period for reducing the amount of wall charges formed in the light emitting cells, wherein the sustain electrode driving circuit and the scan electrode driving circuit are adapted to the driving method of the erasing period. Accordingly, at least two kinds of erase waveforms having different light emission amounts are selected, and an erase waveform is arbitrarily selected in the erase period of each subfield based on the control from the control circuit.

According to the present invention, in the plasma display device, a write process in which the scan electrode driving circuit gradually increases the voltage to the scan electrode in the reset period to generate discharge in all the cells to form wall charges, and the voltage gradually falls. The voltage is applied to have a reduction process for reducing the wall charges formed in the writing process, and the slope of the voltage waveform applied to the scan electrode by the waveform having the smallest light emission amount among the erase waveforms in the erase period and the reduction process. The obtuse waveform cancellation waveform was made with the same slope of the voltage waveform applied to the scan electrode. In the plasma display device, the sustain electrode driving circuit and the scan electrode driving circuit have a waveform having a larger amount of light emission among the erase waveforms in the erase period than the width of the sustain pulse repeatedly applied in the sustain period. It was set as a narrow thin line erase pulse. In the plasma display device, the sustain electrode driving circuit and the scan electrode driving circuit have a waveform having a larger amount of light emission among the erase waveforms in the erase period than the width of the sustain pulse repeatedly applied in the sustain period. A narrow thin line erase pulse is used, and the thin line erase pulse is changed in polarity and applied repeatedly one to several times, and the last polarity is always the same regardless of the number of repetitions.

According to the present invention, in the plasma display device, the sustain electrode driving circuit and the scan electrode driving circuit have a voltage lower than that of the sustain pulse which is repeatedly applied in the sustain period to a waveform having a large amount of light emission among the erase waveforms in the erase period. It was set as the erase pulse. In the plasma display device, the sustain electrode driving circuit and the scan electrode driving circuit have a voltage higher than that of the sustain pulse which is repeatedly applied in the sustain period to a waveform having a large amount of light emission among the erase waveforms in the erase period. The low self-erasing pulse is used to change the voltage difference between the scan electrode and the sustain electrode during the self-erasing discharge in accordance with the display load.

According to the present invention, in the plasma display device, the sustain electrode driving circuit and the scan electrode driving circuit have a voltage lower than that of the sustain pulse which is repeatedly applied in the sustain period to a waveform having a large amount of light emission among the erase waveforms in the erase period. As an erase pulse, the relative polarities of the scan electrodes and the sustain electrodes during the last discharge of the erase waveform in the erase period were the same in all erase waveforms.

According to the present invention, in the plasma display apparatus, the control circuit controls the number of times of light emission in accordance with the display load, and in the display load region in which the number of light emission is not reduced, the erase waveform in the erase period is converted into a waveform having a large amount of light emission. It was.

According to the present invention, a scan electrode and a sustain electrode disposed in parallel with the front substrate, an address electrode disposed in a direction orthogonal to the scan electrode and the sustain electrode on the rear substrate, and a cell formed between the front substrate and the rear substrate. A plasma display panel having a plasma display panel, a scan electrode driving circuit for driving the scan electrodes, a sustain electrode driving circuit for driving the sustain electrodes, an address electrode driving circuit for driving the address electrodes, and a control circuit for controlling the operation of these driving circuits. In a driving method of a plasma display panel having a field, a field is divided into a plurality of subfields, the reset period of each subfield adjusting the amount of charge in a cell, an address period for designating a cell to emit light, and the scan electrode And a sustain period for repeatedly discharging at the sustain electrode to emit light of the cell; At the end of the period, it is preferable to drive the driving circuit as an erasing period for reducing the amount of wall charges formed in the light-emitting cell, and to select and apply at least two or more kinds of erase waveforms having different light emission amounts according to the driving scheme of the erasing period. It is possible to select an erase waveform arbitrarily in the erase period of each subfield.

According to the present invention, in the method of driving the plasma display panel, the write process is applied to the scan electrode in the reset period, the voltage gradually rises to cause discharge in all the cells, and the voltage decreases gradually. A slope of a voltage waveform applied to the scan electrode by a waveform having a small amount of light emission among the erase waveforms in the erase period, and a voltage applied to the scan electrode in the decrease process; An obtuse-cancel waveform with approximately the same slope is set.

In the method of driving the plasma display panel, the thin line erase pulse is narrower than the width of the sustain pulse which is repeatedly applied in the sustain period in the waveform of the erase waveform in the erase period. In the method of driving the plasma display panel, the thin line erasing pulse is narrower than the width of the sustain pulse which is repeatedly applied in the sustaining period of the waveform having a large amount of light emission among the erasing waveforms in the erasing period. Was repeated a plurality of times by changing the polarity, and the last polarity was always the same regardless of the number of repetitions. According to the present invention, in the method of driving the plasma display panel, a waveform having a large amount of light emission among the erase waveforms in the erase period is a self-erase pulse having a lower voltage than the sustain pulse applied repeatedly in the sustain period. According to the present invention, in the method of driving the plasma display panel, a waveform having a large amount of light emitted from the erase waveform in the erase period is a self-erase pulse having a lower voltage than a sustain pulse applied repeatedly in a sustain period. The voltage difference between the scan electrode and the sustain electrode during the change was changed in accordance with the display load.

In the method of driving the plasma display panel, the relative polarities of the scan electrodes and the sustain electrodes during the last discharge of the erase waveform in the erase period are the same in all erase waveforms. In the method of driving the plasma display panel, in the display load region in which the number of light emission is controlled in accordance with the display load and the number of light emission is not reduced, the erase waveform in the erase period is a waveform having a large amount of light emission.

Effect of the Invention

According to the present invention, it is possible to perform stable driving after changing the light emission amount of erase discharge by maintaining the luminance ratio of each subfield at a predetermined value without significantly changing the wall phone state before the reset period.

1 is a conceptual diagram showing a subfield configuration of the present invention.

2 is an exploded perspective view illustrating the structure of the PDP panel of the present invention.

Fig. 3 is a view for explaining the PDP panel main body 1 and the circuit configuration of the present invention.

Fig. 4 is a waveform diagram showing an example of drive waveforms in the first embodiment of the present invention.

5 is a waveform diagram showing an example of drive waveforms in a second embodiment of the present invention;

6 is a diagram illustrating a relationship between load factor, brightness, and power.

Fig. 7 is a waveform diagram showing an example of drive waveforms in the third embodiment of the present invention (an example in which there are a plurality of erase pulses).

<Description of the code>

1: PDP panel body

11: front glass plate

111: X electrode

112: Y electrode

113: dielectric layer

114: protective layer

12: back glass plate

121: address electrode

122: dielectric layer

123: bulkhead

124R, G, B: phosphor

2: X driving circuit

3: Y driving circuit

4: address driving circuit

51: write blunt wave

52: Y Compensation Blunt

41: X write voltage

42: X compensation voltage

43: X voltage

44, 54: first sustain pulse

45, 46, 55, 56: holding pulse

47, 57: erase pulse

48, 49, 50, 58, 59, 60: thin line erase pulse

77: erase blunt wave

87, 88, 89, 90: erase discharge with large discharge amount

97: erase discharge with low discharge amount

SF1 to SF10: subfields

RP: Reset period

AP: address period

SP: retention period

CP1, CP2: erasing period

<Embodiment of the invention>

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described using FIG. 2 is an exploded perspective view showing an example of the structure of the PDP panel main body 1 according to the present invention. On the front glass plate 11, the sustain electrode 111 and the scan electrode 112 which discharge repeatedly are alternately arranged in parallel. This electrode group is covered with a dielectric layer 113, and its surface is covered with a protective layer 114 such as MgO. In the rear glass plate 12, the address electrode 121 is disposed in a direction substantially orthogonal to the sustain electrode 111 and the scan electrode 112, and is covered with the dielectric layer 122. The partition walls 123 are disposed on both sides of the address electrode 121 to distinguish cells in the column direction. In addition, phosphors 124R, 124G, which are excited by ultraviolet rays and generate visible light of red (R), green (G), and blue (B) on the side surfaces of the dielectric layer 122 and the partition wall 123 on the address electrode 121, 124B) is applied. The front glass plate 11 and the rear glass plate 12 are joined to be in contact with the protective layer 114 and the partition wall 123, and a discharge gas such as Ne-Xe is sealed to form a panel.

Next, the structure of the PDP module of this invention is demonstrated using FIG. This figure shows the PDP panel main body 1 and the driving circuit which are formed by joining the front glass plate 11 and the back glass plate 12 together. In FIG. 3, the PDP module includes a PDP panel main body 1, an X driving circuit (sustaining electrode driving circuit) 2, a Y driving circuit (scanning electrode driving circuit) 3, and an address driving circuit 4. And a control circuit 5 and a power supply 6. The sustain electrode 111, the scan electrode 112, and the address electrode 121 of the PDP panel main body 1 are connected to the X driving circuit 2, the Y driving circuit 3, and the address driving circuit 4, respectively. have.

The X driving circuit 2 and the Y driving circuit 3 each have at least two or more kinds of erase waveforms in which the light emission amounts are different depending on the driving scheme of the erasing period, and the subfields of each subfield are based on the control from the control circuit. The erase waveform is arbitrarily selected in the erase period, and a thin line erase pulse narrower than the width of the sustain pulse which is repeatedly applied in the sustain period is applied to the waveform having the large amount of light emission among the erase waveforms in the erase period. In addition, the X drive circuit 2 and the Y drive circuit 3 use a thin line erase pulse that is narrower than the width of the sustain pulse that is repeatedly applied in the sustain period to a waveform having a large amount of light emission among the erase waveforms in the erase period. The erase pulse is repeatedly applied once or by changing the polarity, and outputted so that the last polarity is always the same regardless of the number of repetitions.

The X driving circuit 2 and the Y driving circuit 3 output a self-clearing pulse having a voltage lower than that of the sustain pulse which is repeatedly applied in the sustain period to the waveform having a large amount of light emission among the erase waveforms in the erase period. The voltage difference between the scan electrode 112 and the sustain electrode 111 at the time of erasing discharge is varied in accordance with the display load and output. In addition, the X driving circuit 2 and the Y driving circuit 3 use a waveform having a large amount of light emission among the erase waveforms in the erase period as a self-erase pulse having a lower voltage than the sustain pulse applied repeatedly in the sustain period. The relative polarities of the scan electrodes and sustain electrodes at the time of the last discharge of the erase waveform in E2 are output to be the same in any erase waveform.

The X driving circuit 2 applies the X obtuse wave or the X compensation voltage to the X electrode (holding electrode) in the reset period described later, and in the erasing period, a plurality of schemes having different pulse widths or pulse amplitudes. It is possible to output an erase pulse, so that the intensity of discharge light emission in the erase period can be different.

The Y driving circuit 3 applies the Y obtuse voltage or the Y compensated obtuse wave to the Y electrode (scanning electrode) in the reset period described later, applies a scan pulse in the address period, and pulses in the erase period. It is possible to output plural erase pulses or Y erase blunt waves having different widths or pulse amplitudes, so that the intensity of discharge light emission in the erase period can be different.

In the Y driving circuit 3, a write step in which the voltage gradually rises to the scan electrodes 112 in the reset period to generate discharge in all the cells to form wall charges, and the voltage gradually decreases to form the write step. The voltage is applied to have a reduction process for reducing wall charge, and the slope of the voltage waveform applied to the scan electrode by the waveform having the smallest light emission amount among the erase waveforms in the erase period is applied to the scan electrode 112 in the reduction process. An obtuse-cancel waveform with approximately the same slope as the voltage waveform is output.

The address driving circuit 4 applies an address pulse to the address electrode 121 in an address period described later.

The control circuit 5 controls the X driving circuit 2, the Y driving circuit 3, and the address driving circuit 4 at a predetermined timing, and for example, controls the voltages shown in FIGS. 4 and 5. Control to apply. That is, the control circuit 5 operates the division by dividing one field into a plurality of subfields, each subfield adjusting a charge amount in a cell, an address period for designating a light emitting cell, And a circuit for driving each drive circuit in a sustain period for repeatedly discharging the scan electrode and the sustain electrode to emit light of the cell, and an erasing period for reducing the amount of wall charges formed in the cell that emits light at the end of the sustain period. to be. The control circuit 5 controls the number of light emission in accordance with the display load, and controls the erase waveform in the erasing period to be a waveform having a large amount of light emission in the display load area in which the number of light emission is not reduced.

Next, an example of the driving method when displaying a picture of one image (one field: 1/60 sec) in the address / display separation method will be described using the schematic diagram of FIG. 1. One field is composed of a plurality of subfields (10 subfields SF1 to SF10 in this example) (Fig. 1 (a)). Each subfield consists of an erasing period CP1 or CP2 in which the reset period RP, the address period AP, the sustain period SP, and the light emission amount are different (Fig. 1 (b) and (c)). In the reset period RP, the charges in the cell are rearranged for the purpose of assisting the discharge of the address period AP subsequent thereto. In the address period AP, there are a method of forming a charge in a light emitting cell by performing a discharge to determine a cell to emit light, and a method of erasing the charge in a non-light emitting cell. In this embodiment, a charge is formed in a light emitting cell. In addition, since the present invention relates to the erasing period of sustain discharge, the address may be a method of erasing charges of non-light emitting cells.

In subsequent sustain period SP, discharge is repeatedly performed to emit light of the cell. Subsequent erasure periods CP1 and CP2 are the present invention, which erases or reduces the wall charges formed in the sustain period SP.

4, an example of a drive waveform is demonstrated. (a) to (g) are driving waveforms applied to the sustain electrode 111, the scan electrode 112, and the address electrode 121 to the erase period CP from the reset period RP, respectively, and discharge at that time. The light emission is shown. (a) and (d) are sustain electrodes, (b) and (e) are voltage waveforms applied to the scan electrodes, (c) and (f) are discharge light emission, and (g) are voltage waveforms applied to the address electrodes. .

First, the Y write obtuse wave 51 and the X voltage 41 are applied to the sustain electrodes 111 and the scan electrodes 112 of (a) and (b) to form electric charges in all cells in the reset period RP. Also subsequently applied is an Y compensation blunt wave 52 and an X compensation voltage 42 which erases the necessary amount of charge formed in the cell.

The voltage waveform applied in the next address period AP includes a scan pulse 53 for performing a discharge for determining a cell to be displayed in timing with the address pulse 100 for each row, and an X for forming wall charges by the present discharge. Voltage 43. The scan pulse 53 is applied with the timing shifted from row to row.

Subsequently, the first sustain pulses 44 and 54 and the repeat sustain pulses 45, 46, 55 and 56 are applied to the sustain period SP.

In the erasing period CP, the erasing pulses 47 and 57 are applied. In the erase waveform of this example, the erase pulse 47 has a lower voltage than the sustain pulse 45, and the discharge amount is slightly smaller than the sustain discharge, but the amount of wall charges is reduced by the low voltage. This discharge is sometimes called a self-erasing discharge. (g) is a waveform applied to the address electrode. In the cell to be discharged, the address pulse 100 is applied in accordance with the scan pulse 53.

(c) shows light emission of the cells discharged with the voltage waveforms of (a), (b) and (g). In addition, this light emission is not light emission of fluorescent substance but infrared light (or ultraviolet light) which emits light when an excitation atom returns to a ground state with discharge. In the reset period, the weak write discharge 81 is generated by the Y write blunt wave 51. In addition, in the Y-compensated blunt wave 52, the weak discharge 82 also occurs. In the waveform in which the voltage is gradually changed in this manner, the discharge is weak and the amount of light emitted is small. Therefore, the light emitted by the phosphor excited by the ultraviolet light is also less.

Subsequently, in the address period AP, the address discharge 83 is generated by the scan pulse 53 and the address pulse 100. In the sustain period SP, sustain discharges 84, 85 and 86 are generated, followed by erase discharges 87. This erase discharge 87 has a slightly smaller discharge amount than the sustain discharge, but corresponds to one light emission amount of the sustain discharge. In this discharge, positive wall charges are formed near the scan electrode and negative wall charges are formed near the sustain electrode.

Next, (d) and (e) are cases where an erase waveform of different amounts of light emission is applied to the erase period CP. The driving waveforms of the reset period RP, the address period AP, and the sustain period SP except for the erase period CP are as shown in (a) and (b), and description thereof is omitted. In the erase waveform of this example, an erase obtuse wave 77 similar to the Y compensation obtuse wave 52 applied to the scan electrode 112 is applied to the scan electrode 112 in the reset period RP. At this time, the voltage 67 applied to the sustain electrode 111 is set higher than the voltage 42 applied to the reset period RP.

(f) shows light emission of the cells discharged with the voltage waveforms of (d), (e) and (g), and the same discharge as in (c) will be omitted. The erase discharge of this system is a weak discharge 97, and the amount of light emitted by the discharge is about 1/10 of the amount of light emitted by one sustain discharge. In this discharge, positive wall charges are formed near the scan electrode and negative wall charges are formed near the sustain electrode.

As apparent from the comparison of the light emission shown in (c) and (f) above, the number of sustain discharges including the erase discharge is the same, but the amount of light emission is almost the same as that of the sustain discharge. By selecting, the amount of light emitted in each subfield can be adjusted. In addition, in either erase waveform, the wall charge after the erase discharge is in a similar state, and there is no need to change the subsequent reset waveform.

Next, 2nd Embodiment is described with reference to FIG. In the second embodiment, the erasing waveforms shown in (a) and (b) are different from the first embodiment shown in FIG. 4, except for the same reference numerals as in FIG. 4, and the description thereof is omitted. The erase waveform in this embodiment is a so-called thin line erase waveform, which discharges at the same voltage as the sustain pulse, but reduces the amount of wall charges formed by the thin line erase pulses 48 and 58 whose pulse width is shortened. . In this case, the light emission amount is the same as the light emission amount of sustain discharge as shown in (c). Also in this discharge, positive wall charges are formed in the vicinity of the scan electrode and negative wall charges are formed in the vicinity of the sustain electrode, which is the same as in the first embodiment.

Next, 3rd Embodiment is described with reference to FIG. In the third embodiment, the erasing waveforms shown in (a) and (b) are different from the second embodiment shown in FIG. 5, except for the same reference numerals as in FIG. 5, and the description is omitted. The erase waveform in the present embodiment is a so-called thin line erase waveform, and the discharge amount is formed at the same voltage as the sustain pulse, but the amount of wall charges is formed by the thin line erase pulses 49, 59, 50, and 60 which are sequentially shortened. Will be less. In this case, the light emission amount is the same as the light emission amount of sustain discharge as shown in (c). In this example, the sustain pulse immediately before the erase pulse shown in FIG. 5 is replaced with a thin line erase pulse, and the number of discharges is the same. Also in this erase discharge, after the last erase discharge, positive wall charges are formed in the vicinity of the scan electrode and negative wall charges are formed in the vicinity of the sustain electrode, which is the same as in the first embodiment.

6, the relationship between display load factor, power, and luminance in the plasma display will be described. In general, a control is performed to reduce the number of sustain pulses so that the power is kept below a predetermined value when the load ratio is increased. In this case, since no control is applied to the number of sustain pulses on the low load region side, the luminance ratio of each subfield is a predetermined value. Therefore, in this region, it is preferable to select an erase waveform having high luminance. In the power control region that controls the number of sustain pulses, since the number of discharges is changed twice, it is difficult to necessarily maintain the luminance ratio of each subfield. As in this embodiment, the luminance for one discharge is selected by selecting the erase waveform. By adjusting, the luminance ratio of each subfield can be maintained at a predetermined value.

Claims (16)

A plasma display panel having a scan electrode and a sustain electrode arranged in parallel to a front substrate, an address electrode disposed in a direction perpendicular to the scan electrode and the sustain electrode on a rear substrate, and a cell formed between the front substrate and the rear substrate And a scan electrode drive circuit for driving the scan electrodes, a sustain electrode drive circuit for driving the sustain electrodes, an address electrode drive circuit for driving the address electrodes, and a control circuit for controlling the operation of these drive circuits. As a driving method of Operation by dividing one field into a plurality of subfields, A reset period in which each subfield adjusts the amount of charge in the cell, an address period for designating a cell to emit light, a sustain period for repeatedly discharging the scan electrode and the sustain electrode to emit light of the cell, and a cell formed in the light emitting cell Driving each driving circuit with an erasing period for reducing the amount of wall charge, The erase period is between the sustain period and the reset period subsequent to the sustain period, In the erasing period, whether the scan electrode is to apply a first erasing waveform consisting of a square wave pulse of a potential at which the scan electrode becomes a cathode to the sustain electrode is applied to at least one of the sustain electrode and the scan electrode, or the scan electrode For each subfield, one of the subfields is selected to apply a second erasing waveform to the scan electrode which is a cathode with respect to the sustain electrode and whose voltage value of the scan electrode decreases with time, and whose discharge emission amount is smaller than that of the first erasing waveform. And a plasma display panel driving method. The method of claim 1, A writing process applied to the scan electrode in the reset period to gradually increase the voltage to cause discharge in all the cells to form wall charges, and a reduction process of gradually decreasing the voltage to reduce the wall charges formed in the writing process; Have, In the erase period, the second erase waveform has the same slope as the slope of the voltage waveform applied to the scan electrode in the reduction process. The method according to claim 1 or 2, The first erase waveform is a pulse whose potential difference between the electrodes of the sustain electrode and the scan electrode is smaller than the sustain discharge pulse applied in the sustain period or is a pulse whose application time is shorter than the sustain discharge pulse. A method of driving a plasma display panel. delete delete delete delete delete delete delete delete delete delete delete delete delete

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