KR100888123B1 - Memory circuit - Google Patents

Abstract

The present invention includes a memory circuit. In one embodiment, the memory circuit includes a memory array including a plurality of memory cell capacitors. Each capacitor includes a memory node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is shared between, or a portion of, a plurality of memory cell capacitors in the memory array. The cell electrode in the memory array includes a conductive metal layer comprising one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. Polysilicon is received over the conductive metal layer. A conductive metal layer and polysilicon are accommodated on the memory node electrodes of, or a portion of, a plurality of memory cell capacitors. Other embodiments and aspects are possible.

Description

Memory circuits {MEMORY CIRCUITRY}

The present invention relates to a memory circuit.

There are many kinds of memory integrated circuits. Some of these circuits house multiple memory cell capacitors in a memory array. Each capacitor includes a memory node electrode, a cell electrode, and a capacitor dielectric region between the two. Furthermore, in some memory circuits, cell electrodes are shared between capacitors in the memory array. One example is a DRAM of this conventional type of memory circuit. Irrespective of this, fabricated memory cell capacitors may take various forms, for example, stacked, trenched, planar, or the like. It may also have capacitor storage nodes in the form of a container or cup.

Conventional memory cell capacitor structures form memory node electrodes of titanium nitride, where the capacitor dielectric region comprises one or a combination of aluminum oxide and hafnium oxide. The remaining cell electrodes are formed of three materials, specifically, a titanium nitride layer contained in the capacitor dielectric region, a conductive-doped polysilicon contained in the titanium nitride, and a tungsten contained in the conductive-doped polysilicon. It is formed of silicide. Titanium nitride is used due to the high step coverage of the deposition process leading up to the container openings and can provide excellent adhesion and barrier layers to the doped silicate glass. It is common for memory node container holes to be formed in the silicate glass. Polysilicon also provides excellent compliant step coverage during deposition and also acts as an oxide barrier layer. Moreover, it is common for conductive cell electrode layers to be used to fabricate other conductive components or portions of conductive components in a circuit around a memory array. Polysilicon of these components provides a good etch stop function for etching contacts to such conductive materials in the circuits around the memory array. Tungsten silicide is used superior to polysilicon because of its excellent electrical conductivity compared to conductive-doped polysilicon. Tungsten silicides are typically physical vapor deposited.

A typical known memory cell capacitor structure forms titanium nitride of the cell electrode in the form of a continuous layer that forms all the trenches in a line over the capacitor dielectric region. The conductive-doped polysilicon layer then completely fills the remaining space of the container and is interconnected with all the containers of the array. A tungsten silicide layer is received thereon and thus is not formed in the container. One or more conductive contacts for this cell plate layer are made outside of the memory array, providing a cell electrode at a common potential across the array.

When using aluminum / hafnium oxide, there was a tendency to limit the temperature at which the substrate is exposed. Specifically, the typical maximum temperature limit is 700 degrees Celsius. Borophosphosilicate glass (BPSG) is a typical interlayer / interlevel dielectric, typically deposited before or after deposition of aluminum oxide or hanium oxide. The BPSG is typically heat treated after deposition and annealed in a furnace. This is typically done at 800 degrees Celsius or more. This high temperature treatment activates the conductivity improving impurity dopants in the polysilicon, thereby increasing the electrical conductivity of the doped polysilicon. However, due to the current 700 degree Celsius temperature limit after deposition of aluminum oxide or hafnium oxide, BPSG is deposited without furnace annealing or rapid thermal annealing. Accordingly, the degree of dopant activation of the polysilicon does not reach the desired level, and eventually the resistance of the polysilicon is higher than the desired value.

The present invention includes a memory circuit. In one embodiment, the memory circuit includes a memory array including a plurality of memory cell capacitors. Each capacitor includes a memory node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is shared between, or a portion of, a plurality of memory cell capacitors in the memory array. The cell electrode in the memory array includes a conductive metal layer comprising one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. Polysilicon is received over the conductive metal layer. A conductive metal layer and polysilicon are accommodated on the memory node electrodes of, or a portion of, a plurality of memory cell capacitors.

Other embodiments and aspects are possible.

1 is a plan view of a portion of a semiconductor wafer in accordance with the present invention.

2 is a cross-sectional view taken along line 2-2 of FIG.

3 is an alternative embodiment view of the figure shown in FIG. 2;

A preferred embodiment memory circuit, such as a DRAM circuit, is described with reference to FIGS. At this time, the semiconductor substrate 10 is shown. Substrate 10 includes bulk monocrystalline silicon 12, in which trench isolation regions 14 are formed. Of course, alternative semiconductor substrates (eg, semiconductor-on-insulator, existing or future substrates, etc.) may be considered.

The illustrated memory circuit represents two memory cells of a DRAM circuit, in particular a buried digitline DRAM circuit. However, if a memory array including a plurality of memory cell capacitors is included, any memory circuit can be considered, whether existing or future. Substrate 10 shows a portion of memory array 15 that includes a plurality of capacitors. At this time, two capacitors 16 and 18 are shown. A pair of word lines 20, 22 are shown to be contained within the semiconductor material 12. For example, it may be a gate dielectric layer 24, a conductive-doped polysilicon layer 26 contained thereon, a more conductive, refractory metal or refractory metal silicide layer 28 contained thereon, and the insulation contained thereon. Cap 30 (ie, silicon nitride). Anisotropically etched sidewall spacers 32 are shown to insulate the sidewalls of the wordlines 20, 22. Conductive diffusion regions 34, 36, 38 are provided in the semiconductor material 12 (ie the bulk single crystal silicon substrate) 12. Diffusion region 36 is accommodated between word lines 20 and 22 to form shared bit nodes / junctions for the two memory cells. Diffusion regions 34 and 38 are housed outwardly to the side of word lines 20 and 22 and constitute memory node junctions for both memory cells.

One or more insulating materials 40 are formed over the substrate 12 (including wordlines 20, 22). One preferred material is silicon dioxide, the most preferred being insulating silicate glass such as BPSG or PSG. In the example shown, material 40 may be one material or may be a variety of materials, typically deposited in several steps. Conductive contacts or plugs 42, 43, 44 are received in the material 40 and extend into the diffusion regions 34, 36, 38. It may include one or more conductive materials such as conductively-doped polysilicon, titanium nitride, and titanium silicide. The materials of the plugs 42, 43, 44 may be the same or different. For example, plugs 42, 43, 44 may be formed in contact holes after depositing undoped silicon dioxide followed by deposition of BPSG. 1 and 2 also show embedded digit lines 46 for an example memory circuit.

Individual capacitors 16, 18 are shown to include memory node electrodes 48, capacitor dielectric regions 50, and cell electrodes 52. Cell electrode 52 is shared between, or a portion of, a plurality of memory cell capacitors in a memory array. FIG. 2 shows how the cell electrode 52 is shared by the memory cell capacitors 16 and 18 in the memory array 15.

One preferred memory node electrode material is a conductive metal nitride, such as titanium nitride. Such electrodes may comprise, for example, conductive metal nitrides, or comprise them as a main component, or consist only of metal nitrides. For example, alternative conductive metal nitrides include tungsten nitride, titanium boron nitride, and tantalum nitride. One preferred thickness range for memory node 48 is 50 to 100 angstroms. In a preferred embodiment, the memory node electrode 48 takes the form of a container. Additionally in one preferred embodiment, these containerized memory node electrodes are housed in a container aperture formed in an insulating silicate glass, such as material 40.

Ele's preferred capacitor dielectric region 50 includes one or more of aluminum oxide and hafnium oxide. For example, further preferred embodiments include tantalum oxide, tantalate, titanates such as barium strontium titanate, and oxide-nitride-oxide (ONO) materials.

In a preferred embodiment, cell electrode 52 includes conductive metal nitride layer 54 and conductive metal layer 56. The conductive metal layer 56 includes one or more of tungsten element, tungsten alloy, tungsten silicide, and tungsten nitride. The conductive metal layer has a different composition than the conductive metal nitride layer 54. An example tungsten alloy is titanium-tungsten. In the example shown, conductive metal layer 56 is received over conductive metal nitride layer 54. However, in some embodiments, a conductive metal nitride layer 54 may be received over the conductive metal layer.

Exemplary preferred conductive metal nitride layers are as described above in connection with preferred memory node materials. The preferred thickness range of conductive metal nitride layer 54 is 100-300 angstroms, with 200 angstroms thickness being most preferred in certain preferred examples.

The conductive metal layer 56 may be received over each of the memory node electrodes 48 of the plurality of memory cell capacitors. Alternatively, conductive metal layer 56 may be received only over a portion of each of memory node electrodes 48 of capacitors 16 and 18. For example, the conductive metal layer 56 is shown not to be received above the central portion 60 of the storage node 48 in the bottom portion of the container form shown. If further preferred, a conductive metal nitride layer 54 is received over each of the memory node electrodes 48 of, or a portion of, a plurality of memory cell capacitors. At this time, the layer 54 is shown to be housed above the memory node electrodes 48 of the capacitors 16, 18. One preferred thickness range for conductive metal layer 56 is 100-1000 angstroms.

In the preferred embodiment shown, polysilicon 62 is received over conductive metal nitride layer 54 and conductive metal layer 56. At this time, the conductive metal nitride layer 54, the conductive metal layer 56, and the polysilicon 62 are accommodated on the memory node electrodes 48 of the memory cell capacitors 16 and 18. Additionally in one preferred embodiment, when the conductive metal layer 56 is received over the conductive metal nitride layer 54, the polysilicon 62 is tungsten element, tungsten alloy, tungsten silicide, or tungsten nitrate of the conductive metal layer 56. It is housed on one of the rides. In addition, in the illustrated embodiment, polysilicon 62 is received over conductive metal nitride layer 54, particularly when conductive metal layer 56 is only received over each portion of memory node electrodes 48. When the conductive metal layer 56 is accommodated on each of the memory node electrodes 48 of the plurality of memory cell capacitors, the polysilicon 62 may only be accommodated on either the conductive metal nitride layer or the conductive metal layer. The preferred thickness range of one example of polysilicon 62 is 50-600 angstroms, and it is desirable to fill the remaining space of the storage node container shapes shown. In the illustrated embodiment, the polysilicon 62 is preferably laterally co-extensive laterally with the conductive metal nitride layer 54 in the memory array 15, as shown in FIG. Do.

Polysilicon 62 may be conductively-doped with conductivity improving impurities. For example, polysilicon 62 may include an electrical conductor of the cell electrode. Alternatively, the polysilicon may be doped with insufficient conductivity improving impurities to effectively conduct the polysilicon to include the conductive portion of the cell electrode, in one embodiment not conductive-doped with conductivity-improving impurities. It may be.

The present invention also contemplates polysilicon received on conductive metal layer 56 (whether or not it is housed on each individual memory node electrode), whether or not conductive metal nitride layer 54 is present. However, the embodiment of FIG. 2 is preferred where such a conductive metal nitride layer 54 is present and the conductive metal layer 56 is received over the layer 54.

As a further example, the present invention contemplates a conductive metal layer comprising two or more of tungsten element, tungsten alloy, tungsten silicide, and tungsten nitride. Of course, two, three, four, and so on. For example, FIG. 3 shows an alternative semiconductor wafer 10a. 3 shows a cell electrode 52a comprising a conductive metal layer 56a composed of two layers 55, 57. In this case, the conductive metal layer 56a includes two or more of tungsten element, tungsten alloy, tungsten silicide, and tungsten nitride. Other preferred examples are as mentioned above, and three or four such layers may be used.

The use of known techniques and polysilicon herein is known to reduce dielectric leakage, and polysilicon is believed to act as a stress buffer and block the oxidation of titanium nitride and tungsten silicide during the capacitor formation process.

Claims (62)

delete delete delete delete delete A memory circuit comprising a memory array, the memory circuit comprising: The memory array includes a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is disposed between the plurality of memory cell capacitors in the memory array, Shared between or parts thereof, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, the polysilicon not including a conductive portion of the cell electrode, And the conductive metal layer comprises two or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. delete A memory circuit comprising a memory array, the memory circuit comprising: The memory array includes a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is disposed between the plurality of memory cell capacitors in the memory array, Shared between or parts thereof, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, the polysilicon not including a conductive portion of the cell electrode, And wherein said polysilicon is not conductively doped with conductivity enhancing impurity. delete delete A memory circuit comprising a memory array, the memory circuit comprising: The memory array includes a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is disposed between the plurality of memory cell capacitors in the memory array, Shared between or parts thereof, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, the polysilicon not including a conductive portion of the cell electrode, And the capacitor dielectric region comprises at least one of aluminum oxide or hafnium oxide. A memory circuit comprising a memory array, the memory circuit comprising: The memory array includes a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is disposed between the plurality of memory cell capacitors in the memory array, Shared between or parts thereof, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, the polysilicon not including a conductive portion of the cell electrode, And the cell electrode includes a conductive metal nitride in addition to the conductive metal layer, wherein the conductive metal nitride has a different composition from the conductive metal layer. 13. The memory circuit of claim 12 wherein the polysilicon is received on a conductive metal nitride. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Shared between the parts, The cell electrode in the memory array comprises a conductive metal layer comprising one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, the cell electrode comprising conductive metal nitride in addition to the conductive metal layer; The conductive metal nitride has a different composition from the conductive metal layer, Polysilicon is received over the conductive metal layer and over the conductive metal nitride, the conductive material layer and the polysilicon are received over memory node electrodes, or a portion of a plurality of memory cell capacitors, wherein the polysilicon is: And at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride of the conductive metal layer and the conductive metal nitride. 15. The memory circuit of claim 14 wherein the polysilicon extends laterally equally to the conductive metal nitride in the memory array. A memory circuit comprising a memory array, the memory circuit comprising: The memory array includes a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is disposed between the plurality of memory cell capacitors in the memory array, Shared between or parts thereof, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, the polysilicon not including a conductive portion of the cell electrode, The memory node electrodes comprise a conductive metal nitride, And the capacitor dielectric region comprises at least one of aluminum oxide or hafnium oxide. delete A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Shared between the parts, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, the conductive metal layer being received only over a portion of each of the memory node electrodes of, or a portion of, a plurality of memory cell capacitors. Memory circuit. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Shared between the parts, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, Memory node electrodes of, or a portion of, the plurality of memory cell capacitors take the form of a container, And a conductive metal layer is received only on a portion of each of the plurality of memory cell capacitors, or part thereof, of the container form of the memory node electrodes. A memory circuit comprising a memory array, the memory circuit comprising: The memory array includes a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is disposed between the plurality of memory cell capacitors in the memory array, Shared between or parts thereof, The cell electrode in the memory array comprises a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein polysilicon is received on the conductive metal layer, and a plurality of memory cell capacitors, or The conductive metal layer and polysilicon are received over a portion of the memory node electrodes, the polysilicon not including a conductive portion of the cell electrode, The memory node electrodes of, or a portion of, a plurality of memory cell capacitors take the form of a container, And the polysilicon fills the remaining space in the container form. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Between the parts, shared, The cell electrode in the memory array comprises a conductive metal nitride layer and a conductive metal layer, wherein the conductive metal layer comprises one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein the composition of the conductive metal layer is Different from the composition of the conductive metal nitride layer, Polysilicon is received over the conductive metal nitride layer and the conductive metal layer, wherein the conductive metal nitride layer, the conductive metal layer, and the polysilicon are over memory node electrodes of, or a portion of, a plurality of memory cell capacitors. And wherein the polysilicon does not comprise a conductive portion of the cell electrode. 22. The memory circuit of claim 21 wherein the polysilicon extends laterally equally to the conductive metal nitride layer in the memory array. 22. The memory circuit of claim 21 wherein the conductive metal layer is received over a conductive metal nitride layer. 24. The memory circuit of claim 23 wherein the conductive metal layer is received directly above the conductive metal nitride layer. 22. The memory circuit of claim 21 wherein the conductive metal nitride layer is received over the conductive metal layer. 27. The memory circuit of claim 25 wherein the conductive metal nitride layer is received directly above the conductive metal layer. The method of claim 21, wherein the polysilicon is accommodated on at least one of the following a) or b), wherein a) is a conductive metal nitride layer, b) is a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. 28. The memory circuit of claim 27 wherein the polysilicon is received over a conductive metal nitride layer. 28. The memory circuit of claim 27 wherein the polysilicon is received on at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride of the conductive metal layer. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Between the parts, shared, The cell electrode in the memory array comprises a conductive metal nitride layer and a conductive metal layer, wherein the conductive metal layer comprises one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein the composition of the conductive metal layer is Different from the composition of the conductive metal nitride layer, Polysilicon is received over the conductive metal nitride layer and the conductive metal layer, wherein the conductive metal nitride layer, the conductive metal layer, and the polysilicon are over memory node electrodes of, or a portion of, a plurality of memory cell capacitors. Are accepted, The polysilicon is accommodated above a) and b), wherein a) is a conductive metal nitride layer, b) is a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. The method of claim 21, wherein the polysilicon is accommodated above a) or b), wherein a) is a conductive metal nitride layer, b) is a conductive metal layer comprising at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. 32. The memory circuit of claim 31 wherein the polysilicon is received over the conductive metal nitride layer. 32. The memory circuit of claim 31 wherein the polysilicon is received over one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride of the conductive metal layer. 22. The memory circuit of claim 21 wherein the conductive metal layer comprises a tungsten element. 22. The memory circuit of claim 21 wherein the conductive metal layer comprises tungsten silicide. 22. The memory circuit of claim 21 wherein the conductive metal layer comprises tungsten nitride. 22. The memory circuit of claim 21 wherein the conductive metal layer comprises a tungsten alloy. 22. The memory circuit of claim 21 wherein the conductive metal layer comprises two or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. delete 22. The memory circuit of claim 21 wherein the polysilicon is not conductive-doped with conductivity-improving impurities. delete 22. The memory circuit of claim 21 wherein the polysilicon extends laterally equally to the conductive metal nitride layer in the memory array. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Between the parts, shared, The cell electrode in the memory array comprises a conductive metal nitride layer and a conductive metal layer, wherein the conductive metal layer comprises one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein the composition of the conductive metal layer is Different from the composition of the conductive metal nitride layer, Polysilicon is received over the conductive metal nitride layer and the conductive metal layer, wherein the conductive metal nitride layer, the conductive metal layer, and the polysilicon are over memory node electrodes of, or a portion of, a plurality of memory cell capacitors. Are accepted, And the conductive metal layer is received only over a portion of each of the memory node electrodes of, or a portion of, a plurality of memory cell capacitors. 44. The memory circuit of claim 43 wherein the conductive metal nitride layer is received over each of the memory node electrodes of, or a portion of, a plurality of memory cell capacitors. The method of claim 43, The conductive metal layer is received over the conductive metal nitride layer, And the conductive metal nitride layer is received over each of the memory node electrodes of, or a portion of, the plurality of memory cell capacitors. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Between the parts, shared, The cell electrode in the memory array comprises a conductive metal nitride layer and a conductive metal layer, wherein the conductive metal layer comprises one or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride, wherein the composition of the conductive metal layer is Different from the composition of the conductive metal nitride layer, Polysilicon is received over the conductive metal nitride layer and the conductive metal layer, wherein the conductive metal nitride layer, the conductive metal layer, and the polysilicon are over memory node electrodes of, or a portion of, a plurality of memory cell capacitors. Are accepted, Memory node electrodes of, or a portion of, the plurality of memory cell capacitors take the form of a container, And the conductive metal layer is received only over a portion of each container type of memory node electrodes, or part of a plurality of memory cell capacitors. 47. The memory circuit of claim 46 wherein the conductive metal nitride layer is received over each of the memory node electrodes of, or a portion of, a plurality of memory cell capacitors. The method of claim 46, The conductive metal layer is received over the conductive metal nitride layer, And the conductive metal nitride layer is received over each of the memory node electrodes of, or a portion of, a plurality of memory cell capacitors. 22. The memory circuit of claim 21 wherein the memory node electrodes of, or a portion of, a plurality of memory cell capacitors take the form of a container and the polysilicon fills the remaining space in the container form. 22. The memory circuit of claim 21 wherein the memory circuit comprises a DRAM circuit. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Shared between the portions, the storage node electrodes take the form of a container and are received in a container hole formed in an insulating silicate glass, The cell electrode in the memory array includes a conductive metal nitride layer in a container form and a conductive metal layer received directly over the conductive metal nitride layer, the conductive metal layer being tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. Wherein the conductive metal layer is in direct contact with the conductive metal nitride layer, the composition of the conductive metal layer is different from the composition of the conductive metal nitride layer, Polysilicon is received over at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride of the conductive metal layer and on the conductive metal nitride layer, The conductive metal nitride layer, the conductive metal layer, and the polysilicon are received over memory node electrodes of, or a portion of, a plurality of memory cell capacitors, the polysilicon remaining in the form of a container of the memory node electrodes. Memory circuit, characterized in that to fill. 52. The memory circuit of claim 51 wherein the conductive metal layer comprises tungsten element. 52. The memory circuit of claim 51 wherein the conductive metal layer comprises tungsten silicide. 52. The memory circuit of claim 51 wherein the conductive metal layer comprises tungsten nitride. 52. The memory circuit of claim 51 wherein the conductive metal layer comprises a tungsten alloy. 53. The memory circuit of claim 51, wherein the conductive metal layer comprises two or more of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. 52. The memory circuit of claim 51 wherein the polysilicon is conductively-doped with conductivity-improving impurities. 53. The memory circuit of claim 51 wherein the polysilicon is not conductively-doped with conductivity-improvement impurities. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Shared between the portions, the storage node electrodes take the form of a container and are received in a container hole formed in an insulating silicate glass, The cell electrode in the memory array includes a conductive metal nitride layer in a container form and a conductive metal layer received directly over the conductive metal nitride layer, wherein the conductive metal layer is formed of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. Wherein the conductive metal layer is in direct contact with the conductive metal nitride layer, the composition of the conductive metal layer is different from the composition of the conductive metal nitride layer, Polysilicon is received directly on at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride of the conductive metal layer, The conductive metal nitride layer, the conductive metal layer, and the polysilicon are received over memory node electrodes of, or a portion of, a plurality of memory cell capacitors, the polysilicon remaining in the form of a container of the memory node electrodes. And the polysilicon does not comprise a conductive portion of the cell electrode. 53. The memory circuit of claim 51 wherein the polysilicon extends laterally equally to the conductive metal nitride layer in the memory array. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Shared between the portions, the storage node electrodes take the form of a container and are received in a container hole formed in an insulating silicate glass, The cell electrode in the memory array includes a conductive metal nitride layer in a container form and a conductive metal layer received directly over the conductive metal nitride layer, wherein the conductive metal layer is formed of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. Wherein the conductive metal layer is in direct contact with the conductive metal nitride layer, the composition of the conductive metal layer is different from the composition of the conductive metal nitride layer, Polysilicon is received directly on at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride of the conductive metal layer, The conductive metal nitride layer, the conductive metal layer, and the polysilicon are received over memory node electrodes of, or a portion of, a plurality of memory cell capacitors, the polysilicon remaining in the form of a container of the memory node electrodes. Fill it up, And the conductive metal layer is received only over a portion of each of the memory node electrodes of, or a portion of, a plurality of memory cell capacitors. A memory circuit comprising a memory array, the memory circuit comprising: The memory array comprises a plurality of memory cell capacitors, each capacitor comprising a memory node electrode, a capacitor dielectric region, and a cell electrode, wherein the cell electrode is between a plurality of memory cell capacitors within a memory array, or Shared between the portions, the storage node electrodes take the form of a container and are received in a container hole formed in an insulating silicate glass, The cell electrode in the memory array includes a conductive metal nitride layer in a container form and a conductive metal layer received directly over the conductive metal nitride layer, wherein the conductive metal layer is formed of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride. Wherein the conductive metal layer is in direct contact with the conductive metal nitride layer, the composition of the conductive metal layer is different from the composition of the conductive metal nitride layer, Polysilicon is received directly on at least one of tungsten element, tungsten alloy, tungsten silicide, or tungsten nitride of the conductive metal layer, The conductive metal nitride layer, the conductive metal layer, and the polysilicon are received over memory node electrodes of, or a portion of, a plurality of memory cell capacitors, the polysilicon remaining in the form of a container of the memory node electrodes. Filling in, The polysilicon extends laterally equally with the conductive metal nitride layer in the memory array, And the conductive metal layer is received only over a portion of each of the memory node electrodes of, or a portion of, a plurality of memory cell capacitors.

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