KR100884118B1 - Electro?optical device, electronic apparatus, and method of manufacturing electro?optical device - Google Patents

Abstract

An electro-optical device, an electronic device, and an electro-optical device capable of suppressing variation in capacity of the storage capacitor and lowering the breakdown voltage of the storage capacitor even when a portion of the gate insulating layer partially thinned is used as the dielectric layer of the storage capacitor. To provide a method for producing the same.

In forming the holding capacitance of the liquid crystal device, after forming the thick lower gate insulating layer 4a of the gate insulating layer 4, the lower gate insulating layer of the portion overlapping the lower electrode 3c by dry etching. Remove (4a). Next, a thin upper gate insulating layer 4b is formed, and the upper gate insulating layer 4b is used as the dielectric layer 4c of the storage capacitor 1h.

Description

ELECTRO-OPTICAL DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING ELECTRO-OPTICAL DEVICE}

1 (a) and 1 (b) are a plan view of a liquid crystal device (electro-optical device) as viewed from an opposing substrate side with respective components formed thereon, and a cross-sectional view taken along the line H-H ';

Explanatory drawing which shows the electrical structure of the element substrate of the liquid crystal device shown in FIG.

3 (a) and 3 (b) are a plan view of one pixel of the liquid crystal device according to the first embodiment of the present invention, and a cross-sectional view when the liquid crystal device is cut at a position corresponding to A1-B1,

4 (a) to 4 (g) are cross-sectional views illustrating a method of manufacturing an element substrate used in the liquid crystal device shown in FIG. 3;

(A)-(d) is process sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG.

6 (a) and 6 (b) are a plan view of one pixel of the liquid crystal device according to the second embodiment of the present invention, and a sectional view when the liquid crystal device is cut at a position corresponding to A2-B2,

7 (a) to 7 (g) are cross-sectional views illustrating a method for manufacturing an element substrate used in the liquid crystal device shown in FIG. 6;

8 (a) and 8 (b) are a plan view of one pixel of the liquid crystal device according to the third embodiment of the present invention, and a cross-sectional view when the liquid crystal device is cut at a position corresponding to A3-B3,

9 (a) to 9 (g) are cross-sectional views illustrating a method for manufacturing an element substrate used in the liquid crystal device shown in FIG. 8;

10 (a) and 10 (b) are a plan view of one pixel of the liquid crystal device according to the fourth embodiment of the present invention, and a cross-sectional view when the liquid crystal device is cut at a position corresponding to A4-B4,

(A)-(g) is sectional drawing which shows the manufacturing method of the element substrate used for the liquid crystal device shown in FIG.

12 (a) and 12 (b) are a plan view of one pixel of the liquid crystal device according to the fifth embodiment of the present invention, and a cross-sectional view when the liquid crystal device is cut at a position corresponding to A5-B5,

13 is an explanatory diagram when a liquid crystal device according to the present invention is used as a display device of various electronic devices;

14 (a) and 14 (b) are a plan view of one pixel of a conventional liquid crystal device, and a cross-sectional view when the liquid crystal device is cut at a position corresponding to A11-B11,

15 (a) to 15 (e) are cross-sectional views illustrating a method of manufacturing an element substrate used in a liquid crystal device according to a reference example.

Explanation of symbols for the main parts of the drawings

1: liquid crystal device (electro-optical device) 1b: pixel

1c: thin film transistor 1e: pixel formation region

1f: liquid crystal 1g: liquid crystal capacity

1h: holding capacitor 2a: pixel electrode

3a: gate line (gate electrode / scanning line) 3b: capacitor line

3c: lower electrode of storage capacitor 4: gate insulating layer

4a: lower gate insulating layer 4b: upper gate insulating layer

4c: dielectric layer 6a: source line (data line)

6b: drain electrode

5a, 6c, 6d: upper electrode of holding capacitor

The present invention relates to an electro-optical device, an electronic device, and a manufacturing method of the electro-optical device provided with a thin film transistor and a storage capacitor on an element substrate.

Among various electro-optical devices, in the active matrix liquid crystal device, for example, the liquid crystal is held between the element substrate 10 and the opposing substrate (not shown) shown in FIGS. 14A and 14B. In the element substrate 10, each of the plurality of pixel regions 1e corresponding to the intersection of the gate line 3a (scan line) and the source line 6a (data line) has a pixel switching thin film transistor 1c, And a pixel electrode 2a electrically connected to the drain region of the thin film transistor 1c, and is formed by an image signal applied from the source line 6a to the pixel electrode 2a via the thin film transistor 1c. The orientation of the liquid crystal 1f is controlled for each pixel. Further, in the pixel region 1e, a storage capacitor 1h is formed in which the extending portion of the drain electrode 6b at the time of driving the liquid crystal 1f is the upper electrode 6c. In (1h), the gate insulating layer 4 of the thin film transistor 1c is often used as the dielectric layer 4c. Here, when the capacitance value per unit area of the storage capacitor 1h is increased, the charge retention characteristic is improved. In addition, when the capacitance value per unit area of the storage capacitor 1h is increased, the occupied area can be reduced, and the pixel aperture ratio can be increased.

Thus, in forming a thin film transistor having a bottom gate structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are sequentially stacked from the lower layer side, after forming the gate insulating layer, the gate insulating layer is formed on the upper layer of the gate insulating layer. The semiconductor layer is formed in an island shape, and then, the portion of the gate insulating layer that overlaps with the lower electrode of the storage capacitor is etched to a position halfway in the depth direction, and the portion where the film thickness is thinned by etching is formed. The structure used as a dielectric layer is proposed (refer patent document 1).

Further, in forming a top gate structure thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are stacked in this order from the lower layer side, they are formed by thermal oxidation of the semiconductor layer. After forming the laminated film of the 1st insulating film which consists of a silicon oxide film, and the 2nd insulating film which consists of a silicon nitride film formed by the CVD method as a gate insulating layer, the area | region which overlaps with a channel region among the gate insulating layers is covered with a resist mask, and a 2nd insulating film is formed. The structure which removes an insulating film by an etching and uses the part which thinned the film thickness in the gate insulating layer as a dielectric layer of a storage capacitance is proposed (refer patent document 2).

(Patent Document 1) Japanese Patent Publication No. 2584290

(Patent Document 2) Japanese Patent Publication No. 3106566

However, as in the technique described in Patent Literature 1, when the gate insulating layer is thinned by etching to form a dielectric layer having a storage capacitance, both of the film thickness variation at the time of film formation and the variation in removal amount of the gate insulating layer at the time of etching are There exists a problem that it affects and it is easy to produce a deviation in the capacity | capacitance of a maintenance capacitance.

Further, as in the technique described in Patent Document 2, when the second insulating film is etched by covering a region overlapping with the channel region in the gate insulating layer with a resist mask, there is a problem that the interface between the gate insulating layer and the gate electrode is contaminated by the resist. have.

As described below with reference to FIG. 15, the inventor of the present invention describes a device substrate including a thin film transistor having a lower gate structure described with reference to FIGS. 14A and 14B. It is proposed to apply the technique, and according to such a configuration, as described below with reference to Fig. 15, the interface between the gate insulating layer and the gate electrode can be prevented from being contaminated by the resist. However, like the technique described in Patent Literature 2, when the second insulating film on the upper side of the first insulating film and the second insulating film constituting the gate insulating layer is removed by etching, the first insulating film at the time of etching the second insulating film There is a problem that this damage is caused and the withstand voltage of the holding capacitor is lowered. FIG. 15 is a cross sectional view when the technique described in Patent Document 2 is applied when manufacturing the element substrate 10 including the thin film transistor 1c having the lower gate structure as shown in FIGS. 14A and 14B. The example described here is not a prior art but a reference example devised by the present inventor. In the manufacturing method shown in FIG. 15, first, as shown to FIG. 15 (a), after simultaneously forming the gate line 3a (gate electrode) with the lower electrode 3c (part of the capacitor line 3b), As shown in Fig. 15B, the lower gate insulating layer 4a constituting the lower side of the gate insulating layer 4 and the upper gate insulating layer constituting the upper side of the gate insulating layer 4 ( 4b). Next, an intrinsic amorphous silicon film 7d for forming an active layer and an n ⁺ type silicon film 7e for forming an ohmic contact layer are sequentially formed, followed by etching. As shown in FIG. 15C, the semiconductor layer 7a and the n ⁺ -type silicon film 7e constituting the active layer are patterned into island shapes. Next, as shown in FIG.15 (d), the part which overlaps with the lower electrode 3c in the gate insulating layer 4 is etched, the upper gate insulating layer 4b is removed, and the opening 41 is removed. To form. Next, after forming a conductive film, etching is performed to form a source electrode (source line 6a) and a drain electrode 6b. Subsequently, the n ⁺ type silicon film 7e is etched to form ohmic contact layers 7b and 7c. As a result, the thin film transistor 1c is formed. In addition, a storage capacitor 1h is formed in which the lower gate insulating layer 4a is the dielectric layer 4c, and the extending portion of the drain electrode 6b is the upper electrode 6c.

According to this manufacturing method, both the interface between the gate insulating layer 4 and the gate electrode (gate line 3a) and the interface between the gate insulating layer 4 and the semiconductor layer 7a can be prevented from being contaminated by the resist. Although the semiconductor film 7a is patterned by dry etching in the process shown in FIG. 15C, and the upper gate insulating layer 4b is dry-etched in the process shown in FIG. Two times during removal, the lower gate insulating layer 4a is damaged by static electricity or plasma during dry etching, and a defect occurs in the lower gate insulating layer 4a. In the process shown in Fig. 15D, when the upper gate insulating layer 4b is removed by wet etching, pinholes are generated in the weak portion of the lower gate insulating layer 4a. As a result, there arises a problem that the withstand voltage of the holding capacitor 1h is lowered.

In view of the above problems, an object of the present invention is to provide an electro-optical device which can suppress the capacitance variation of the storage capacitance and the drop in the breakdown voltage of the storage capacitance even when a portion of the gate insulating layer partially thinned is used as the dielectric layer of the storage capacitance. It is providing the manufacturing method of an electronic device, and an electro-optical device.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, in this invention, the thin film transistor in which the gate electrode, the gate insulation layer, and the semiconductor layer were laminated | stacked in each of the several pixel area | region on the element substrate, and is electrically connected to the drain region of this thin film transistor In the electro-optical device having a pixel electrode, and a storage capacity having a lower electrode and an upper electrode facing each other with the gate insulating layer interposed therebetween, the thin film transistor includes the gate electrode, the gate insulating layer, and the semiconductor layer. It is laminated | stacked in order from the lower layer side, The said gate insulating layer is provided with the lower gate insulating layer which consists of one layer-several layers of insulating films, and the upper gate side insulating layer which consists of one layer-several layers of insulating films, The said lower layer The gate insulating layer is formed to a thickness that makes the parasitic capacitance of the thin film transistor small. The lower electrode and is characterized in that it is removed from the upper electrode and the overlapping portion.

In the present invention, a thin film transistor having a structure in which a gate electrode, a gate insulating layer and a semiconductor layer are stacked on each of the plurality of pixel regions on the element substrate, a pixel electrode electrically connected to the drain region of the thin film transistor, and In the method of manufacturing an electro-optical device having a storage capacitor having a lower electrode and an upper electrode facing each other with a gate insulating layer interposed therebetween, a gate electrode forming step of simultaneously forming the gate electrode with the lower electrode, and the gate insulating layer And a gate insulating layer forming step of forming a semiconductor layer, and a semiconductor layer forming step of forming a semiconductor layer. In the gate insulating layer forming step, a lower layer of the gate insulating layer is formed to a thickness that decreases the parasitic capacitance of the thin film transistor. A lower gate insulating layer forming step of forming an insulating film of one or more layers to constitute, A lower gate insulating layer etching step of removing portions overlapping with the lower electrode from the insulating film formed in the lower gate insulating layer forming step, and an upper layer forming one or more insulating films forming the upper layer side of the gate insulating layer; A gate insulating layer forming step is performed.

In the present invention, the thin film transistor formed in the pixel formation region has a thin film transistor having a lower gate structure in which a gate electrode, a gate insulating layer, and a semiconductor layer are laminated in order from the lower layer side. Thus, the upper gate insulating layer and the semiconductor layer A layer can be formed continuously. Therefore, it is possible to prevent contamination of both the interface between the gate insulating layer and the gate electrode and the interface between the gate insulating layer and the semiconductor layer by the resist. For this reason, the reliability of a thin film transistor can be improved. Further, in using the partially thinned gate insulating layer as the dielectric layer for the storage capacitance, the dielectric layer is formed only by the upper gate insulating layer without leaving the lower gate insulating layer, whereby the gate insulating layer is positioned in the middle of the depth direction. Since it is not necessary to employ the configuration of etching until now, it is possible to prevent the capacity variation of the holding capacitance caused by the variation in the etching depth. In using the partially thinned gate insulating layer as the dielectric layer for the storage capacitance, the lower gate insulating layer is removed from the lower gate insulating layer and the upper gate insulating layer to hold the upper gate insulating layer. It is used as a dielectric layer of capacity. Such an upper gate insulating layer is not exposed to static electricity or plasma when the lower gate insulating layer is partially dry-etched, so that surface damage and defects can be prevented from occurring in the upper gate insulating layer. In addition, since the upper gate insulating layer does not come into contact with the etchant when the lower gate insulating layer is partially wet-etched, no pinhole is generated in the upper gate insulating layer. For this reason, it can prevent that the withstand voltage of a storage capacitance falls.

In the present invention, it is preferable that the upper gate insulating film is formed thinner than the lower gate insulating film.

In the present invention, the upper gate insulating layer forming step and the semiconductor layer forming step are preferably performed continuously while maintaining the element substrate in a vacuum atmosphere. In such a configuration, the surface of the gate insulating layer (the surface of the upper gate insulating layer) can be kept clean, whereby the reliability of the thin film transistor can be improved.

In the present invention, the lower gate insulating layer and the upper gate insulating layer may be formed of a plurality of insulating films, respectively, but the lower gate insulating layer and the upper gate insulating layer are each one insulating film. You may comprise by.

In the present invention, the semiconductor layer is made of, for example, an amorphous silicon film.

In the present invention, the upper gate insulating layer is preferably made of a silicon nitride film. Since the silicon nitride film has a higher dielectric constant than that of the silicon oxide film, a high capacity can be obtained if the area occupied by the storage capacitor is the same.

In the present invention, the upper electrode may be configured to be a portion extending from the drain electrode of the thin film transistor to a region facing the lower electrode.

In the present invention, the upper electrode may adopt a configuration in which the pixel electrode is a portion facing the lower electrode.

In the present invention, the upper electrode may be configured to be a transparent electrode electrically connected to the drain electrode of the thin film transistor. In such a configuration, the pixel aperture ratio can be increased as compared with the case where the light-shielding upper electrode is used.

In this invention, the structure in which the said lower electrode is formed by the capacitance line extended in parallel with the said gate line can be employ | adopted. Further, in the present invention, the lower electrode is formed by a gate line for supplying a gate signal to a pixel region of a front end adjacent to the pixel region where the lower electrode is formed in a direction crossing the extension direction of the gate line. The formed structure may be adopted.

The electro-optical device according to the present invention can be used for electronic devices such as mobile phones and mobile computers.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each drawing used for the following description, in order to make each layer or each member the magnitude | size which can be recognized on drawing, the scale was made different for each layer or each member. In addition, in the following description, the same code | symbol is attached | subjected and demonstrated to the part which has a common function so that correspondence with the example shown in FIG. 14 and FIG. 15 becomes clear.

(Example 1)

(Overall Configuration of Liquid Crystal Device)

Fig.1 (a), (b) is the top view which looked at the liquid crystal device (electro-optical device) with the each component formed on it on the opposing board | substrate side, respectively, and its HH 'cross section. 1 (a) and (b), the liquid crystal device 1 of the present embodiment is a transmissive active matrix liquid crystal of TN (Twisted Nematic) mode, ECB (Electrically Controlled Birefringence) mode, or VAN (Vertical Aligned Nematic) mode. Device. In this liquid crystal device 1, the element substrate 10 and the counter substrate 20 are bonded to each other via a sealant 22, and the liquid crystal 1f is held therebetween. In the element substrate 10, a data line driving IC 60 and a scanning line driving IC 30 are mounted in a chip on glass (COG) area at an end region located outside the sealing agent 22. Moreover, the mounting terminal 12 is formed along the board | substrate side. The sealant 22 is an adhesive made of a photocurable resin, a thermosetting resin, or the like for joining the element substrate 10 and the counter substrate 20 around them, and includes a glass fiber for setting a distance between both substrates to a predetermined value ( Gap materials, such as glass fiber or glass beads, are mix | blended. In the sealing agent 22, the liquid crystal injection port 25 is formed by the broken part, and after inject | pouring a liquid crystal 1f, it is sealed by the sealing material 26. As shown in FIG.

Although mentioned later in detail, the thin film transistor 1c and the pixel electrode 2a are formed in matrix form in the element substrate 10, and the oriented film 19 is formed in the surface. In the opposing substrate 20, a frame 24 (not shown in Fig. 1 (b)) made of a light-shielding material is formed in an inner region of the sealant 22, and the inner side thereof is an image display region 1a. have. Although not shown in the opposing substrate 20, a light shielding film called a black matrix or black stripe is formed in an area facing the longitudinal and horizontal boundary regions of each pixel, and the opposing electrode 28 and the alignment film are formed on the upper layer side. (29) is formed. Although not shown in FIG. 1 (b), in the opposing substrate 20, an RGB color filter is formed together with the protective film in a region facing each pixel of the element substrate 10, whereby a liquid crystal device ( 1) can be used as a color display device of an electronic device such as a mobile computer, a cellular phone, a liquid crystal television, or the like.

(Configuration of Element Substrate 10)

It is explanatory drawing which shows the electrical structure of the element substrate of the liquid crystal device shown in FIG. As shown in FIG. 2, in the element substrate 10, a direction in which a plurality of source lines 6a (data lines) and gate lines 3a (scan lines) cross each other in an area corresponding to the image display area 1a. The pixel 1b is formed in the position corresponding to the crossing part of these wiring. The gate line 3a extends from the scan line driver IC 30, and the source line 6a extends from the data line driver IC 60. In the element substrate 10, a pixel switching thin film transistor 1c for controlling the driving of the liquid crystal 1f is formed in each pixel 1b, and a source line 6a is provided at a source of the thin film transistor 1c. This is electrically connected, and the gate line 3a is electrically connected to the gate of the thin film transistor 1c.

In addition, the capacitor substrate 3b is formed in the element substrate 10 in parallel with the gate line 3a. In this embodiment, the liquid crystal capacitor 1g configured between the thin film transistor 1c and the counter substrate 20 is connected in series, and the holding capacitor 1h is parallel to the liquid crystal capacitor 1g. Connected. Here, the capacitor line 3b is connected to the scan line driving IC 30, but is held at the potential of the electrostatic potential. In addition, the storage capacitor 1h may be comprised between the gate line 3a of the front end, and in this case, the capacitance line 3b can be abbreviate | omitted.

In the liquid crystal device 1 configured as described above, the thin film transistor 1c is turned on for only a predetermined period of time, so that the image signal supplied from the source line 6a is predetermined to the liquid crystal capacitor 1g of each pixel 1b. Write at the timing. The image signal of a predetermined level written in the liquid crystal capacitor 1g is held for a certain period of time in the liquid crystal capacitor 1g, and the holding capacitor 1h prevents the image signal held in the liquid crystal capacitor 1g from leaking out. have.

(Configuration of Each Pixel)

3 (a) and 3 (b) are a plan view of one pixel of the liquid crystal device according to the first embodiment of the present invention, and sectional views when the liquid crystal device is cut at a position corresponding to A1-B1. In FIG. 3A, the pixel electrode is represented by a thick long dotted line, the gate line and the thin film formed at the same time are represented by a thin solid line, the source line and the thin film formed at the same time are represented by a thin dashed line, and the semiconductor layer is represented by a thin and short dotted line. Indicates. The portion corresponding to the dielectric layer constituting the storage capacitor is represented by a thin double-dot chain line, and the contact hole is represented by a thin solid line like the gate line or the like.

As shown in FIG. 3A, the element substrate 10 includes the following elements constituting the pixel 1b in the pixel region 1e surrounded by the gate line 3a and the source line 6a. have. First, a semiconductor layer 7a made of an amorphous silicon film constituting the active layer of the lower gate type thin film transistor 1c is formed in the pixel region 1e. In addition, the gate electrode is formed by the protruding portion from the gate line 3a. In the semiconductor layer 7a constituting the active layer of the thin film transistor 1c, the source line 6a overlaps as a source electrode at the end of the source side, and the drain electrode 6b overlaps the end of the drain side. In addition, the capacitor line 3b is formed in parallel with the gate line 3a.

Further, in the pixel region 1e, the storage capacitor 1h having the protruding portion from the capacitor line 3b as the lower electrode 3c and the extending portion from the drain electrode 6b as the upper electrode 6c is provided. Formed. The upper electrode 6c is electrically connected to the pixel electrode 2a made of an ITO film (Indium Tin Oxide) via the contact holes 81 and 91.

The cross section A1-B1 of the element substrate 10 configured as described above is displayed as shown in Fig. 3B. First, a gate line 3a (gate electrode) and a capacitor line 3b (lower electrode 3c of the holding capacitor 1h) made of a conductive film are formed on an insulating substrate 11 made of a glass substrate or a quartz substrate. Formed. In this embodiment, both the gate line 3a and the capacitor line 3b have a two-layer structure in which a molybdenum film having a film thickness of 20 nm is laminated on an upper layer of a neodymium-containing aluminum alloy film having a film thickness of 150 nm.

In this embodiment, the gate insulating layer 4 is formed on the upper layer side of the gate line 3a so as to cover the gate line 3a. The semiconductor layer 7a constituting the active layer of the thin film transistor 1c is formed in a region partially overlapping with the protruding portion (gate electrode) of the gate line 3a among the upper layers of the gate insulating layer 4. . In the semiconductor layer 7a, an ohmic contact layer 7b made of a doped silicon film and a source line 6a are stacked on an upper layer of a source region, and an ohmic contact made of a doped silicon film is formed on an upper layer of a drain region. The layer 7c and the drain electrode 6b are formed, and the thin film transistor 1c is comprised. In addition, the upper electrode 6c of the storage capacitor 1h is formed by the extending portion of the drain electrode 6b. In this embodiment, the semiconductor layer 7a is made of an intrinsic amorphous silicon film having a film thickness of 150 nm, and the ohmic contact layers 7b, 7c have an n ⁺ type amor having a thickness of 50 nm doped with phosphorus. It is made of a parse silicon film. The source line 6a and the drain electrode 6b (upper electrode 6c) both face the upper layer from the lower layer toward the upper layer, and the molybdenum film having a film thickness of 5 nm, the aluminum film having a film thickness of 1500 nm, and the film thickness The three-layer structure which laminated | stacked the 50 nm molybdenum film is provided.

On the upper layer side of the source line 6a, the drain electrode 6b, and the upper electrode 6c, a passivation film 8 made of a silicon nitride film or the like and a planarization film 9 made of a photosensitive resin layer such as an acrylic resin are provided. Each is formed as an interlayer insulating film, and the pixel electrode 2a is formed on the upper layer of the planarization film 9. The pixel electrode 2a is electrically connected to the upper electrode 6c via the contact hole 91 formed in the planarization film 9 and the contact hole 81 formed in the passivation film 8, and the upper electrode 6c. And the drain electrode 6b are electrically connected to the drain region of the thin film transistor 1c. An alignment film 19 is formed on the surface of the pixel electrode 2a. In this embodiment, the passivation film 8 consists of a silicon nitride film whose film thickness is 250 nm, and the pixel electrode 2a consists of an ITO film whose film thickness is 100 nm.

The opposing substrate 20 is disposed to face the element substrate 10 configured as described above, and the liquid crystal 1f is held between the element substrate 10 and the opposing substrate 20. On the counter substrate 20, color filters 27, counter electrodes 28, and alignment films 29 of respective colors are formed, and the liquid crystal capacitor 1g (between the pixel electrode 2a and the counter electrode 28 ( 2). Moreover, although a black matrix, a protective film, etc. may be formed in the counter substrate 20 side, those illustration is abbreviate | omitted.

(Configuration of the gate insulating layer and the dielectric layer)

In the liquid crystal device 1 of this embodiment, the gate insulating layer 4 is formed of a lower gate insulating layer 4a made of a thick silicon nitride film and an upper gate insulating layer made of a thin silicon nitride film. It is a two-layer structure. In this embodiment, the film thickness of the lower gate insulating layer 4a is formed to a thickness that reduces the influence of the parasitic capacitance of the thin film transistor, and the film thickness of the upper gate insulating film is formed thinner than the lower gate insulating film. For example, the lower gate insulating film is 250 to 500 nm, preferably 300 nm, and the film thickness of the upper gate insulating layer 4b is 50 to 200 nm, preferably 100 nm. These film thicknesses can be optimally determined after considering the balance of the write capability, parasitic capacitance, and retention capacitance of the thin film transistor. For example, in the case of a structure in which the size of the pixel 1b is small in high image quality (for example, short side of one pixel is 40 µm or less), the storage capacitor 1h and the liquid crystal capacitor 1g in the pixel 1c are reduced. The minimum dimension of the thin film transistor 1c is suppressed by the resolution of photolithography. For this reason, in such high-definition pixels, the ratio of the parasitic capacitance of the thin film transistor 1c to the total capacitance of one pixel becomes high. When the ratio of parasitic capacitance (hereinafter referred to as parasitic capacitance ratio) increases, it is known that the electro-optical device 1 causes deterioration of display quality such as flicker, crosstalk, burning, etc. It is common to design so that this parasitic capacitance ratio will be as small as possible. However, when the parasitic capacitance ratio is limited by the high quality layout as described above, it is difficult to improve this in the conventional technique. By using the structure and process of the present invention, however, the film thickness of the gate insulating film 4 of the thin film transistor 1c can be set and manufactured completely independently of the side of the storage capacitor 1h. That is, in the above-described high-definition pixel, by setting the gate insulating film thicker than the standard condition, the parasitic capacitance of the thin film transistor 1c can be reduced and the parasitic capacitance ratio can be made small. In this condition setting, although the current driving capability (signal writing capability to the pixel 1b) of the thin film transistor 1c is lowered, the pixel capacitance itself to be written in a high-definition pixel is smaller. Even if the thickness is increased, the design can be performed so that a problem does not occur in writing capability.

In this embodiment, the lower gate insulating layer 4a in the gate insulating layer 4 is in the region overlapping the lower electrode 3c and the upper electrode 6c of the storage capacitor 1h in a planar manner over the entire thickness direction. It is removed and the opening 41 is formed. On the other hand, the upper gate insulating layer 4b is formed in substantially the entire surface. For this reason, the gate insulating layer 4 consists only of the upper gate insulating layer 4b in the area | region which overlaps planarly with the lower electrode 3c and the upper electrode 6c (region overlapping planarly with opening 41). The thin film part is provided, and the thin film part constitutes the dielectric layer 4c of the storage capacitor 1h. Here, a thick portion having the same thickness as the gate insulating layer 4 remains on the upper layer side of the lower electrode 3c along the edge of the lower electrode 3c, and the dielectric layer 4c is surrounded by this thick insulating film. For this reason, the fall of the withstand voltage which is easy to generate | occur | produce in the edge part of the lower electrode 3c or the edge part of the upper electrode 6c can be prevented.

(Manufacturing method of the liquid crystal device 1)

4 (a) to 4 (g) and 5 (a) to (d) are cross-sectional views illustrating a method of manufacturing the element substrate 10 used in the liquid crystal device 1 of the present embodiment. In addition, in order to manufacture the element substrate 10, although the following process is performed in the state of the large substrate which can take many element substrates 10, in the following description, as the element substrate 10 also about a large substrate, Explain.

First, in the gate electrode forming step shown in Fig. 4A, a metal film (aluminum alloy film having a film thickness of 150 nm and molybdenum having a film thickness of 20 nm) is formed on the surface of an insulating substrate 11 such as a large glass substrate. After the film is formed, the metal film is patterned using photolithography, and the gate line 3a (gate electrode) and the capacitor line 3b (lower electrode 3c) are simultaneously formed.

Next, a gate insulating layer forming step is performed. In this embodiment, in the gate insulating layer forming step, first, in the lower gate insulating layer forming step shown in FIG. 4B, the thick lower layer side constituting the lower layer side of the gate insulating layer 4 by the plasma CVD method. The gate insulating layer 4a is formed. In this embodiment, the lower gate insulating layer 4a is made of a silicon nitride film having a film thickness of about 300 nm.

Next, in the lower gate insulating layer etching step shown in FIG. 4C, a resist mask (not shown) having an opening is formed in a region overlapping with the lower electrode 3c in a planar manner using a photolithography technique. After that, reactive ion etching (dry etching) with a fluorine-based etching gas such as SF ₆ is performed on the lower gate insulating layer 4a to form the opening 41. Since such reactive ion etching utilizes the physical sputtering effect of the ions and the synergistic effect of the radical chemical etching effect, it is excellent in anisotropy and high productivity can be obtained.

Next, in the upper gate insulating layer film forming step shown in FIG. 4 (d), the thin upper gate insulating layer 4b constituting the upper layer of the gate insulating layer 4 is formed by the plasma CVD method. In this embodiment, the upper gate insulating layer 4b is made of a silicon nitride film having a film thickness of about 100 nm. As a result, a gate insulating layer 4 composed of a thick lower gate insulating layer 4a and a thin upper gate insulating layer 4b is formed on the upper layer side of the gate line 3a (gate electrode). The dielectric layer 4c which consists only of the upper gate insulating layer 4b is formed in the area | region which overlaps planarly with the opening 41. As shown in FIG.

Next, in the semiconductor layer forming step shown in Fig. 4E, by the plasma CVD method, an intrinsic amorphous silicon film 7d having a film thickness of 150 nm and an n ⁺ type silicon film having a film thickness of 50 nm are formed. 7e) are formed continuously. At that time, the semiconductor substrate forming process shown in FIG. 4E is performed while the element substrate 10 which performed the upper gate insulation layer forming process shown in FIG. 4D is maintained in a vacuum atmosphere, and the element substrate 10 is performed. ) Is not in contact with the atmosphere. Thereby, the amorphous silicon film 7d can be laminated | stacked in the state in which the surface of the gate insulating layer 4 (upper gate insulating layer 4b) is clean.

Next, as shown in FIG. 4 (f), the amorphous silicon film 7d and the n ⁺ -type silicon film 7e are etched using a photolithography technique to form an island-like semiconductor layer 7a. , And island-like n ⁺ type silicon film 7e is formed. Also in this etching, reactive ion etching (dry etching) using fluorine etching gas such as SF ₆ is performed.

Next, as shown in Fig. 4 (g), after forming a metal film (laminated film of molybdenum film having a film thickness of 5 nm, aluminum film having a film thickness of 1500 nm, and molybdenum film having a film thickness of 50 nm), And patterning using photolithography techniques to form the source line 6a, the drain electrode 6b, and the upper electrode 6c. Subsequently, using the source line 6a and the drain electrode 6b as a mask, the n ⁺ type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to remove the source and drain. Is separated. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed to form ohmic contact layers 7b and 7c. At this time, a part of the surface of the semiconductor layer 7a is etched. In this way, the low gate pixel switching thin film transistor 1c is formed, and the storage capacitor 1h is formed.

Next, as shown to Fig.5 (a), the passivation film 8 which consists of a silicon nitride film whose film thickness is 250 nm is formed by plasma CVD method.

Next, as shown in FIG.5 (b), after apply | coating photosensitive resin, such as an acrylic resin, by spin coating method, it exposes and develops and the planarization film 9 provided with the contact hole 91 is formed. do.

Next, as shown in FIG. 5C, the passivation film 8 is etched using photolithography technology to form the contact hole 81 at a position overlapping with the contact hole 91. Also in this etching, reactive ion etching (dry etching) using fluorine etching gas such as SF ₆ is performed.

Next, as shown in Fig. 5 (d), an ITO film having a thickness of 100 nm is formed by the sputtering method, and then patterned by using photolithography technique and wet etching to form the pixel electrode 2a. . As a result, the pixel electrode 2a is electrically connected to the upper electrode 6c via the contact holes 91 and 81. Next, after forming the polyimide film for forming the oriented film 19 shown to FIG. 3 (b), polishing process is performed.

In this way, the element substrate 10 in which various wirings and TFTs are formed in the state of the large substrate is bonded to the large counter substrate 20 formed separately and the sealing agent 22, and then cut into a predetermined size. As a result, since the liquid crystal injection hole 25 is opened, after the liquid crystal 1f is injected between the element substrate 10 and the counter substrate 20 from the liquid crystal injection hole 25, the liquid crystal injection hole 25 is sealed with the sealing material 26. Seal by.

(Main effect of this form)

As described above, in the liquid crystal device 1 of this embodiment, since the thin film transistor 1c has a lower gate structure, it is intrinsic to form the upper gate insulating film 4b and the active layer (semiconductor layer 7a). Since the amorphous silicon film 7d and the n ⁺ type silicon film 7e for forming the ohmic contact layers 7b and 7c can be formed in succession, the amorphous silicon film is formed on the upper layer of the clean upper gate insulating film 4b. The film 7d can be formed. Furthermore, in this embodiment, when the upper gate insulating film 4b, the amorphous silicon film 7d, and the ohmic contact layers 7b and 7c are configured, the device substrate 10 is kept in a vacuum atmosphere. Contamination of the surface of the upper gate insulating film 4b can be reliably prevented. For this reason, the interface of the gate insulating layer 4 and the semiconductor layer 7a is clean, and the reliability of the thin film transistor 1c is high.

In addition, since the thickness of the dielectric layer 4c of the storage capacitor 1h is 1/4 times the thickness of the gate insulating layer 4, the capacitance per unit area is four times. In addition, the upper gate insulating layer 4b constituting the dielectric layer 4c is a silicon nitride film (a dielectric constant is about 7 to 8) and has a higher dielectric constant than the silicon oxide film, so that the storage capacitor 1h has a capacitance per unit area. This is high. For this reason, the storage capacitance 1h has a high charge retention characteristic, and the pixel aperture ratio can be increased by reducing the occupied area as the capacitance value per unit area is increased.

In addition, in this embodiment, in using the partially thinned portion of the gate insulating layer 4 as the dielectric layer 4c of the storage capacitor 1h, the upper gate insulating layer is left without leaving the lower gate insulating layer 4a. Since the dielectric layer 4c is formed only of the layer 4b, unlike the case of partially leaving the lower gate insulating layer 4a, it is possible to prevent the capacitance variation of the holding capacitor 1h due to the variation in the etching depth.

In this embodiment, the part where the gate insulating layer 4 is partially thinned is used as the dielectric layer 4c of the storage capacitor 1h, and the lower gate insulating layer 4a and the upper gate insulating layer 4b are used. ), The lower gate insulating layer 4a is removed, and the upper gate insulating layer 4b formed on the upper layer of the lower gate insulating layer 4a is used as the dielectric layer 4c of the storage capacitor 1h. . In such an upper gate insulating layer 4b, since the lower gate insulating layer 4a is not exposed to static electricity or plasma when the lower gate insulating layer 4a is removed by dry etching, the defect density of the upper gate insulating layer 4b is low. For this reason, generation | occurrence | production of the problem of the breakdown voltage of the holding capacitor 1h, etc. can be prevented. For example, the dielectric layer 4c (lower gate insulating layer 4a) of the storage capacitor 1h described with reference to FIG. 15 has a defect density of 0.2 pieces / cm ² under the influence of static electricity or plasma. The dielectric layer 4c (upper gate insulating layer 4b) of the storage capacitor 1h of the form is not affected by static electricity or plasma, and has a defect density of 0.01 / cm ² , which is remarkably small. Such a defect density is equivalent to 20% in the liquid crystal device 1 having the holding capacitor 1h described with reference to FIG. 15 when converted into a 2.4-inch HVGA system liquid crystal panel. According to the liquid crystal device 1 with the holding capacitor 1h, the defective occurrence rate can be reduced to 1%.

In this embodiment, although the opening 41 is formed by dry etching the lower gate insulating layer 4a, the opening 41 may be formed by wet etching. Even in this case, since the upper gate insulating layer 4b does not contact the etching liquid with respect to the lower gate insulating layer 4a, pinholes do not occur in the upper gate insulating layer 4b. For this reason, the variation of the breakdown voltage of the holding capacitor 1h can be prevented.

(Example 2)

6 (a) and 6 (b) are a plan view of one pixel of the liquid crystal device according to the second embodiment of the present invention, and a cross-sectional view when the liquid crystal device is cut at a position corresponding to A2-B2. 7 (a) to 7 (g) are cross-sectional views illustrating the steps up to forming the source and drain electrodes in the manufacturing process of the element substrate 10 used in the liquid crystal device 1 of the present embodiment. In Fig. 6 (a), the pixel electrode is represented by a thick long dotted line, the gate line and the thin film formed at the same time are represented by a thin solid line, the source line and the thin film formed at the same time are represented by a thin dashed line, and the semiconductor layer is represented by a thin and short dotted line. Indicates. The portion corresponding to the dielectric layer constituting the storage capacitor is represented by a thin double-dot chain line, and the contact hole is represented by a thin solid line like the gate line or the like. Moreover, about an etching stopper layer, it shows with a thick short short line. In addition, since the basic structure of this embodiment is the same as that of Example 1, the same code | symbol is attached | subjected to a common part and their description is abbreviate | omitted.

As shown in Figs. 6 (a) and 6 (b), also in this embodiment, in the element substrate 101, in the pixel region 1e surrounded by the gate line 3a and the source line 6a in the element substrate 101, The lower gate type thin film transistor 1c and the storage capacitor 1h are formed. The storage capacitor 1h uses the protruding portion from the capacitor line 3b as the lower electrode 3c and the extending portion from the drain electrode 6b as the upper electrode 6c. The gate insulating layer 4 has a two-layer structure of the lower gate insulating layer 4a composed of a thick silicon nitride film on the lower side and the upper gate insulating layer composed of a thin silicon nitride film on the upper side as in the first embodiment. It is. The lower gate insulating layer 4a is removed over the entire thickness direction in the region overlapping planarly with the lower electrode 3c and the upper electrode 6c of the storage capacitor 1h, and the opening 41 is formed. . For this reason, the dielectric layer 4c of the storage capacitor 1h is comprised by the part (thin lower gate insulating layer 4a) of the thin film thickness among the gate insulating layers 4. As shown in FIG. An insulating film having the same thickness as the gate insulating layer 4 is formed along the edge of the lower electrode 3c among the upper layers of the lower electrode 3c, and the dielectric layer 4c is surrounded by the thick insulating film.

In this embodiment, the etching stopper layer 7x is formed in the region sandwiched between the end of the source line 6a (source electrode) and the end of the drain electrode 6b of the upper layer side of the semiconductor layer 7a. The ohmic contact layers 7b and 7c are formed so as to cover the upper layer of the stopper layer 7x. In this embodiment, the etching stopper layer 7x is made of a silicon nitride film having a film thickness of 150 nm. Since the other structure is the same as that of Example 1, description is abbreviate | omitted.

In order to manufacture the element substrate 10 having such a structure, after forming a metal film (lamination film of aluminum alloy film and molybdenum film) on the surface of the insulating substrate 11 in the gate electrode forming step shown in FIG. The metal film is patterned using photolithography technique to form the gate line 3a (gate electrode) and the capacitor line 3b (lower electrode 3c).

Next, a gate insulating layer forming step is performed. Also in this embodiment, similarly to Example 1, in the lower gate insulating layer forming step shown in FIG. 7B, a thick silicon nitride film constituting the lower layer side of the gate insulating layer 4 by the plasma CVD method (lower layer side). After the gate insulating layer 4a is formed, in the lower gate insulating layer etching step, the lower gate insulating layer 4a is etched to form the opening 41 at a position overlapping the lower electrode 3c. do. Next, in the upper gate insulating layer forming step shown in FIG. 7C, a thin silicon nitride film (upper gate insulating layer 4b) constituting the upper layer of the gate insulating layer 4 is formed.

Next, in the semiconductor layer forming step shown in FIG. 7 (d), the intrinsic amorphous silicon film 7d is formed by the plasma CVD method. At this time, about the element substrate 10 which performed the upper-layer gate insulating layer formation process shown in FIG.7 (c), the semiconductor layer formation process shown in FIG.7 (d) is performed, maintaining in the vacuum atmosphere, and an element The substrate 10 is not in contact with the atmosphere. Thereby, the amorphous silicon film 7d (active layer) can be laminated | stacked in the state in which the surface of the gate insulating layer 4 (upper gate insulating layer 4b) is clean. Next, after forming a silicon nitride film having a film thickness of 150 nm on the upper layer of the amorphous silicon film 7d, the silicon nitride film is etched to form an etching stopper layer 7x. Also in this etching, reactive ion etching (dry etching) using fluorine etching gas such as SF ₆ is performed.

Next, as shown in FIG.7 (e), the n ⁺ type silicon film 7e is formed in the upper layer side of the etching stopper layer 7x. Next, as shown in FIG. 7 (f), dry etching is performed on the amorphous silicon film 7d and the n ⁺ type silicon film 7e by using a photolithography technique to form an island-like semiconductor layer 7a. And n ⁺ type silicon film 7e.

Next, as shown in Fig. 7G, a metal film (laminated film of molybdenum film, aluminum film, and molybdenum film) is formed, and then patterned by using photolithography technology, so that the source line 6a and the drain electrode are formed. 6b and the upper electrode 6c are formed. Subsequently, using the source line 6a and the drain electrode 6b as a mask, the n ⁺ type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to remove the source and drain. Perform separation of. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed to form ohmic contact layers 7b and 7c. At this time, the etching stopper layer 7x functions to protect the semiconductor layer 7a. In this way, the low gate pixel switching thin film transistor 1c is formed, and the storage capacitor 1h is formed. Since the process after that is the same as that of Example 1, description is abbreviate | omitted.

As described above, in this embodiment, since the basic structure of the storage capacitor 1h is the same as that of the first embodiment, a highly reliable thin film transistor 1c can be formed, and a storage capacitor 1h having a high capacitance and a stable withstand voltage is formed. The same effect as in Example 1 can be obtained.

As shown in Fig. 7D, when forming the etching stopper layer 7x, the amorphous silicon film 7d functions to protect the upper gate insulating layer 4b. For this reason, even when the etching stopper layer 7x is formed, defects can be prevented from occurring in the upper gate insulating layer 4b used as the dielectric layer 4c.

(Example 3)

8A and 8B are a plan view of one pixel of the liquid crystal device according to the third embodiment of the present invention, and sectional views when the liquid crystal device is cut at a position corresponding to A3-B3. 9A to 9G are cross-sectional views showing the steps up to forming the source and drain electrodes in the manufacturing process of the element substrate 10 used in the liquid crystal device 1 of the present embodiment. In FIG. 8 (a), the pixel electrode is represented by a thick long dotted line, the gate line and the thin film formed at the same time are represented by a thin solid line, the source line and the thin film formed at the same time are represented by a thin dashed line, and the semiconductor layer is a thin and short dotted line. Represented by In addition, about the part corresponded to the dielectric layer which comprises a storage capacitance, it shows with a thin dashed-dotted line, and the contact hole is shown with a thin solid line like a gate line. In addition, about the upper electrode of a storage capacitor, it shows with a thick one-dot chain line. In addition, since the basic structure of this embodiment is the same as that of Example 1, the same code | symbol is attached | subjected to a common part and their description is abbreviate | omitted.

As shown in Figs. 8A and 8B, in this embodiment, in the element substrate 10, in the element substrate 10, the pixel region 1e surrounded by the gate line 3a and the source line 6a is formed. , The low gate type thin film transistor 1c and the storage capacitor 1h are formed.

In this embodiment, the storage capacitor 1h is similar to the first embodiment in that the protruding portion from the capacitor line 3b is the lower electrode 3c. However, the upper electrode 5a of the storage capacitor 1h is comprised by the ITO film formed between the gate insulating layer 4 and the drain electrode 6b, and the upper electrode 5a is the drain electrode 6b. It is electrically connected to the drain electrode 6b by the partial overlap part with (). In this embodiment, the film thickness of the ITO film constituting the upper electrode 5a is 50 nm. Moreover, the pixel electrode 2a formed in the upper layer of the planarization film 9 is electrically connected with respect to the upper electrode 5a through the contact holes 81 and 91. FIG.

As in the first embodiment, the gate insulating layer 4 has a two-layer structure of a lower gate insulating layer 4a made of a thick silicon nitride film and an upper gate insulating layer made of a thin silicon nitride film. It is. The lower gate insulating layer 4a is removed over the entire thickness direction in the region overlapping planarly with the lower electrode 3c and the upper electrode 5a of the storage capacitor 1h, and the opening 41 is formed. . For this reason, the dielectric layer 4c of the storage capacitor 1h is comprised by the part (thin lower gate insulating layer 4a) of the thin film thickness among the gate insulating layers 4. As shown in FIG. An insulating film having the same thickness as the gate insulating layer 4 is formed along the edge of the lower electrode 3c among the upper layers of the lower electrode 3c, and the dielectric layer 4c is surrounded by the thick insulating film. Since the other structure is the same as that of Example 1, description is abbreviate | omitted.

In order to manufacture the element substrate 10 having such a configuration, after forming a metal film (lamination film of an aluminum alloy film and a molybdenum film) on the surface of the insulating substrate 11 in the gate electrode forming step shown in FIG. The metal film is patterned using photolithography technique to form the gate line 3a (gate electrode) and the capacitor line 3b (lower electrode 3c).

Next, a gate insulating layer forming step is performed. Also in this embodiment, similarly to Example 1, in the lower gate insulating layer forming step shown in FIG. 9B, a thick silicon nitride film constituting the lower layer side of the gate insulating layer 4 by the plasma CVD method (lower layer side). After the gate insulating layer 4a is formed, in the lower gate insulating layer etching step, the lower gate insulating layer 4a is etched to form the opening 41 at a position overlapping the lower electrode 3c. do. Next, in the upper gate insulating layer film forming step shown in Fig. 9C, a thin silicon nitride film (upper gate insulating layer 4b) constituting the upper layer of the gate insulating layer 4 is formed.

Next, in the semiconductor layer forming step shown in FIG. 9D, the intrinsic amorphous silicon film 7d and the n ⁺ type silicon film 7e are sequentially formed. At this time, about the element substrate 10 which performed the upper gate insulation layer formation process shown in FIG. 9 (c), the semiconductor substrate formation process shown in FIG. 9 (d) is performed, maintaining in the vacuum atmosphere, and an element substrate Do not contact (10) with the atmosphere. Thereby, the amorphous silicon film 7d (active layer) can be laminated | stacked in the state in which the surface of the gate insulating layer 4 (upper gate insulating layer 4b) is clean.

Next, as shown in Fig. 9E, dry etching is performed on the amorphous silicon film 7d and the n ⁺ type silicon film 7e by using a photolithography technique to form an island-like semiconductor layer 7a. ) And an island-like n ⁺ -type silicon film 7e.

Next, in the upper electrode forming step shown in FIG. 9 (f), after forming an ITO film having a film thickness of 50 nm by the sputtering method, wet etching is performed on the ITO film using a photolithography technique to obtain the upper electrode. (5a) is formed. In this way, the holding capacitor 1h is formed.

Next, as shown in Fig. 9G, a metal film (laminated film of molybdenum film, aluminum film, and molybdenum film) is formed, and then patterned by using photolithography technology, so that the source line 6a and the drain electrode are formed. 6b and the upper electrode 6c are formed. Next, using the source line 6a and the drain electrode 6b as a mask, the n ⁺ type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to remove the source and drain. Is separated. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed to form ohmic contact layers 7b and 7c. In this way, the low gate pixel switching thin film transistor 1c is formed. Since the process after that is the same as that of Example 1, description is abbreviate | omitted.

As described above, in this embodiment, since the basic structure of the storage capacitor 1h is the same as that of the first embodiment, a highly reliable thin film transistor 1c can be formed, and a storage capacitor 1h having a high capacitance and a stable withstand voltage is formed. The same effect as in Example 1 can be obtained.

In addition, since the ITO film (transparent electrode) was used as the upper electrode 5a, the pixel aperture ratio can be increased as compared with the case where the extending portion of the drain electrode 6b is used as the upper electrode.

(Example 4)

10 (a) and 10 (b) are a plan view of one pixel of the liquid crystal device according to the fourth embodiment of the present invention and a cross-sectional view when the liquid crystal device is cut at a position corresponding to A4-B4. 11A to 11G are cross-sectional views illustrating the steps up to forming the source and drain electrodes in the manufacturing process of the element substrate 10 used in the liquid crystal device 1 of the present embodiment. In Fig. 10 (a), the pixel electrode is represented by a thick long dotted line, the gate line and the thin film formed at the same time are represented by a thin solid line, the source line and the thin film formed at the same time are represented by a thin single-dot chain line, and the semiconductor layer is represented by a thin and short dotted line. Indicates. The portion corresponding to the dielectric layer constituting the storage capacitor is represented by a thin double-dot chain line, and the contact hole is represented by a thin solid line like the gate line or the like. In addition, since the basic structure of this embodiment is the same as that of Example 1, the same code | symbol is attached | subjected to a common part and their description is abbreviate | omitted.

As shown in Figs. 10 (a) and 10 (b), also in this embodiment, in the element substrate 10 in the pixel region 1e enclosed by the gate line 3a and the source line 6a, as in the first embodiment, The lower gate type thin film transistor 1c and the storage capacitor 1h are formed. However, unlike Embodiments 1 to 3, in this embodiment, the planarization film is not formed, and the pixel electrode 2a is formed between the gate insulating layer 4 and the drain electrode 6b, and the drain electrode 6b. It is electrically connected to the drain electrode 6b by the partial overlap part with ().

The storage capacitor 1h is similar to the first embodiment in that the protruding portion from the capacitor line 3b is the lower electrode 3c. However, the upper electrode of the storage capacitor 1h is comprised by the part which overlaps planarly with the lower electrode 3c among the pixel electrodes 2a.

The gate insulating layer 4 has a two-layer structure of the lower gate insulating layer 4a composed of a thick silicon nitride film on the lower side and the upper gate insulating layer composed of a thin silicon nitride film on the upper side as in the first embodiment. It is. The lower gate insulating layer 4a is removed over the entire thickness direction in the region overlapping planarly with the lower electrode 3c and the pixel electrode 2a of the storage capacitor 1h, so that the opening 41 is formed. have. For this reason, the dielectric layer 4c of the storage capacitor 1h is comprised by the part (thin lower gate insulating layer 4a) of the thin film thickness among the gate insulating layers 4. As shown in FIG. An insulating film having the same thickness as the gate insulating layer 4 is formed along the edge of the lower electrode 3c among the upper layers of the lower electrode 3c, and the dielectric layer 4c is surrounded by the thick insulating film. Since the other structure is the same as that of Example 1, description is abbreviate | omitted.

In order to manufacture the element substrate 10 having such a configuration, after forming a metal film (lamination film of aluminum alloy film and molybdenum film) on the surface of the insulating substrate 11 in the gate electrode forming step shown in FIG. The metal film is patterned using photolithography technique to form the gate line 3a (gate electrode) and the capacitor line 3b (lower electrode 3c).

Next, a gate insulating layer forming step is performed. Also in this embodiment, in the lower gate insulating layer forming step shown in FIG. 11 (b) as in the first embodiment, a thick silicon nitride film constituting the lower layer side of the gate insulating layer 4 by the plasma CVD method (lower layer side). After the gate insulating layer 4a is formed, in the lower gate insulating layer etching step, the lower gate insulating layer 4a is etched to form the opening 41 at a position overlapping the lower electrode 3c. do. Next, in the upper gate insulating layer film forming step shown in FIG. 11C, a thin silicon nitride film (upper gate insulating layer 4b) constituting the upper layer side of the gate insulating layer 4 is formed.

Next, in the semiconductor layer forming step shown in FIG. 11D, the intrinsic amorphous silicon film 7d and the n ⁺ type silicon film 7e are sequentially formed. At this time, about the element substrate 10 which performed the upper-layer gate insulating layer formation process shown in FIG. 11 (c), the semiconductor substrate formation process shown in FIG. 11 (d) is performed, maintaining in the vacuum atmosphere, and an element substrate Do not contact (10) with the atmosphere. Thereby, the amorphous silicon film 7d (active layer) can be laminated | stacked in the state in which the surface of the gate insulating layer 4 (upper gate insulating layer 4b) is clean.

Next, as shown in FIG. 11E, dry etching is performed on the amorphous silicon film 7d and the n ⁺ -type silicon film 7e by using a photolithography technique to form an island-like semiconductor layer 7a. ) And an island-like n ⁺ -type silicon film 7e.

Next, in the pixel electrode formation process (upper electrode formation process) shown in FIG. 11 (f), after forming an ITO film, the ITO film is etched using photolithography technique to form the pixel 2a. In this way, the holding capacitor 1h is formed.

Next, as shown in Fig. 11G, a metal film (laminated film of molybdenum film, aluminum film, and molybdenum film) is formed, and then patterned by using photolithography technology, so that the source line 6a and the drain electrode are formed. 6b and the upper electrode 6c are formed. Subsequently, using the source line 6a and the drain electrode 6b as a mask, the n ⁺ type silicon film 7e between the source line 6a and the drain electrode 6b is removed by etching to remove the source and drain. Is separated. As a result, the n ⁺ -type silicon film 7e is removed from the region where the source line 6a and the drain electrode 6b are not formed to form ohmic contact layers 7b and 7c. In this way, the low gate pixel switching thin film transistor 1c is formed. Since the process after that is the same as that of Example 1, description is abbreviate | omitted.

As described above, in this embodiment, since the basic structure of the storage capacitor 1h is the same as that of the first embodiment, a highly reliable thin film transistor 1c can be formed, and a storage capacitor 1h having a high capacitance and a stable withstand voltage is formed. The same effect as in Example 1 can be obtained.

In addition, since a part of the pixel electrode 2a made of the ITO film (transparent electrode) was used as the upper electrode of the storage capacitor 1h, the pixel was compared with the case where the extending portion of the drain electrode 6b was used as the upper electrode. The aperture ratio can be increased.

(Example 5)

12A and 12B are a plan view of one pixel of the liquid crystal device according to the fifth embodiment of the present invention, and sectional views when the liquid crystal device is cut at positions corresponding to A5-B5. In FIG. 12A, the pixel electrode is represented by a thick long dotted line, the gate line and the thin film formed at the same time are represented by a thin solid line, the source line and the thin film formed at the same time are represented by a thin dashed line, and the semiconductor layer is represented by a thin and short dotted line. Indicates. The portion corresponding to the dielectric layer constituting the storage capacitor is represented by a thin double-dot chain line, and the contact hole is represented by a thin solid line like the gate line or the like. In addition, since the basic structure of this embodiment is the same as that of Example 1, the same code | symbol is attached | subjected to a common part and their description is abbreviate | omitted.

As shown in Figs. 12 (a) and 12 (b), also in this embodiment, in the element substrate 10, in the element region 10, the pixel region 1e surrounded by the gate line 3a and the source line 6a is formed. , The low gate type thin film transistor 1c and the storage capacitor 1h are formed. However, unlike Embodiments 1 to 4, in this embodiment, the capacitor line is not formed and the front end in the scanning direction (the direction intersecting the extension direction of the gate line 3a / the extension direction of the source line 6a). A part of the gate line 3a on the side constitutes the lower electrode 3c of the storage capacitor 1h.

In the storage capacitor 1h, the upper electrode 6d is formed in a region overlapping with the lower electrode 3c. In this embodiment, as the upper electrode 6d, the source line 6a and the drain electrode 6b. The metal layer formed simultaneously with is used. Here, the upper electrode 6d is formed separately from the drain electrode 6b. For this reason, the pixel electrode 2a formed in the upper layer of the planarization film 9 passes through the contact hole 81 of the passivation film 8, and the contact hole 91 of the planarization film 9, and the upper electrode 6d. Is electrically connected to the drain electrode 6b via the contact hole 82 of the passivation film 8 and the contact hole 92 of the planarization film 9.

The gate insulating layer 4 has a two-layer structure of the lower gate insulating layer 4a composed of a thick silicon nitride film on the lower side and the upper gate insulating layer composed of a thin silicon nitride film on the upper side as in the first embodiment. It is. The lower gate insulating layer 4a is removed over the entire thickness direction in the region overlapping planarly with the lower electrode 3c and the upper electrode 6d of the storage capacitor 1h, and the opening 41 is formed. . For this reason, the dielectric layer 4c of the storage capacitor 1h is comprised by the part (thin lower gate insulating layer 4a) of the thin film thickness among the gate insulating layers 4. As shown in FIG. An insulating film having the same thickness as the gate insulating layer 4 is formed along the edge of the lower electrode 3c among the upper layers of the lower electrode 3c, and the dielectric layer 4c is surrounded by the thick insulating film. Since the other structure is the same as that of Example 1, description is abbreviate | omitted.

The element substrate 10 of such a structure can be manufactured by the method similar to Example 1 fundamentally. That is, in the gate electrode forming step shown in FIG. 4A, the capacitor line is not formed and the gate line 3a is formed in the planar shape shown in FIG. 12A. In addition, when the source line 6a and the drain electrode 6b are formed in the source / drain electrode forming step shown in Fig. 4G, the upper electrode 6d is formed. In addition, in the planarization film formation process shown in FIG. 5 (b), the planarization film 9 provided with the contact holes 91 and 92 is formed, and also in the contact hole formation process shown in FIG. 5 (c), photolithography When etching the passivation film 8 using the technique, the contact holes 81 and 82 are formed at positions overlapping with the contact holes 91 and 92.

(Other Embodiments)

In the above embodiment, although both the lower gate insulating layer 4a and the upper gate insulating layer 4b constituting the gate insulating layer 4 are made of the same insulating film, the lower gate insulating layer 4a And the upper gate insulating layer 4b may be formed of different insulating films. In this case, when the gate insulating layer 4 is formed of a silicon oxide film and a silicon nitride film, the upper gate insulating layer 4b used as the dielectric layer 4c is preferably made of a silicon nitride film having a high dielectric constant. Further, in the above embodiment, the lower gate insulating layer 4a and the upper gate insulating layer 4b each consisted of one insulating film, but the lower gate insulating layer 4a and the upper gate insulating layer Each of 4b may be constituted of a plurality of insulating films.

In the above embodiment, in using the partially thinned portion of the gate insulating layer 4 as the dielectric layer 4c of the storage capacitor 1h, the lower layer side only in the inner region than the outer peripheral edge of the lower electrode 3c. Although the opening 41 is formed by removing the gate insulating layer 4a, when the withstand voltage drop that is likely to occur at the edge portion of the lower electrode 3c or the edge portion of the upper electrode is not a problem, or other measures are taken. If so, the lower gate insulating layer 4a may be removed over a region wider than the lower electrode 3c or the upper electrode.

In the above embodiment, a multilayer film of an aluminum alloy film and a molybdenum film is used for the gate line 3a, and a multilayer film of an aluminum film and a molybdenum film is used for the source line 6a, but other metal films can be used for these wirings. Or a conductive film such as a silicide film or the like may be used. In addition, although the intrinsic amorphous silicon film | membrane was used as the semiconductor layer 7a in the said Example, you may use another silicon film, transparent semiconductor films, such as an organic semiconductor film and a zinc oxide.

In addition, in the said embodiment, although the transmissive liquid crystal device was demonstrated to the example, you may apply this invention to a transflective liquid crystal device or a total reflection type liquid crystal device. In the above embodiment, the active matrix liquid crystal device of the TN mode, the ECB mode, and the VAN mode has been described as an example, but other modes such as an IPS (In-Plane Switching) mode may be applied to the liquid crystal device (electro-optical device) of the present invention. You may apply.

In addition to the liquid crystal device as the electro-optical device, for example, even in an organic EL (electroluminescence) device, the thin film transistor and the thin film transistor are electrically connected to each pixel region on the element substrate holding the organic EL film as the electro-optic material. Since the storage capacitor which has the connected pixel electrode and the lower electrode below the gate insulating layer of the said thin film transistor is formed, you may apply this invention to such organic electroluminescent apparatus.

(Example of an electronic device)

13 illustrates an embodiment in which the liquid crystal device according to the present invention is used as a display device of various electronic devices. The electronic apparatus shown here is a personal computer, a mobile phone, etc., and the display information output source 170, the display information processing circuit 171, the power supply circuit 172, the timing generator 173, and the liquid crystal device 1 Have Moreover, the liquid crystal device 1 has the panel 175 and the drive circuit 176, and the liquid crystal device 1 mentioned above can be used. The display information output source 170 includes a memory such as ROM (Read Only Memory), a random access memory (RAM), a storage device such as various disks, and the like, a tuning circuit for synchronously outputting a digital image signal, and the like. Based on the various clock signals generated by the generator 173, display information such as an image signal of a predetermined format is supplied to the display information processing circuit 171. FIG. The display information processing circuit 171 includes a variety of well-known circuits such as a series-parallel conversion circuit, an amplification and inversion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like, and executes processing of the inputted display information. The image signal is supplied to the drive circuit 176 together with the clock signal CLK. The power supply circuit 172 supplies a predetermined voltage to each component.

According to the present invention described above, an electro-optical device, an electronic device capable of suppressing a variation in capacitance of a storage capacitor and a drop in the breakdown voltage of the storage capacitor, even when a portion in which the gate insulating layer is partially thinned as the dielectric layer of the storage capacitor, and It is possible to provide a method for producing an electro-optical device.

Claims (11)

A thin film transistor in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked in each of a plurality of pixel regions on the element substrate; A pixel electrode electrically connected to a drain region of the thin film transistor; A storage capacitor having opposing lower and upper electrodes with the gate insulating layer interposed therebetween; Provided with In the thin film transistor, the gate electrode, the gate insulating layer, and the semiconductor layer are stacked in this order from a lower layer side, The gate insulating layer has a lower gate insulating layer composed of one layer to a plurality of insulating films, and an upper gate insulating layer composed of one layer to a plurality of insulating films, The lower gate insulating layer is formed to a thickness that reduces the parasitic capacitance of the thin film transistor, and is removed at a portion overlapping with the lower electrode and the upper electrode. The upper electrode is a transparent electrode formed on the gate insulating layer and connected to the drain electrode. Electro-optical device, characterized in that. The method of claim 1, The upper gate insulating film is formed thinner than the lower gate insulating film. The method according to claim 1 or 2, The lower gate insulating layer is composed of one insulating film, and the upper gate insulating layer is composed of one insulating film. The method according to claim 1 or 2, And said semiconductor layer is made of an amorphous silicon film. The method according to claim 1 or 2, And the upper gate insulating layer is formed of a silicon nitride film. The method according to claim 1 or 2, And the upper electrode is a portion extending from the drain electrode of the thin film transistor to a region facing the lower electrode. The method according to claim 1 or 2, And the upper electrode is a transparent electrode electrically connected to the drain electrode of the thin film transistor. The method according to claim 1 or 2, And the upper electrode is a portion of the pixel electrode that faces the lower electrode. An electronic apparatus comprising the electro-optical device according to claim 1 or 2. A thin film transistor in which a gate electrode, a gate insulating layer, and a semiconductor layer are stacked on each of the plurality of pixel regions on the element substrate, a pixel electrode electrically connected to a drain region of the thin film transistor, and the gate insulating layer are opposed to each other. In the manufacturing method of the electro-optical device which has the storage capacitance provided with the lower electrode and the upper electrode to A gate electrode forming step of simultaneously forming the gate electrode with the lower electrode; A gate insulating layer forming step of forming the gate insulating layer; An upper electrode forming step of forming an upper electrode formed of a transparent electrode connected to the drain electrode on an upper layer of the gate insulating layer; Semiconductor layer forming process of forming the semiconductor layer Provided with In the gate insulating layer forming step, A lower gate insulating layer forming step of forming an insulating film of one layer to a plurality of layers, wherein the lower layer side of the gate insulating layer is formed to a thickness that decreases the parasitic capacitance of the thin film transistor; A lower gate insulating layer etching step of removing portions of the insulating film formed in the lower gate insulating layer forming step from overlapping with the lower electrode; Performing an upper gate insulating layer forming step of forming an insulating film of one layer to a plurality of layers constituting an upper layer side of the gate insulating layer The manufacturing method of the electro-optical device characterized by the above-mentioned. The method of claim 10, A method of manufacturing the electro-optical device, wherein the upper gate insulating layer forming step and the semiconductor layer forming step are performed continuously while maintaining the element substrate in a vacuum atmosphere.

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