KR100861209B1 - Semiconductor device having sub word line driver - Google Patents

Abstract

A semiconductor device including a sub-word line driver is provided to prevent previously latent failure caused by damage of a gate. A predetermined lower structure is formed on a semiconductor substrate. A first active region(14) is defined by an isolation layer(12) within the semiconductor substrate. A gate(16) is formed across the first active region and receives an inverse pre-decoding signal. A first contact plug(18) is formed to connect the gate with a first metal line. A second contact plug(20) is formed to connect the first metal line with a second metal line. A second active region(22) is electrically connected to the first metal line. The second active region is connected to the first metal line through a third metal line(24).

Description

Semiconductor device having a sub word line driver

1A and 1B are photographic diagrams illustrating a failure analysis result of a small block fail in a general semiconductor memory device.

FIG. 1C is a photograph showing that damage occurs to a gate oxide film formed under a gate of a failed NMOS transistor in a general semiconductor memory device, and thus the physical property of the gate oxide material has a conductor property.

2 is a circuit diagram illustrating a sub word line driver according to the present invention.

3A and 3B are diagrams illustrating an NMOS transistor NT2 to which an inverted pre-decoding signal FXBi of a general sub word line driver is input.

<Description of the symbols for the main parts of the drawings>

MWL: Main Word Line

SWL: sub word line

PT: PMOS transistor

NT1, NT2: NMOS transistor

RD: reverse bias diode

FXi: pre-decoded signal

FXBi: Inverted pre-decoded signal

12: device isolation film

14: active area

16: gate

18, 20, 24: contact plug

22: N + active area

The present invention relates to a semiconductor device, and more particularly, to a sub word line driver capable of preventing plasma induced damage (PID).

In general, efforts are being made in various directions to store more information in a small area in accordance with high integration and high speed of semiconductor devices.

In particular, the design and layout of circuits and the implementation of new circuits have achieved the goal of high integration, low power, and high speed of semiconductor devices.

In the early stages of the development of semiconductor devices, the area occupied by the peripheral circuits in the semiconductor device was relatively larger than that of the cell array in the core region. However, according to the development trend of the semiconductor device, the cell array area is gradually occupying most of the semiconductor devices. . This trend will be even more pronounced in the gigabit era.

In addition, in accordance with the trend toward higher integration of semiconductor devices, reduction of power consumption of semiconductor devices has emerged as an important design element in terms of improving chip reliability.

In terms of reducing power consumption, when a power supply of a semiconductor device is lowered, a loss of a data signal due to noise occurs in a circuit. At this time, the potential of the core voltage is not significantly lowered, but the potential is lowered due to the threshold voltage caused by the cell transistor, which causes serious problems such as loss of the data signal. In order to solve the lowering of the supply voltage due to the threshold voltage and noise, a word line voltage driving circuit having a supply voltage higher than the supply voltage has been studied.

In general, a semiconductor device has a plurality of word lines, and the word lines are formed of polysilicon or polycide having a relatively high resistance. Therefore, since most word lines are narrow and long, and have a very large resistance, when a data is read or written, a cell driving voltage at a row decoder is transferred to a memory cell far from the row decoder. A delay in proportion to the product of the capacitance of the line and the resistance, that is, an RC delay occurs, causes the speed characteristic of the semiconductor device to decrease.

In order to solve this problem, a memory device having a hierarchical word line structure has been proposed in 256M DRAM or more. have.

First, one of the row decoders is enabled in the same column by column address information, which is an external input signal, to enable the main word line connected to the row decoder. Subsequently, one of the coding lines is enabled by row address information which is an external input signal. Therefore, the corresponding main word line enabled by the row decoder and the coding signal through the coding line are activated to activate the corresponding sub word line driver, and the sub word line connected to the sub word line driver is activated to recover the data of the memory cell. Read or write external data to the cell.

As described above, the semiconductor memory device employing the hierarchical word line structure has a sub word line driver used instead of the word trap technology, so that the gap between the metal lines used as the main word lines is sufficiently secured, thereby making the metal process easier. The yield of the semiconductor memory can be increased.

1A and 1B are photographic diagrams illustrating a failure analysis result of a small block fail in a general semiconductor memory device. Here, FIG. 1A illustrates an aspect of being charged up at a bit line level, and FIG. 1B illustrates an aspect of being charged up at a gate level.

Referring to FIG. 1B, it can be seen that the gate of the NMOS transistor to which the inverted pre-decoded signal of the sub word line driver is applied is charged up on the FIB image.

At this time, the gate is not insulated by the gate oxide layer and is electrically connected to the substrate, and there is a leakage current between the gate and the substrate.

FIG. 1C is a photograph showing that damage occurs to a gate oxide film formed under a gate of a failed NMOS transistor in a general semiconductor memory device, and thus the physical property of the gate oxide material has a conductor property. Here, (i) is a photograph showing a cross section, and (ii) is an enlargement of the failing part of (i).

Therefore, it is interpreted that the corresponding NMOS transistors are abnormally operated and all of the sub word lines are determined to be fail and thus fail in the form of a block fail.

This block failure is impossible to repair, so the entire chip is treated as defective and fatal to the yield.

The cause of the failure can be found in the layout of the sub word line driver. The gate input of the gate damaged NMOS transistor is connected to the first metal line (or bit line) via a contact plug. The first metal line is connected to the second metal line through a contact plug.

Here, when the first metal line is deposited with an interlayer insulating film formed of high density plasma (HDP), which is performed to electrically insulate the subsequent conductor, charges are unbalanced by high plasma, which is induced. In this case, electric flow does not occur, and charge is locally concentrated on the gate oxide to cause oxide degradation.

The present invention provides a sub word line driver capable of preventing a decrease in yield due to block failure by connecting a reverse bias diode to a gate input terminal of an NMOS transistor to which an inverted pre-decoded signal of a sub word line driver is input. It aims to do it.

A semiconductor device having a hierarchical word line structure implemented by a main word line and a sub word line, and including a sub word line driver for driving the sub word line,

The sub word line driver,

A switching element for inputting an inverted pre-decoded signal to an input terminal to selectively connect the sub word line to ground; And

And a reverse bias diode connected between the input terminal of the switching element and the back bias voltage terminal.

In addition, the switching device

A semiconductor substrate on which a predetermined lower structure is formed;

A first active region defined by an isolation layer in the semiconductor substrate;

A gate formed to intersect the first active region and to receive the inverted pre-decoded signal;

A first contact plug connecting the gate to a first metal line;

A second contact plug connecting the first metal line to the second metal line; And

And a second active region electrically connected to the first metal line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

The present invention discloses a sub word line driver for preventing plasma induced damage (PID). That is, the sub word line driver according to the present invention connects a reverse bias diode to the gate terminal of the NMOS transistor to which the inverted pre-decoding signal FXB is input, thereby forming an electric charge introduced when the interlayer insulating film is formed by the HDP process. In the process of neutralizing the charge, a current flow is formed in the reverse bias diode to prevent the gate oxide damage.

2 is a circuit diagram illustrating a sub word line driver according to the present invention.

The sub word line driver applies the PMOS transistor PT for selectively applying the pre-decoding signal FXi (i = 0 to 7) to the sub word line SWL according to the potential of the main word line MWL, and the sub word line SWL according to the potential of the main word line MWL. Transistor NT1 selectively connects Vss to ground Vss, gate terminal and back of NMOS transistor NT2 and NMOS transistor NT2 selectively connect subword line SWL to ground Vss according to inverted pre-decode signal FXBi (i = 0-7) A reverse bias diode RD formed between the bias voltages Vbb. Here, the back bias voltage Vbb is applied to the body of the NMOS transistors NT1 and NT2 to adjust the threshold voltage.

3A and 3B are diagrams illustrating an NMOS transistor NT2 to which a PMOS transistor PT, an NMOS transistor NT1, and an inverted pre-decode signal FXBi are input in a general sub word line driver. 3A is a layout diagram illustrating two sub wordline drivers, and FIG. 3B is a cross-sectional view taken along line AA ′ of the subwordline driver of FIG. 3A.

The NMOS transistor NT2 is connected to the gate 16 via an active region 14 defined by the device isolation film 12, a gate 16 formed to cross the active region 14 up and down, and a contact plug 18. It includes a first metal line M0. Here, the first metal line M0 is connected to the second metal line (not shown) through the contact plug 20.

In addition, an N + active region 22 is further formed adjacent to the gate region where the contact plug 18 for connecting the first metal line M0 to the gate 16 is formed. Here, the N + active region 22 is connected to the first metal line M0 through the contact plug 24.

At this time, the N + active region 22 forms an N + / P reverse bias diode together with the P-type semiconductor substrate to insulate the interlayer insulating layer by the HDP process to insulate the first metal line M0 and the conductor formed thereafter. When forming, the charge imbalance formed by the high-density plasma can form an electron flow as shown in the arrow direction shown in FIG. 3B to prevent deterioration of the gate oxide film.

As described above, the present invention proposes a sub word line driver structure for preventing PID damage. The basic principle is to form a reverse bias diode at the gate input terminal of the NMOS transistor NT2 to which the inverted pre-decoding signal FXBi to which a fail occurs is input. will be. Therefore, the electric current flows smoothly through the reverse bias diode during the neutralization process of the charges introduced by the HDP process for forming the interlayer insulating film, thereby preventing damage to the gate oxide film.

In addition, the present invention can fundamentally eliminate the block failure caused by the PID damage, thereby improving the direct yield. In addition, it is possible to improve the reliability of the semiconductor device with a structure that can prevent potential failures (failures due to additional gate damage degradation after B / I, such as a TDBI system) due to gate damage.

According to the present invention, a reverse bias diode is connected to a gate input terminal of an NMOS transistor to which an inverted pre-decoded signal of a sub word line driver is input, thereby preventing a decrease in yield due to block failure.

In addition, the present invention has the effect of improving the reliability of the semiconductor device in a structure that can prevent the potential failure by the gate damage in advance.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

A semiconductor device having a hierarchical word line structure implemented by a main word line and a sub word line, and including a sub word line driver for driving the sub word line, The sub word line driver, A switching element for inputting an inverted pre-decoded signal to an input terminal to selectively connect the sub word line to ground; And And a reverse bias diode connected between the input terminal of the switching element and the back bias voltage terminal. The method of claim 1, wherein the switching device A semiconductor substrate on which a predetermined lower structure is formed; A first active region defined by an isolation layer in the semiconductor substrate; A gate formed to intersect the first active region and to receive the inverted pre-decoded signal; A first contact plug connecting the gate to a first metal line; A second contact plug connecting the first metal line to a second metal line; And And a second active region electrically connected to the first metal line. The method of claim 2, And the second active region is connected to the first metal line through a third contact plug. The method of claim 2, And wherein the second active region is doped with a conductor material that is out of phase with the semiconductor substrate. The method of claim 4, wherein Wherein the semiconductor substrate is doped with a P-type impurity, and the second active region is doped with an N + -type impurity.

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